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<p class="MsoNormal"><span style="color:#002060">Hi experts,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">I have a virtual device model plugged into VirtualBox 5.1.24 OSE via PDM, and I am seeing a problem with the ICH9 fake BIOS support of prefetch space. Or maybe that’s not the right way to put it. Let me explain
what I’m trying to do and then my problem.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">I actually have two different virtual device models. The first has a PCIe switch plugged into host bus at 0:28:0, with secondary bus connected to an endpoint at 3:0:0. The endpoint has two 64-bit BAR pairs,
both with the prefetch flag set, but they’re small. The fake BIOS enumerates, sets up the endpoint BARs and the bridge’s prefetch-base/limit registers which I then use to register the address range with PDMDevHlpMMIORegister(). This model works well.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">The second model has a PCI/PCIe switch inserted, so a bridge at 0:28:0, another at 3:0:0, another at 4:0:0, and the endpoint at 5:0:0. This endpoint also has two 64-bit BAR pairs, both with the prefetch flag
set, one big one small. When I try to register the address ranges with PDMDevHlpMMIORegister() it returns VERR_MM_HYPER_NO_MEMORY.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">First question is whether this is indeed the right way to get those address redirected through PDM to my model? It seems to lead to memory allocation, which I don’t need since the memory is modeled in my virtual
device. I just need to take care of accesses within the range assigned by the fake BIOS.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">Second question is whether someone can elaborate on this comment in ich9pciBiosInitDeviceBARs()?
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"> /* Hack: since this PCI init code cannot handle prefetchable BARs on<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"> * anything besides the primary bus, it's for now the best solution<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"> * to leave such BARs uninitialized and keep memory transactions<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"> * disabled. The OS will hopefully be clever enough to fix this.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"> * Prefetchable BARs are the only ones which can be truly big (and<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"> * are almost always 64-bit BARs). The non-prefetchable ones will not<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"> * cause running out of space in the PCI memory hole. */<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">It is programming the prefetch-base/limit registers of all the bridges, so in what way can the PCI init code not “handle prefetchable BARs on anything besides the primary bus”? In what way can we hope the OS
will be “clever enough to fix this”? The lspci –vv command shows valid address ranges, based on the base/limit registers, but the BARs won’t respond if accessed. And is there an issue with PCI addresses above 4G?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">I will keep digging and learning, because I don’t yet understand the connection between this and VERR_MM_HYPER_NO_MEMORY — which I believe comes from mmHyperAllocInternal() — but some insight would be helpful.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060">// RicV<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#002060"><o:p> </o:p></span></p>
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