<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: Times New Roman; font-size: 12pt; color: #000000'><style>p { margin: 0; }</style><div><div style="font-family: Times New Roman; font-size: 12pt; color: #000000"><br> Hi Ananth,<br><br> PCIDevSetDWord in the device won't do it, that's expected. It will get rewritten.<br><br> I don't think VirtualBox supplies any device with so many BARs so it's entirely possible that something isn't working. The trouble is that you have your code + ours, and we only have our code, so it's quite hard for us to debug the problem.<br><br> One hint... what happens if you switch your VM to use EFI instead of the classic BIOS? I believe EFI should initialize all the PCI resources itself, so you might be able to see what happens even before an OS boots.<br><br> And two more comments. I see that you have both the VirtualBox VGA device and your own. No one can tell you for certain that that won't cause problems. And you presumably want to use MSIs (otherwise you wouldn't bother with ICH9), but you're using quite old version of VirtualBox. There were several fixes in the MSI handling area in VirtualBox 5.0.<br><br> Regards,<br> Michal<br><br>----- Original Message -----<br>From: apallapothu@gmail.com<br>To: klaus.espenlaub@oracle.com<br>Cc: vbox-dev@virtualbox.org<br>Sent: Tuesday, August 18, 2015 9:04:05 PM GMT +01:00 Amsterdam / Berlin / Bern / Rome / Stockholm / Vienna<br>Subject: Re: [vbox-dev] ICH9 BAR5 access<br><br><div dir="ltr">Hi Klaus, <div><br></div><div> Thanks for the response. </div><div><br></div><div> In the PCIe config space I set all BAR's to 0, using PCIDevSetDWord .... no address mapping from myside. </div><div> I first register the region using PDMDevHlpPCIIORegionRegister with respective size.</div><div> BAR0 = 0x800,0000 128 M</div><div> BAR5 = 0x4,0000 256K</div><div> Then I register memory call backs using PDMDevHlpMMIORegister for the size.</div><div><br></div><div> While experimenting, I played with different base address in DevPciIch9.cpp "pGlobals->uPciBiosMmio = UINT32_C(0xB8000000);" which moved BAR's accordingly.</div><div><br></div><div> While experimenting, I have tried setting start address for BAR's in PCIe config space, I saw that this address eventually gets overwritten by FakeBIOS and then OS.</div><div> </div><div> When I ran lspci on the guest I did not see conflict in address mapping. Attached lspci output. My pass through device shows up under VGA. </div><div> I have added lspci output of fully functional PIIX3 chipset for comparison. </div><div><br></div><div> At the end of the attachment, please note the VM debugger output in ICH9 chip set which apparently doesn't see the VGA device. </div><div><br></div><div> Just to keep my message crisp, with the same device code, in PIIX3 I am able to see memory access to the addresses specified in BAR0, BAR5 while in ICH9, I only see access coming through in BAR0 and NOT BAR5. </div><div><br></div><div>Thanks.</div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Aug 18, 2015 at 2:25 PM, Klaus Espenlaub <span dir="ltr"><<a href="mailto:klaus.espenlaub@oracle.com" target="_blank">klaus.espenlaub@oracle.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>
Hi Ananth,<span class=""><br>
<br>
<div>On 18.08.2015 20:04, Ananth Pallapothu
wrote:<br>
</div>
<blockquote>
<div dir="ltr">Hello Experts,
<div><br>
</div>
<div> <span style="font-family:Calibri;font-size:11pt">I have
added new
pass through device to the VirtualBox setup . Registered all
6 BAR's with
appropriate sizes, none exceeding 256M. All BAR's were set
to reflect hardware
functionality (assigned 0), eventually OS programmed base
address regions with
the sizes I have registered them with.</span></div>
</div>
</blockquote></span>
Can you provide more details (how you map the regions initially and
on remap)? Hard to say what's happening otherwise.<span class=""><br>
<blockquote>
<div dir="ltr">
<p style="margin:0in;font-family:Calibri;font-size:11.0pt">My
fundamental
problem is, I have been able to access BAR0 and NOT BAR5. I
tried playing with
BIOSmmio address setting in DevPciIch9, that made difference
in relocating
BAR's but functionality remained the same (Not able to access
BAR5)</p>
<p style="margin:0in;font-family:Calibri;font-size:11.0pt">Interesting
part is,
PIIX3 chipset is fully functional ie., can access BAR5 in
PIIX3 but NOT in
ICH9. <br>
</p>
</div>
</blockquote></span>
Could be that with PIIX3 there's no remap and with ICH9 there's a
remap... really difficult to say anything with the sparse
information.<span class="HOEnZb"><font color="#888888"><br>
<br>
Klaus</font></span><span class=""><br>
<blockquote>
<div dir="ltr">
<p style="margin:0in;font-family:Calibri;font-size:11.0pt"><br>
</p>
<p style="margin:0in;font-family:Calibri;font-size:11.0pt">PS:
There seems to be some problem with my email ID, so not sure
whether my last email came through. Sorry if you have already
received it. </p>
<p style="margin:0in;font-family:Calibri;font-size:11.0pt"><br>
</p>
<p style="margin:0in;font-family:Calibri;font-size:11.0pt">Thanks.</p>
</div>
<br>
</blockquote>
</span></div>
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