<div dir="ltr">Yo,<br><br>I'm working on a kernel project in which I am currently
attempting to get IO-APIC support working in Virtual Box. I say "in
Virtual Box", because the my code works everywhere else -- on all of the
real hardware test cases I have (2 laptops), the Bochs emulator, Qemu
and VMWare Player.<br><br>The exact description is as follows. When
using the i8259 PIC IRQ controllers, I am able to program the i8254 PIT
timer to interrupt periodically, and my kernel receives IRQs as
expected, and the rate/frequency of the IRQs is as programmed. My timer
API successfully times delays of any granularity supported by the i8254
PIT.<br><br>However, when I attempt to switch the chipset from "PIC"
mode to "Symmetric I/O" mode (and use the IO-APICs), the timer interrupt
does not come in as expected. I have checked as many assumptions as
possible.<br><ul><li> The i8254 PIT timer works as programmed, and to
the exact frequency programmed when I am using the i8259 PIC IRQ routing
system. The i8254 PIT driver is not the problem.</li><li> The ACPI MADT
table does not allow for an "enabled" flag in the IO-APIC entry
structure, so it cannot be that I am enabling IO-APICs that the Virtual
Box firmware has marked as "unusable". In any case, Virtual Box's
firmware only reports one IO-APIC.</li><li> I have programmed the
IO-APIC's pins as detailed by the ACPI MADT's ISA IRQ Override entry
structures. There are two ISA IRQ Override entries in the Virtual Box
MADT. The first maps ISA IRQ 0 to ACPI Global System Interrupt 2 (with
default edge-triggering and rising edge, as expected for ISA), and the
second is an override for ISA IRQ pin 9 which just maps ISA-IRQ-9 to
GSI-9 with a level triggering override. I've programmed the IO-APIC pins
as specified.</li><li> The pins on the IO-APIC are set to all interrupt the same CPU: CPU0, and dumping the pin-states confirms this.</li><li>
The pins on the IO-APIC are all set to interrupt on CPU interrupt
vectors starting at vector 32 (since vectors 0-31 are reserved for
exceptions by Intel). Pin 0 interrupts on vector 32, pin 1 interrupts on
vector 33, and so on. This has been confirmed with a read-out and dump
of the pins.</li><li> When trying to unmask ISA-IRQ-0, I correctly
unmask GSI 2, since the ACPI MADT in Virtual Box overrides ISA-IRQ-0 to
be mapped to GSI-2. (In desperation, I also unmasked GSI-0, and even
unmasked all of the IO-APIC pins, all to no avail: no IRQs come in still
when I am trying to use the IO-APICs.)</li><li> The Local APIC units
are probably not the problem, since I can send INIT and STARTUP IPIs to
them to boot AP CPUs -- they receive IPI interrupts successfully in
Virtual Box.</li></ul><br>I'd like to repeat that this code works on
real hardware, in Bochs, Qemu, and VMware Player. Could I have some
pointers? I am aware for example, that Linux also had problems getting
IO-APICs working on Virtual Box at some point (According to <a href="http://www.virtualbox.org/manual/ch12.html#ts_linux-buggy">http://www.virtualbox.org/manual/ch12.html#ts_linux-buggy</a>). I've checked
as many assumptions as I possibly can, including trying to use the ICH9
chipset instead of the PIIX3 chipset, and trying different Guest OS
machine configurations in the settings for my virtual machine (tried all
of them in the "Linux" series and "Windows" series).<br><br>Please feel
free to ask me any questions, or ask me for any information you see
fit. The only reason I haven't completely dismissed this as a bug in
Virtual Box's IO-APIC code is that Linux (eventually, after patching the
kernel) was able to get IO-APICs working in Virtual Box. Could any of
the developers, or knowledgeable users provide any information on what
exactly the eccentricity in the Virtual Box IO-APIC implementation (if
any) actually is? I can provide ISO images of the kernel in question (I
would be very, very grateful if someone is willing to trace my kernel in
Virtual Box), and I am also willing to provide source code for the
IO-APIC setup, if needed (the project is actually open-sourced, GPV2
licensed. However, I'm hesitant to publicly link to it for now, because I
am still pretty far from "first release"). I'd prefer to have this
project work in all emulators if possible.<br><br>--Thanks a lot,<br>latentprion</div>