[vbox-dev] Arrangement of EPT structures with SMP

[Tom Birch]

I'm looking through the page management code, specifically hardware
acceleration on Intel with EPT, and I can't quite figure out the
high-level relationships between various structures. Both the VMCS and
EPTP seem to be per-PVMCPU data structures, does this mean that within
a single VM, you can have multiple distinct EPTPs (on different
VCpus), or is this arrangement just a consequence of the way shadow
paging worked before EPT? Put another way, can I guarantee that all
VCpus within a single VM will all share the same EPTP? I'm mainly
concerned about how this applies to Darwin if that matters, but I
seems like a fairly Host-OS-agnostic feature.

cheers,
Tom