; $Id: bs3-cpu-instr-2-template.mac 104000 2024-03-22 15:37:38Z vboxsync $ ;; @file ; BS3Kit - bs3-cpu-instr-2 assembly template. ; ; ; Copyright (C) 2007-2023 Oracle and/or its affiliates. ; ; This file is part of VirtualBox base platform packages, as ; available from https://www.virtualbox.org. ; ; This program is free software; you can redistribute it and/or ; modify it under the terms of the GNU General Public License ; as published by the Free Software Foundation, in version 3 of the ; License. ; ; This program is distributed in the hope that it will be useful, but ; WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ; General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, see . ; ; The contents of this file may alternatively be used under the terms ; of the Common Development and Distribution License Version 1.0 ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included ; in the VirtualBox distribution, in which case the provisions of the ; CDDL are applicable instead of those of the GPL. ; ; You may elect to license modified versions of this file under the ; terms and conditions of either the GPL or the CDDL or both. ; ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0 ; ;********************************************************************************************************************************* ;* Header Files * ;********************************************************************************************************************************* %include "bs3kit-template-header.mac" ; setup environment ;********************************************************************************************************************************* ;* Defined Constants And Macros * ;********************************************************************************************************************************* ;; ; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function ; with an instruction length byte. ; ; ASSUMES the length is between the start of the function and the .again label. ; %ifndef BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED %define BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED %macro BS3CPUINSTR2_PROC_BEGIN_CMN 1 align 8, db 0cch db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1) BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR %endmacro %endif ;; ; For defining simple instruction test. %ifndef BS3CPUINSTR2_EMIT_INSTR_UD2_DEFINED %define BS3CPUINSTR2_EMIT_INSTR_UD2_DEFINED %macro BS3CPUINSTR2_EMIT_INSTR_UD2 2+ BS3CPUINSTR2_PROC_BEGIN_CMN %1 %2 .again: ud2 jmp .again BS3_PROC_END_CMN %1 %endmacro %endif ;; ; @param 1 The instruction menmonic. ; @param 2 Whether there are both an 8-bit form and a 16/32-bit immediate form of the instruction (1) or not 0. ; @param 3 Mask describing the immediate forms. Bit 0 = imm8; Bit 2 = immV. ; @param 4 Whether there are alternative forms of the instruction. ; @param %ifnmacro BS3CPUINSTR2_BINARY_OP 4 %macro BS3CPUINSTR2_BINARY_OP 4 %if %2 != 0 ; 8-bit BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _dl, %1 al, dl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch %+ _bh, %1 ch, bh BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl %+ _ah, %1 dl, ah BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _ah, %1 [xBX], ah BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _bl, %1 [xDI], bl %if %3 & 3 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _Ib, %1 al, 0x7f BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cl %+ _Ib, %1 cl, 0x7f BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dh %+ _Ib, %1 dh, 0x7f BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _Ib, %1 byte [xDI], 0x7f %endif %if %4 != 0 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl %+ _DSxBX, %1 dl, [xBX] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch %+ _DSxBX, %1 ch, [xBX] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dh %+ _cl, ALT_INSTRUCTION8_ %+ %1 dh, cl %endif %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _sil %+ _dil, %1 sil, dil BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9b %+ _r8b, %1 r9b, r8b BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _r13b, %1 al, r13b BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx14 %+ _r11b, %1 [r14], r11b %if %3 & 3 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8b %+ _Ib, %1 r8b, 0x7e BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14b %+ _Ib, %1 r14b, 0x7e BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx13 %+ _Ib, %1 byte [r13], 0x7e %endif %if %4 != 0 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r11b %+ _DSx12, %1 r11b, [r12] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dl %+ _r14b, ALT_INSTRUCTION8_ %+ %1 dl, r14b BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r8b %+ _bl, ALT_INSTRUCTION8_ %+ %1 r8b, bl %endif %endif %endif ; 16-bit BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _di %+ _si, %1 di, si BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cx %+ _bp, %1 cx, bp BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _si, %1 [xDI], si BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _ax, %1 [xBX], ax %if %3 & 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ax %+ _Ib, %1 ax, strict byte 0x7f BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _si %+ _Ib, %1 si, strict byte 0x7f BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxDI %+ _Ib, %1 word [xDI], strict byte 0x7f %endif %if %3 & 2 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ax %+ _Iw, %1 ax, 0x7f01 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bx %+ _Iw, %1 bx, 0x7f01 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _Iw, %1 word [xBX], 0x7f01 %endif %if %4 != 0 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _si %+ _DSxDI, %1 si, [xDI] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ax %+ _DSxBX, %1 ax, [xBX] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _bp %+ _bx, ALT_INSTRUCTION16_ %+ %1 bp, bx %endif %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _cx, %1 r8w, cx BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r15w %+ _r10w, %1 r15w, r10w BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx15 %+ _r12w, %1 [r15], r12w %if %3 & 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _Ib, %1 r8w, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r12w %+ _Ib, %1 r12w, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSx14 %+ _Ib, %1 word [r14], strict byte 0x77 %endif %if %3 & 2 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _Iw, %1 r8w, 0x7788 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13w %+ _Iw, %1 r13w, 0x7788 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx11 %+ _Iw, %1 word [r11], 0x7788 %endif %if %4 != 0 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9w %+ _DSx8, %1 r9w, [r8] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r13w %+ _ax, ALT_INSTRUCTION16_ %+ %1 r13w, ax BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _si %+ _r9w, ALT_INSTRUCTION16_ %+ %1 si, r9w %endif %endif ; 32-bit BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _ebx, %1 eax, ebx BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _ebp, %1 ecx, ebp BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _edx %+ _edi, %1 edx, edi BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _esi, %1 [xDI], esi BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _eax, %1 [xBX], eax %if %3 & 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _Ib, %1 eax, strict byte 0x7f BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _Ib, %1 ecx, strict byte 0x7f BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxDI %+ _Ib, %1 dword [xDI], strict byte 0x7f %endif %if %3 & 2 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _Id, %1 eax, 0x7f011234 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ebp %+ _Id, %1 ebp, 0x7f011234 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxSI %+ _Id, %1 dword [xSI], 0x7f011234 %endif %if %4 != 0 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _DSxBX, %1 eax, [xBX] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ebp %+ _DSxDI, %1 ebp, [xDI] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _edi %+ _esi, ALT_INSTRUCTION32_ %+ %1 edi, esi %endif %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _r8d, %1 eax, r8d BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9d %+ _ecx, %1 r9d, ecx BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13d %+ _r14d, %1 r13d, r14d BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx10 %+ _r11d, %1 [r10], r11d %if %3 & 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8d %+ _Ib, %1 r8d, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r11d %+ _Ib, %1 r11d, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSx15 %+ _Ib, %1 dword [r15], strict byte 0x77 %endif %if %3 & 2 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8d %+ _Id, %1 r8d, 0x778899aa BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14d %+ _Id, %1 r14d, 0x778899aa BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx12 %+ _Id, %1 dword [r12], 0x778899aa %endif %if %4 != 0 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14d %+ _DSx12, %1 r14d, [r12] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15d %+ _esi, ALT_INSTRUCTION32_ %+ %1 r15d, esi BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _eax %+ _r10d, ALT_INSTRUCTION32_ %+ %1 eax, r10d %endif %endif ; 64-bit %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _rbx, %1 rax, rbx BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _rax, %1 r8, rax BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rdx %+ _r10, %1 rdx, r10 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _rax, %1 [rbx], rax BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx12 %+ _r8, %1 [r12], r8 %if %3 & 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _Ib, %1 rax, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rbp %+ _Ib, %1 rbp, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _Ib, %1 r8, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r11 %+ _Ib, %1 r11, strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxSI %+ _Ib, %1 qword [rsi], strict byte 0x77 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx8 %+ _Ib, %1 qword [r8], strict byte 0x77 %endif %if %3 & 2 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _Id, %1 rax, 0x778899aa BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _Id, %1 r8, 0x778899aa BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rbx %+ _Id, %1 rbx, 0x778899aa BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14 %+ _Id, %1 r14, 0x778899aa BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx12 %+ _Id, %1 qword [r12], 0x778899aa %endif %if %4 != 0 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _DSxBX, %1 rax, [rbx] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _DSx12, %1 r8, [r12] BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15 %+ _rsi, ALT_INSTRUCTION64_ %+ %1 r15, rsi BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _rbx %+ _r14, ALT_INSTRUCTION64_ %+ %1 rbx, r14 %endif %endif %endmacro ; BS3CPUINSTR2_BINARY_OP %endif ;; ; @param 1 The instruction menmonic. %ifnmacro BS3CPUINSTR2_SHIFT_OP 1 %macro BS3CPUINSTR2_SHIFT_OP 1 ; 8-bit BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _1, %1 al, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl %+ _Ib, %1 dl, 7 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch %+ _cl, %1 ch, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxBX %+ _1, %1 byte [xBX], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxDI %+ _Ib, %1 byte [xDI], 6 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxSI %+ _cl, %1 byte [xSI], cl %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _sil %+ _1, %1 sil, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9b %+ _Ib, %1 r9b, 5 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13b %+ _cl, %1 r13b, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSx14 %+ _1, %1 byte [r14], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxAX %+ _Ib, %1 byte [rax], 4 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSx9 %+ _cl, %1 byte [r9], cl %endif ; 16-bit BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _di %+ _1, %1 di, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cx %+ _Ib, %1 cx, 15 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bp %+ _cl, %1 bp, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxSI %+ _1, %1 word [xSI], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxDI %+ _Ib, %1 word [xDI], 14 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxBX %+ _cl, %1 word [xBX], cl %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _1, %1 r8w, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9w %+ _Ib, %1 r9w, 5 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13w %+ _cl, %1 r13w, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSx14 %+ _1, %1 word [r14], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxBP %+ _Ib, %1 word [rbp], 4 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSx9 %+ _cl, %1 word [r9], cl %endif ; 32-bit BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _edi %+ _1, %1 edi, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _Ib, %1 ecx, 25 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ebp %+ _cl, %1 ebp, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxSI %+ _1, %1 dword [xSI], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxBX %+ _Ib, %1 dword [xBX], 24 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxDI %+ _cl, %1 dword [xDI], cl %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8d %+ _1, %1 r8d, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9d %+ _Ib, %1 r9d, 23 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13d %+ _cl, %1 r13d, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSx14 %+ _1, %1 dword [r14], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxBP %+ _Ib, %1 dword [rbp], 22 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSx9 %+ _cl, %1 dword [r9], cl %endif ; 64-bit %ifdef TMPL_64BIT BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rdi %+ _1, %1 rdi, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rcx %+ _Ib, %1 rcx, 35 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rbp %+ _cl, %1 rbp, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxSI %+ _1, %1 qword [xSI], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxBX %+ _Ib, %1 qword [xBX], 24 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxDI %+ _cl, %1 qword [xDI], cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _1, %1 r8, 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9 %+ _Ib, %1 r9, 48 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13 %+ _cl, %1 r13, cl BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx14 %+ _1, %1 qword [r14], 1 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxBP %+ _Ib, %1 qword [rbp], 56 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx9 %+ _cl, %1 qword [r9], cl %endif %endmacro ; BS3CPUINSTR2_SHIFT_OP %endif ;********************************************************************************************************************************* ;* External Symbols * ;********************************************************************************************************************************* TMPL_BEGIN_TEXT ; ; Test code snippets containing code which differs between 16-bit, 32-bit ; and 64-bit CPUs modes. ; %ifdef BS3_INSTANTIATING_CMN %ifndef ALT_INSTRUCTION_MACROS_DEFINED %define ALT_INSTRUCTION_MACROS_DEFINED %macro ALT_INSTRUCTION8_REG_RM 3+ X86_MKOP_REX8 %1, %2 db %3 X86_MKOP_MODRM8 X86_MOD_REG, %1, %2 %endmacro %macro ALT_INSTRUCTION16_REG_RM 3+ %if TMPL_BITS != 16 db X86_OP_PRF_SIZE_OP %endif X86_MKOP_REX16 %1, %2 db %3 X86_MKOP_MODRM16 X86_MOD_REG, %1, %2 %endmacro %macro ALT_INSTRUCTION32_REG_RM 3+ %if TMPL_BITS == 16 db X86_OP_PRF_SIZE_OP %endif X86_MKOP_REX32 %1, %2 db %3 X86_MKOP_MODRM32 X86_MOD_REG, %1, %2 %endmacro %macro ALT_INSTRUCTION64_REG_RM 3+ X86_MKOP_REX64 %1, %2 db %3 X86_MKOP_MODRM64 X86_MOD_REG, %1, %2 %endmacro ; nasm v2.16.02rc1 encodes the 20h and 21h variants (AND rm,reg) %macro ALT_INSTRUCTION8_and 2 ALT_INSTRUCTION8_REG_RM %1, %2, 22h %endmacro %macro ALT_INSTRUCTION16_and 2 ALT_INSTRUCTION16_REG_RM %1, %2, 23h %endmacro %macro ALT_INSTRUCTION32_and 2 ALT_INSTRUCTION32_REG_RM %1, %2, 23h %endmacro %macro ALT_INSTRUCTION64_and 2 ALT_INSTRUCTION64_REG_RM %1, %2, 23h %endmacro ; nasm v2.16.02rc1 encodes the 08h and 09h variants (OR rm,reg) %macro ALT_INSTRUCTION8_or 2 ALT_INSTRUCTION8_REG_RM %1, %2, 0ah %endmacro %macro ALT_INSTRUCTION16_or 2 ALT_INSTRUCTION16_REG_RM %1, %2, 0bh %endmacro %macro ALT_INSTRUCTION32_or 2 ALT_INSTRUCTION32_REG_RM %1, %2, 0bh %endmacro %macro ALT_INSTRUCTION64_or 2 ALT_INSTRUCTION64_REG_RM %1, %2, 0bh %endmacro ; nasm v2.16.02rc1 encodes the 30h and 31h variants (XOR rm,reg) %macro ALT_INSTRUCTION8_xor 2 ALT_INSTRUCTION8_REG_RM %1, %2, 32h %endmacro %macro ALT_INSTRUCTION16_xor 2 ALT_INSTRUCTION16_REG_RM %1, %2, 33h %endmacro %macro ALT_INSTRUCTION32_xor 2 ALT_INSTRUCTION32_REG_RM %1, %2, 33h %endmacro %macro ALT_INSTRUCTION64_xor 2 ALT_INSTRUCTION64_REG_RM %1, %2, 33h %endmacro ; nasm v2.16.02rc1 encodes the 00h and 01h variants (ADD rm,reg) %macro ALT_INSTRUCTION8_add 2 ALT_INSTRUCTION8_REG_RM %1, %2, 02h %endmacro %macro ALT_INSTRUCTION16_add 2 ALT_INSTRUCTION16_REG_RM %1, %2, 03h %endmacro %macro ALT_INSTRUCTION32_add 2 ALT_INSTRUCTION32_REG_RM %1, %2, 03h %endmacro %macro ALT_INSTRUCTION64_add 2 ALT_INSTRUCTION64_REG_RM %1, %2, 03h %endmacro ; nasm v2.16.02rc1 encodes the 10h and 11h variants (ADC rm,reg) %macro ALT_INSTRUCTION8_adc 2 ALT_INSTRUCTION8_REG_RM %1, %2, 12h %endmacro %macro ALT_INSTRUCTION16_adc 2 ALT_INSTRUCTION16_REG_RM %1, %2, 13h %endmacro %macro ALT_INSTRUCTION32_adc 2 ALT_INSTRUCTION32_REG_RM %1, %2, 13h %endmacro %macro ALT_INSTRUCTION64_adc 2 ALT_INSTRUCTION64_REG_RM %1, %2, 13h %endmacro ; nasm v2.16.02rc1 encodes the 28h and 29h variants (SUB rm,reg) %macro ALT_INSTRUCTION8_sub 2 ALT_INSTRUCTION8_REG_RM %1, %2, 2ah %endmacro %macro ALT_INSTRUCTION16_sub 2 ALT_INSTRUCTION16_REG_RM %1, %2, 2bh %endmacro %macro ALT_INSTRUCTION32_sub 2 ALT_INSTRUCTION32_REG_RM %1, %2, 2bh %endmacro %macro ALT_INSTRUCTION64_sub 2 ALT_INSTRUCTION64_REG_RM %1, %2, 2bh %endmacro ; nasm v2.16.02rc1 encodes the 18h and 19h variants (SBB rm,reg) %macro ALT_INSTRUCTION8_sbb 2 ALT_INSTRUCTION8_REG_RM %1, %2, 1ah %endmacro %macro ALT_INSTRUCTION16_sbb 2 ALT_INSTRUCTION16_REG_RM %1, %2, 1bh %endmacro %macro ALT_INSTRUCTION32_sbb 2 ALT_INSTRUCTION32_REG_RM %1, %2, 1bh %endmacro %macro ALT_INSTRUCTION64_sbb 2 ALT_INSTRUCTION64_REG_RM %1, %2, 1bh %endmacro ; nasm v2.16.02rc1 encodes the 38h and 39h variants (CMP rm,reg) %macro ALT_INSTRUCTION8_cmp 2 ALT_INSTRUCTION8_REG_RM %1, %2, 3ah %endmacro %macro ALT_INSTRUCTION16_cmp 2 ALT_INSTRUCTION16_REG_RM %1, %2, 3bh %endmacro %macro ALT_INSTRUCTION32_cmp 2 ALT_INSTRUCTION32_REG_RM %1, %2, 3bh %endmacro %macro ALT_INSTRUCTION64_cmp 2 ALT_INSTRUCTION64_REG_RM %1, %2, 3bh %endmacro %endif ; !ALT_INSTRUCTION_MACROS_DEFINED BS3CPUINSTR2_BINARY_OP and, 1, 3, 1 BS3CPUINSTR2_BINARY_OP or, 1, 3, 1 BS3CPUINSTR2_BINARY_OP xor, 1, 3, 1 BS3CPUINSTR2_BINARY_OP test, 1, 2, 0 BS3CPUINSTR2_BINARY_OP add, 1, 3, 1 BS3CPUINSTR2_BINARY_OP adc, 1, 3, 1 BS3CPUINSTR2_BINARY_OP sub, 1, 3, 1 BS3CPUINSTR2_BINARY_OP sbb, 1, 3, 1 BS3CPUINSTR2_BINARY_OP cmp, 1, 3, 1 BS3CPUINSTR2_BINARY_OP bt, 0, 1, 0 BS3CPUINSTR2_BINARY_OP btc, 0, 1, 0 BS3CPUINSTR2_BINARY_OP btr, 0, 1, 0 BS3CPUINSTR2_BINARY_OP bts, 0, 1, 0 BS3CPUINSTR2_SHIFT_OP shl BS3CPUINSTR2_SHIFT_OP shr BS3CPUINSTR2_SHIFT_OP sar BS3CPUINSTR2_SHIFT_OP rol BS3CPUINSTR2_SHIFT_OP ror BS3CPUINSTR2_SHIFT_OP rcl BS3CPUINSTR2_SHIFT_OP rcr BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR mul xBX .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR imul xBX .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR imul xCX, xBX .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR div xBX .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR idiv xBX .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2 ; ; BSF / BSR / TZCNT / LZCNT ; %ifndef EMIT_BITSCAN_DEFINED %define EMIT_BITSCAN_DEFINED %macro EMIT_BITSCAN 3 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2, BS3_PBC_NEAR %2 %1 ax, bx .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2, BS3_PBC_NEAR %2 %1 ax, [fs:xBX] .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2, BS3_PBC_NEAR %2 %1 eax, ebx .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2, BS3_PBC_NEAR %2 %1 eax, [fs:xBX] .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2 %if TMPL_BITS == 64 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2, BS3_PBC_NEAR %2 %1 rax, rbx .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2, BS3_PBC_NEAR %2 %1 rax, [fs:xBX] .again: ud2 jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2 %endif %endmacro %endif EMIT_BITSCAN bsf, .ignored:, bsf EMIT_BITSCAN bsr, .ignored:, bsr EMIT_BITSCAN tzcnt, .ignored:, tzcnt EMIT_BITSCAN lzcnt, .ignored:, lzcnt EMIT_BITSCAN bsf, db 0f2h, f2_bsf EMIT_BITSCAN bsr, db 0f2h, f2_bsr EMIT_BITSCAN tzcnt, db 0f2h, f2_tzcnt EMIT_BITSCAN lzcnt, db 0f2h, f2_lzcnt ; ; RORX - VEX instruction with a couple of questions about non-standard encodings. ; ;;%define icebp ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR rorx ebx, edx, 2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 rorx rbx, rdx, 2 %else db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR db 0C4h, 0E3h, 07Bh | 4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR db 0C4h, 0E3h, 003h | ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1 - behaviour is undocumented - 10980xe #UD .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR db 0C4h, 0E3h, 003h | ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15 - behaviour is not documented - 10980xe #UD .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15 %if TMPL_BITS == 64 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0 - behaviour is not documented - ignored by 10980xe .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1 %endif ; A couple of memory variants BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp, BS3_PBC_NEAR rorx ebx, [xDI], 36 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 rorx rbx, [xDI], 68 %elif TMPL_BITS == 32 db 0C4h,0E3h,07Bh,0F0h,01Fh,044h ; 16-bit ignores VEX.W=1 (10980xe) %else db 0C4h,0E3h,0FBh,0F0h,01Dh,044h ; 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp ; ; ANDN (BMI1) ; BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 andn rax, rcx, rbx %else db 0C4h,0E2h,0F0h,0F2h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp, BS3_PBC_NEAR andn eax, ecx, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 andn rax, rcx, [fs:rbx] %elif TMPL_BITS == 32 db 064h,0C4h,0E2h,0F0h,0F2h,003h ; andn rax, rcx, [fs:ebx] %else db 064h,0C4h,0E2h,0F0h,0F2h,007h ; andn rax, rcx, [fs:bx] %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR andn eax, ecx, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp ; ; BEXTR / SHLX / SARX / SHRX - BMI1 (opcode f7h) ; BZHI - BMI2 (opcode f5h) ; ; @param %1 instruction ; @param %2 opcode ; @param %3 prefix ; %ifndef SHLX_SARX_SHRX_DEFINED %define SHLX_SARX_SHRX_DEFINED %macro SHLX_SARX_SHRX 3 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 %1 rax, rbx, rcx ; SHLX=C4E2F1F7C3 %else db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp, BS3_PBC_NEAR %1 eax, ebx, ecx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 %1 rax, [fs:rbx], rcx ; SHLX=64C4E2F1F703 %elif TMPL_BITS == 32 db 064h,0C4h,0E2h,0F0h|%3,%2,003h %else db 064h,0C4h,0E2h,0F0h|%3,%2,007h %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp, BS3_PBC_NEAR %1 eax, [fs:xBX], ecx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp %endmacro %endif SHLX_SARX_SHRX bextr, 0f7h, 0 ; none SHLX_SARX_SHRX shlx, 0f7h, 1 ; 66h SHLX_SARX_SHRX sarx, 0f7h, 2 ; f3h SHLX_SARX_SHRX shrx, 0f7h, 3 ; f2h SHLX_SARX_SHRX bzhi, 0f5h, 0 ; none ; ; PPEP / PEXT - BMI2 (opcode f5h) ; ; @param %1 instruction ; @param %2 opcode ; @param %3 prefix ; %ifndef PDEP_PEXT_DEFINED %define PDEP_PEXT_DEFINED %macro PDEP_PEXT_ 3 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 %1 rax, rcx, rbx %else db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp, BS3_PBC_NEAR %1 eax, ecx, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 %1 rax, rcx, [fs:rbx] %elif TMPL_BITS == 32 db 064h,0C4h,0E2h,0F0h|%3,%2,003h %else db 064h,0C4h,0E2h,0F0h|%3,%2,007h %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR %1 eax, ecx, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp %endmacro %endif PDEP_PEXT_ pext, 0f5h, 2 ; f3h PDEP_PEXT_ pdep, 0f5h, 3 ; f2h ; ; BLSR / BLSMSK / BLSI ; These are encoded in the exact same way, only the /r differs (%2). ; %ifndef BLSR_BLSMSK_BLSI_DEFINED %define BLSR_BLSMSK_BLSI_DEFINED %macro BLSR_BLSMSK_BLSI 2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 %1 rax, rbx ; BLSR=C4E2F8F3CB %else db 0C4h,0E2h,0F8h,0F3h,0C3h | (%2 << 3) ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp, BS3_PBC_NEAR %1 eax, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 %1 rax, [fs:rbx] ; BSLR=64C4E2F8F30B %elif TMPL_BITS == 32 db 064h,0C4h,0E2h,0F8h,0F3h,003h | (%2 << 3) %else db 064h,0C4h,0E2h,0F8h,0F3h,007h | (%2 << 3) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp, BS3_PBC_NEAR %1 eax, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp %endmacro %endif BLSR_BLSMSK_BLSI blsr, 1 BLSR_BLSMSK_BLSI blsmsk, 2 BLSR_BLSMSK_BLSI blsi, 3 ; ; MULX ; BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 mulx rax, rcx, rbx ; C4E2F3F6C3 %else db 0C4h,0E2h,0F3h,0F6h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 mulx rcx, rcx, rbx ; C4E2F3F6CB %else db 0C4h,0E2h,0F3h,0F6h,0CBh ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp, BS3_PBC_NEAR %if TMPL_BITS == 64 mulx rax, rcx, [fs:rbx] ; 64C4E2F3F603 %elif TMPL_BITS == 32 db 064h,0C4h,0E2h,0F3h,0F6h,003h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %else db 064h,0C4h,0E2h,0F3h,0F6h,007h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) %endif .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR mulx eax, ecx, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR mulx ecx, ecx, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp, BS3_PBC_NEAR mulx eax, ecx, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp ; ; POPCNT ; BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_BX_icebp, BS3_PBC_NEAR popcnt ax, bx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_BX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp, BS3_PBC_NEAR popcnt eax, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp %if TMPL_BITS == 64 BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp, BS3_PBC_NEAR popcnt rax, rbx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp %endif BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp, BS3_PBC_NEAR popcnt ax, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp, BS3_PBC_NEAR popcnt eax, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp %if TMPL_BITS == 64 BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp, BS3_PBC_NEAR popcnt rax, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp %endif ; ; CRC32 ; BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BL_icebp crc32 eax, bl .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BL_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BX_icebp crc32 eax, bx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BX_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp crc32 eax, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp %if TMPL_BITS == 64 BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp crc32 rax, rbx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp %endif BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp crc32 eax, byte [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp crc32 eax, word [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp crc32 eax, dword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp %if TMPL_BITS == 64 BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp crc32 rax, qword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp %endif ; ; ADCX ; BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp adcx eax, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp %if TMPL_BITS == 64 BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp adcx rax, rbx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp %endif BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp adcx eax, dword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp %if TMPL_BITS == 64 BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp adcx rax, qword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp %endif ; ; ADOX ; BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_EBX_icebp adox eax, ebx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_EBX_icebp %if TMPL_BITS == 64 BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_RBX_icebp adox rax, rbx .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_RBX_icebp %endif BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp adox eax, dword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp %if TMPL_BITS == 64 BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp adox rax, qword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp %endif ; ; MOVBE ; BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_AX_word_FSxBX_icebp movbe ax, word [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_movbe_AX_word_FSxBX_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_word_FSxBX_AX_icebp movbe word [fs:xBX], ax .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_movbe_word_FSxBX_AX_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_EAX_dword_FSxBX_icebp movbe eax, dword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_movbe_EAX_dword_FSxBX_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_dword_FSxBX_EAX_icebp movbe dword [fs:xBX], eax .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_movbe_dword_FSxBX_EAX_icebp %if TMPL_BITS == 64 BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_RAX_qword_FSxBX_icebp movbe rax, qword [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_movbe_RAX_qword_FSxBX_icebp BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_qword_FSxBX_RAX_icebp movbe qword [fs:xBX], rax .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_movbe_qword_FSxBX_RAX_icebp %endif ; ; CMPXCHG8B ; BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg8b_FSxDI_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR lock cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg8b_FSxDI_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR o16 cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg8b_FSxDI_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR db 0f0h, 066h cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg8b_FSxDI_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR repz cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg8b_FSxDI_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR db 0f0h, 0f3h cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg8b_FSxDI_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR repnz cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg8b_FSxDI_icebp BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR db 0f0h, 0f2h cmpxchg8b [fs:xDI] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg8b_FSxDI_icebp ; ; CMPXCHG16B ; %if TMPL_BITS == 64 BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 4) BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR lock cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR o16 cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR db 0f0h, 066h cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 6) BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR repz cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR db 0f0h, 0f3h cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 6) BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR repnz cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR db 0f0h, 0f2h cmpxchg16b [rdi] .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 6) BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR wrfsbase rbx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR wrfsbase ebx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 4) BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR wrgsbase rbx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR wrgsbase ebx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 4) BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR wrfsbase rbx mov ebx, 0 rdfsbase rcx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 15) BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR wrfsbase ebx mov ebx, 0 rdfsbase ecx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 13) BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR wrgsbase rbx mov ebx, 0 rdgsbase rcx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 15) BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR wrgsbase ebx mov ebx, 0 rdgsbase ecx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 13) BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR rdfsbase rbx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR rdfsbase ebx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 4) BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR rdgsbase rbx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 5) BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR rdgsbase ebx .again: ud2 jmp .again AssertCompile(.again - BS3_LAST_LABEL == 4) BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2 ;; @todo figure out this fudge. sigh. times (348) db 0cch ; fudge to avoid 'rderr' during boot. %endif ; TMPL_BITS == 64 %endif ; BS3_INSTANTIATING_CMN %include "bs3kit-template-footer.mac" ; reset environment