Changeset 9539

Timestamp:

06/09/08 14:15:55 (6 months ago)

Author:

vboxsync

Message:

Some changes for amd64.
Lifted a restriction for executing code in VT-x (idt & tr): watch for regressions.

Files:

• trunk/src/VBox/VMM/HWACCM.cpp (modified) (2 diffs)
• trunk/src/VBox/VMM/PGM.cpp (modified) (1 diff)
• trunk/src/VBox/VMM/VMM.cpp (modified) (1 diff)
• trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (1 diff)
• trunk/src/VBox/VMM/VMMAll/PGMAllGst.h (modified) (7 diffs)

trunk/src/VBox/VMM/HWACCM.cpp

@@ -635 +635 @@
-    }
-
-and protected mode without paging 
+
-     * (but do we really care?)
-     */
@@ -643 +643 @@
-    /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
-
-
+ 0 //
-    /* Too early for VMX. */
-    if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
-        return false;
+#endif
-
-    /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
+    /* Windows XP; switch to protected mode; all selectors are marked not present in the 
+     * hidden registers (possible recompiler bug) */
-    if (pCtx->csHid.Attr.n.u1Present == 0)
-        return false;
-    if (pCtx->ssHid.Attr.n.u1Present == 0)
-        return false;
-#endif
-
-    if (pVM->hwaccm.s.vmx.fEnabled)

trunk/src/VBox/VMM/PGM.cpp

@@ -3147 +3147 @@
-        }
-
-//
+
-        case PGMMODE_AMD64:
-            GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */

trunk/src/VBox/VMM/VMM.cpp

@@ -1700 +1700 @@
-    }
-
+    /* Do nothing if the switcher is disabled. */
+    if (pVM->vmm.s.fSwitcherDisabled)
+        return VINF_SUCCESS;
+
-    /*
-     * Select the new switcher.

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -581 +581 @@
-    int rc;
-
-Flow
+2
-
-    /** @todo merge PGMGCInvalidatePage with this one */

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -398 +398 @@
-{
-#if PGM_GST_TYPE == PGM_TYPE_32BIT \
-
-
+
-
-    LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
@@ -415 +414 @@
-        {
-            PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
-
+ 
-            pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
-            pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
-
-elif PGM_GST_TYPE == PGM_TYPE_PAE
+ else /* PAE */
-            unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
-            pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
@@ -455 +454 @@
-                PGM_INVL_PG(GCPtr);
-            }
-
-
-
-
+
-        }
-        else
@@ -466 +462 @@
-        AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
-
-
+/amd64
-    int rc = VINF_SUCCESS;
-#endif
@@ -500 +496 @@
-
-#elif PGM_GST_TYPE == PGM_TYPE_AMD64
-
-
+
-
-#else /* prot/real mode stub */
@@ -613 +608 @@
-    }
-
-#elif PGM_GST_TYPE == PGM_TYPE_AMD64
-    AssertFailed();
-#else
-
+/amd64
-
-#endif
@@ -680 +673 @@
-        }
-    }
-#elif PGM_GST_TYPE == PGM_TYPE_AMD64
-    AssertFailed();
-#else
-
+/amd64
-#endif
-    return rc;