Changeset 6318
- Timestamp:
- 01/10/08 09:25:28 (11 months ago)
- Files:
-
- trunk/src/VBox/Devices/Storage/fdc.c (modified) (22 diffs)
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- Added
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trunk/src/VBox/Devices/Storage/fdc.c
r5999 r6318 709 709 FLOPPY_DPRINTF("Reset interrupt\n"); 710 710 #ifdef VBOX 711 fdctrl->pDevIns->pDevHlp->pfnISASetIrq (fdctrl->pDevIns, 712 fdctrl->irq_lvl, 0); 711 PDMDevHlpISASetIrq (fdctrl->pDevIns, fdctrl->irq_lvl, 0); 713 712 #else 714 713 pic_set_irq(fdctrl->irq_lvl, 0); … … 721 720 if (~(fdctrl->state & FD_CTRL_INTR)) { 722 721 #ifdef VBOX 723 fdctrl->pDevIns->pDevHlp->pfnISASetIrq (fdctrl->pDevIns, 724 fdctrl->irq_lvl, 1); 722 PDMDevHlpISASetIrq (fdctrl->pDevIns, fdctrl->irq_lvl, 1); 725 723 #else 726 724 pic_set_irq(fdctrl->irq_lvl, 1); … … 997 995 if (fdctrl->state & FD_CTRL_BUSY) { 998 996 #ifdef VBOX 999 fdctrl->pDevIns->pDevHlp->pfnDMASetDREQ (fdctrl->pDevIns, 1000 fdctrl->dma_chann, 1001 0); 997 PDMDevHlpDMASetDREQ (fdctrl->pDevIns, fdctrl->dma_chann, 0); 1002 998 #else 1003 999 DMA_release_DREQ(fdctrl->dma_chann); … … 1081 1077 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); 1082 1078 #else 1083 dma_mode = fdctrl->pDevIns->pDevHlp->pfnDMAGetChannelMode ( 1084 fdctrl->pDevIns, 1085 fdctrl->dma_chann 1086 ); 1079 dma_mode = PDMDevHlpDMAGetChannelMode (fdctrl->pDevIns, fdctrl->dma_chann); 1087 1080 #endif 1088 1081 dma_mode = (dma_mode >> 2) & 3; … … 1104 1097 DMA_schedule(fdctrl->dma_chann); 1105 1098 #else 1106 fdctrl->pDevIns->pDevHlp->pfnDMASetDREQ (fdctrl->pDevIns, 1107 fdctrl->dma_chann, 1108 1); 1109 fdctrl->pDevIns->pDevHlp->pfnDMASchedule (fdctrl->pDevIns); 1099 PDMDevHlpDMASetDREQ (fdctrl->pDevIns, fdctrl->dma_chann, 1); 1100 PDMDevHlpDMASchedule (fdctrl->pDevIns); 1110 1101 #endif 1111 1102 return; … … 1248 1239 { 1249 1240 uint32_t read; 1250 int rc = fdctrl->pDevIns->pDevHlp->pfnDMAWriteMemory( 1251 fdctrl->pDevIns, 1252 nchan, 1253 fdctrl->fifo + rel_pos, 1254 fdctrl->data_pos, 1255 len, 1256 &read); 1241 int rc = PDMDevHlpDMAWriteMemory(fdctrl->pDevIns, nchan, 1242 fdctrl->fifo + rel_pos, 1243 fdctrl->data_pos, 1244 len, &read); 1257 1245 dump (fdctrl->fifo + rel_pos, len); 1258 AssertMsgRC (rc, 1259 ("DMAWriteMemory -> %Vrc\n", rc)); 1246 AssertMsgRC (rc, ("DMAWriteMemory -> %Vrc\n", rc)); 1260 1247 } 1261 1248 #else … … 1271 1258 { 1272 1259 uint32_t written; 1273 int rc = fdctrl->pDevIns->pDevHlp->pfnDMAReadMemory( 1274 fdctrl->pDevIns, 1275 nchan, 1276 fdctrl->fifo + rel_pos, 1277 fdctrl->data_pos, 1278 len, 1279 &written); 1280 AssertMsgRC (rc, 1281 ("DMAReadMemory -> %Vrc\n", rc)); 1260 int rc = PDMDevHlpDMAReadMemory(fdctrl->pDevIns, nchan, 1261 fdctrl->fifo + rel_pos, 1262 fdctrl->data_pos, 1263 len, &written); 1264 AssertMsgRC (rc, ("DMAReadMemory -> %Vrc\n", rc)); 1282 1265 } 1283 1266 #else … … 1324 1307 uint32_t read; 1325 1308 1326 rc = fdctrl->pDevIns->pDevHlp->pfnDMAReadMemory ( 1327 fdctrl->pDevIns, 1328 nchan, 1329 tmpbuf, 1330 fdctrl->data_pos, 1331 len, 1332 &read); 1333 AssertMsg (VBOX_SUCCESS (rc), 1334 ("DMAReadMemory -> %Vrc\n", rc)); 1309 rc = PDMDevHlpDMAReadMemory (fdctrl->pDevIns, nchan, tmpbuf, 1310 fdctrl->data_pos, len, &read); 1311 AssertMsg (VBOX_SUCCESS (rc), ("DMAReadMemory -> %Vrc\n", rc)); 1335 1312 #else 1336 1313 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); … … 1484 1461 /* READ commands */ 1485 1462 #ifdef VBOX 1486 fdctrl->pDevIns->pDevHlp->pfnPhysWrite ( 1487 fdctrl->pDevIns, 1488 addr + fdctrl->data_pos, 1489 fdctrl->fifo + rel_pos, 1490 len); 1463 PDMDevHlpPhysWrite (fdctrl->pDevIns, addr + fdctrl->data_pos, 1464 fdctrl->fifo + rel_pos, len); 1491 1465 #else 1492 1466 cpu_physical_memory_write(addr + fdctrl->data_pos, … … 1500 1474 int rc; 1501 1475 1502 fdctrl->pDevIns->pDevHlp->pfnPhysRead ( 1503 fdctrl->pDevIns, 1504 addr + fdctrl->data_pos, 1505 fdctrl->fifo + rel_pos, 1506 len); 1476 PDMDevHlpPhysRead (fdctrl->pDevIns, addr + fdctrl->data_pos, 1477 fdctrl->fifo + rel_pos, len); 1507 1478 1508 1479 cur_drv->Led.Asserted.s.fWriting … … 1544 1515 int ret; 1545 1516 #ifdef VBOX 1546 fdctrl->pDevIns->pDevHlp->pfnPhysRead ( 1547 fdctrl->pDevIns, 1548 addr + fdctrl->data_pos, 1549 tmpbuf, 1550 len); 1517 PDMDevHlpPhysRead (fdctrl->pDevIns, addr + fdctrl->data_pos, 1518 tmpbuf, len); 1551 1519 #else 1552 1520 cpu_physical_memory_read(addr + fdctrl->data_pos, … … 2803 2771 * Validate configuration. 2804 2772 */ 2805 if (!CFGMR3AreValuesValid(pCfgHandle, "IRQ\0DMA\0MemMapped\0IOBase\0")) {2773 if (!CFGMR3AreValuesValid(pCfgHandle, "IRQ\0DMA\0MemMapped\0IOBase\0")) 2806 2774 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES; 2807 }2808 2775 2809 2776 /* … … 2811 2778 */ 2812 2779 rc = CFGMR3QueryU8 (pCfgHandle, "IRQ", &irq_lvl); 2813 if (rc == VERR_CFGM_VALUE_NOT_FOUND) {2780 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 2814 2781 irq_lvl = 6; 2815 }2816 else if (VBOX_FAILURE (rc)){2782 else if (VBOX_FAILURE (rc)) 2783 { 2817 2784 AssertMsgFailed (("Configuration error: Failed to read U8 IRQ, rc=%Vrc\n", rc)); 2818 2785 return rc; … … 2820 2787 2821 2788 rc = CFGMR3QueryU8 (pCfgHandle, "DMA", &dma_chann); 2822 if (rc == VERR_CFGM_VALUE_NOT_FOUND) {2789 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 2823 2790 dma_chann = 2; 2824 }2825 else if (VBOX_FAILURE (rc)){2791 else if (VBOX_FAILURE (rc)) 2792 { 2826 2793 AssertMsgFailed (("Configuration error: Failed to read U8 DMA, rc=%Vrc\n", rc)); 2827 2794 return rc; … … 2829 2796 2830 2797 rc = CFGMR3QueryU16 (pCfgHandle, "IOBase", &io_base); 2831 if (rc == VERR_CFGM_VALUE_NOT_FOUND) {2798 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 2832 2799 io_base = 0x3f0; 2833 }2834 else if (VBOX_FAILURE (rc)){2800 else if (VBOX_FAILURE (rc)) 2801 { 2835 2802 AssertMsgFailed (("Configuration error: Failed to read U16 IOBase, rc=%Vrc\n", rc)); 2836 2803 return rc; … … 2838 2805 2839 2806 rc = CFGMR3QueryBool (pCfgHandle, "MemMapped", &mem_mapped); 2840 if (rc == VERR_CFGM_VALUE_NOT_FOUND) {2807 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 2841 2808 mem_mapped = false; 2842 }2843 else if (VBOX_FAILURE (rc)){2809 else if (VBOX_FAILURE (rc)) 2810 { 2844 2811 AssertMsgFailed (("Configuration error: Failed to read bool value MemMapped rc=%Vrc\n", rc)); 2845 2812 return rc; … … 2860 2827 fdctrl->ILeds.pfnQueryStatusLed = fdcStatusQueryStatusLed; 2861 2828 2862 for (i = 0; i < ELEMENTS(fdctrl->drives); ++i) { 2829 for (i = 0; i < ELEMENTS(fdctrl->drives); ++i) 2830 { 2863 2831 fdrive_t *drv = &fdctrl->drives[i]; 2864 2832 … … 2876 2844 */ 2877 2845 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, fdc_timer, "FDC Timer", &fdctrl->result_timer); 2878 if (VBOX_FAILURE (rc)) {2846 if (VBOX_FAILURE (rc)) 2879 2847 return rc; 2880 }2881 2848 2882 2849 /* 2883 2850 * Register DMA channel. 2884 2851 */ 2885 if (fdctrl->dma_chann != 0xff) { 2852 if (fdctrl->dma_chann != 0xff) 2853 { 2886 2854 fdctrl->dma_en = 1; 2887 rc = pDevIns->pDevHlp->pfnDMARegister ( 2888 pDevIns, 2889 dma_chann, 2890 &fdctrl_transfer_handler, 2891 fdctrl); 2892 if (VBOX_FAILURE (rc)) { 2855 rc = PDMDevHlpDMARegister (pDevIns, dma_chann, &fdctrl_transfer_handler, fdctrl); 2856 if (VBOX_FAILURE (rc)) 2893 2857 return rc; 2894 2895 } else {2858 } 2859 else 2896 2860 fdctrl->dma_en = 0; 2897 }2898 2861 2899 2862 /* 2900 2863 * IO / MMIO. 2901 2864 */ 2902 if (mem_mapped) { 2865 if (mem_mapped) 2866 { 2903 2867 AssertMsgFailed (("Memory mapped floppy not support by now\n")); 2904 2868 return VERR_NOT_SUPPORTED; … … 2908 2872 cpu_register_physical_memory(base, 0x08, io_mem); 2909 2873 #endif 2910 } else { 2911 rc = pDevIns->pDevHlp->pfnIOPortRegister ( 2912 pDevIns, 2913 io_base + 0x1, 2914 5, 2915 fdctrl, 2916 fdc_io_write, 2917 fdc_io_read, 2918 NULL, NULL, 2919 "FDC#1" 2920 ); 2921 if (VBOX_FAILURE (rc)) { 2874 } 2875 else 2876 { 2877 rc = PDMDevHlpIOPortRegister (pDevIns, io_base + 0x1, 5, fdctrl, 2878 fdc_io_write, fdc_io_read, NULL, NULL, "FDC#1"); 2879 if (VBOX_FAILURE (rc)) 2922 2880 return rc; 2923 } 2924 2925 rc = pDevIns->pDevHlp->pfnIOPortRegister ( 2926 pDevIns, 2927 io_base + 0x7, 2928 1, 2929 fdctrl, 2930 fdc_io_write, 2931 fdc_io_read, 2932 NULL, NULL, 2933 "FDC#2" 2934 ); 2935 if (VBOX_FAILURE (rc)) { 2881 2882 rc = PDMDevHlpIOPortRegister (pDevIns, io_base + 0x7, 1, fdctrl, 2883 fdc_io_write, fdc_io_read, NULL, NULL, "FDC#2"); 2884 if (VBOX_FAILURE (rc)) 2936 2885 return rc; 2937 }2938 2886 } 2939 2887 … … 2941 2889 * Register the saved state data unit. 2942 2890 */ 2943 rc = pDevIns->pDevHlp->pfnSSMRegister ( 2944 pDevIns, /* pDevIns */ 2945 pDevIns->pDevReg->szDeviceName, /* pszName */ 2946 iInstance, /* u32Instance */ 2947 1 /* u32Version */, 2948 sizeof (*fdctrl), /* cbGuess */ 2949 NULL, /* pfnSavePrep */ 2950 SaveExec, /* pfnSaveExec */ 2951 NULL, /* pfnSaveDone */ 2952 NULL, /* pfnLoadPrep */ 2953 LoadExec, /* pfnLoadExec */ 2954 NULL /* pfnLoadDone */ 2955 ); 2891 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1, sizeof(*fdctrl), 2892 NULL, SaveExec, NULL, NULL, LoadExec, NULL); 2956 2893 if (VBOX_FAILURE(rc)) 2957 2894 return rc; … … 2974 2911 * Initialize drives. 2975 2912 */ 2976 for (i = 0; i < ELEMENTS(fdctrl->drives); i++) { 2913 for (i = 0; i < ELEMENTS(fdctrl->drives); i++) 2914 { 2977 2915 fdrive_t *drv = &fdctrl->drives[i]; 2978 2916 rc = fdConfig (drv, pDevIns); 2979 2917 if ( VBOX_FAILURE (rc) 2980 && rc != VERR_PDM_NO_ATTACHED_DRIVER) { 2918 && rc != VERR_PDM_NO_ATTACHED_DRIVER) 2919 { 2981 2920 AssertMsgFailed (("Configuration error: failed to configure drive %d, rc=%Vrc\n", rc)); 2982 2921 return rc; … … 2987 2926 fdctrl->state = FD_CTRL_ACTIVE; 2988 2927 2989 for (i = 0; i < ELEMENTS(fdctrl->drives); i++) {2928 for (i = 0; i < ELEMENTS(fdctrl->drives); i++) 2990 2929 fd_revalidate(&fdctrl->drives[i]); 2991 }2992 2930 2993 2931 return VINF_SUCCESS;
