Changeset 14751

Timestamp:

11/28/08 02:21:42 (1 month ago)

Author:

vboxsync

Message:

#1865: PGMAllPool: Fixes for non-contiguous mapping of the fake 2048 entry PAE PD (R0 darwin only).

Files:

• trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp (modified) (19 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -308 +308 @@
-            PX86PML4    pPML4;
-        } uShw;
-        uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-
-        switch (pPage->enmKind)
@@ -314 +313 @@
-            case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
-            {
+                uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                const unsigned iShw = off / sizeof(X86PTE);
-                if (uShw.pPT->a[iShw].n.u1Present)
@@ -331 +331 @@
-            /* page/2 sized */
-            case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
+                uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
-                {
@@ -350 +351 @@
-            case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
-            {
+                uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                const unsigned iShw = off / sizeof(X86PTEPAE);
-                if (uShw.pPTPae->a[iShw].n.u1Present)
@@ -389 +391 @@
-            case PGMPOOLKIND_ROOT_32BIT_PD:
-            {
+                uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                const unsigned iShw = off / sizeof(X86PTE);         // ASSUMING 32-bit guest paging!
-                if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
@@ -428 +431 @@
-            case PGMPOOLKIND_ROOT_PAE_PD:
-            {
-
+
+
+
+
+
-                for (unsigned i = 0; i < 2; i++, iShw++)
-                {
@@ -435 +442 @@
-                        Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
-                        VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
-=%#x!\n"
+Pdpt=%#x iShw=%#x!\n", iShwPdpt
-                    }
-                    /* paranoia / a bit assumptive. */
@@ -443 +450 @@
-                    {
-                        const unsigned iShw2 = iShw + 2;
-
+ /** @todo was completely wrong, it's better now after #1865 but still wrong from cross PD. */
-                            &&  (uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
-                        {
-                            Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
-                            VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
-2=%#x!\n"
+Pdpt=%#x iShw2=%#x!\n", iShwPdpt
-                        }
-                    }
@@ -455 +462 @@
-                        &&  !VM_FF_ISSET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3))
-                    {
-=%#x: %RX64 -> freeing it!\n"
+Pdpt=%#x iShw=%#x: %RX64 -> freeing it!\n", iShwPdpt
-# ifdef IN_RC           /* TLB load - we're pushing things a bit... */
-                        ASMProbeReadByte(pvAddress);
-# endif
-
+ + iShwPdpt * X86_PG_PAE_ENTRIES
-                        uShw.pPDPae->a[iShw].u = 0;
-                    }
@@ -469 +476 @@
-            case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
-            {
+                uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                const unsigned iShw = off / sizeof(X86PDEPAE);
-                if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
@@ -534 +542 @@
-                 * - messing with the bits of pd pointers without changing the physical address
-                 */
+                uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                const unsigned iShw = off / sizeof(X86PDPE);
-                if (iShw < X86_PG_PAE_PDPE_ENTRIES)          /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
@@ -567 +576 @@
-                Assert(pPage->enmKind == PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD);
-
+                uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                const unsigned iShw = off / sizeof(X86PDEPAE);
-                if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
@@ -623 +633 @@
-                if (!VM_FF_ISSET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3))
-                {
+                    uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                    const unsigned iShw = off / sizeof(X86PDPE);
-                    if (uShw.pPDPT->a[iShw].n.u1Present)
@@ -655 +666 @@
-                if (!VM_FF_ISSET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3))
-                {
+                    uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                    const unsigned iShw = off / sizeof(X86PDPE);
-                    if (uShw.pPML4->a[iShw].n.u1Present)
@@ -2712 +2724 @@
-    Assert(pUser->iUser != NIL_PGMPOOL_IDX);
-    Assert(pUser->iUser < pPool->cCurPages);
+    uint32_t iUserTable = pUser->iUserTable;
-
-    /*
@@ -2717 +2730 @@
-     */
-    PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
+#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
+    if (pUserPage->enmKind == PGMPOOLKIND_ROOT_PAE_PD)
+    {
+        /* Must translate the fake 2048 entry PD to a 512 PD one since the R0 mapping is not linear. */
+        Assert(pUser->iUser == PGMPOOL_IDX_PAE_PD);
+        uint32_t iPdpt = iUserTable / X86_PG_PAE_ENTRIES;
+        iUserTable    %= X86_PG_PAE_ENTRIES;
+        pUserPage      = &pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + iPdpt];
+        Assert(pUserPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD);
+    }
+#endif
-    union
-    {
@@ -2734 +2758 @@
-    {
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-pUser->
-pUser->
+
+
-            break;
+# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-        case PGMPOOLKIND_ROOT_PAE_PD:
-pUser->
-pUser->iUserTable] & PGM_PDFLAGS_MAPPING), ("%llx %d\n", u.pau64[pUser->iUserTable], pUser->
+
+iUserTable] & PGM_PDFLAGS_MAPPING), ("%llx %d\n", u.pau64[iUserTable], 
-            break;
+# endif
-        case PGMPOOLKIND_ROOT_PDPT:
-pUser->
-pUser->
+
+
-            break;
-        case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
-        case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
-pUser->
+
-            break;
-        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
-pUser->
-pUser->
+
+
-            break;
-        case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
-pUser->
-pUser->
+
+
-            break;
-        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
-pUser->
+
-            /* GCPhys >> PAGE_SHIFT is the index here */
-            break;
-        case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
-        case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
-pUser->
+
-            break;
-
-        case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
-        case PGMPOOLKIND_EPT_PD_FOR_PHYS:
-pUser->
+
-            break;
-
-        case PGMPOOLKIND_ROOT_NESTED:
-pUser->
+
-            break;
-
@@ -2788 +2814 @@
-        /* 32-bit entries */
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-pUser->
+
-            break;
-
@@ -2799 +2825 @@
-        case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
-        case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
+#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-        case PGMPOOLKIND_ROOT_PAE_PD:
+#endif
-        case PGMPOOLKIND_ROOT_PDPT:
-        case PGMPOOLKIND_ROOT_NESTED:
-        case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
-        case PGMPOOLKIND_EPT_PD_FOR_PHYS:
-pUser->
+
-            break;
-