Navigation

← Previous Changeset
Next Changeset →

Changeset 13960

Timestamp:

11/07/08 14:04:45 (2 months ago)

Author:

vboxsync

Message:

Moved guest and host CPU contexts into per-VCPU array.

Files:

trunk/include/VBox/cpum.h (modified) (5 diffs)
trunk/include/VBox/vm.h (modified) (3 diffs)
trunk/include/VBox/vm.mac (modified) (1 diff)
trunk/src/VBox/VMM/CPUM.cpp (modified) (10 diffs)
trunk/src/VBox/VMM/CPUMInternal.h (modified) (5 diffs)
trunk/src/VBox/VMM/CPUMInternal.mac (modified) (3 diffs)
trunk/src/VBox/VMM/PATM/PATM.cpp (modified) (1 diff)
trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm (modified) (9 diffs)
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (modified) (99 diffs)
trunk/src/VBox/VMM/VMMGC/CPUMGC.cpp (modified) (2 diffs)
trunk/src/VBox/VMM/VMMGC/CPUMGCA.asm (modified) (8 diffs)
trunk/src/VBox/VMM/VMMGC/TRPMGCHandlers.cpp (modified) (1 diff)
trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp (modified) (14 diffs)
trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp (modified) (4 diffs)
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (6 diffs)
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (6 diffs)
trunk/src/VBox/VMM/VMMSwitcher/AMD64ToPAE.asm (modified) (21 diffs)
trunk/src/VBox/VMM/VMMSwitcher/PAEand32Bit.mac (modified) (19 diffs)
trunk/src/VBox/VMM/testcase/Makefile.kmk (modified) (1 diff)
trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp (modified) (1 diff)

Legend:

: Unmodified
: Added
: Removed
: Modified
: Copied
: Moved

trunk/include/VBox/cpum.h

r13832	r13960
891	891	VMMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
892	892	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVM pVM);
	893	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtrEx(PVM pVM, PVMCPU pVCpu);
893	894	VMMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
894	895	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
…	…
899	900	VMMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
900	901	VMMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
901		VMMDECL(int) CPUMHandleLazyFPU(PVM pVM);
902		VMMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
	902	VMMDECL(int) CPUMHandleLazyFPU(PVM pVM, PVMCPU pVCpu);
	903	VMMDECL(int) CPUMRestoreHostFPUState(PVM pVM, PVMCPU pVCpu);
903	904
904	905	/** @name Changed flags
…	…
928	929	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
929	930	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
930		VMMDECL(bool) CPUMIsGuestFPUStateActive(PVM ~~pVM~~);
	931	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCPU);
931	932	VMMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
932	933	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVM pVM);
…	…
966	967	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM);
967	968	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
968		~~VMMR3DECL(int) CPUMR3QueryGuestCtxRCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);~~
969	969	# ifdef DEBUG
970	970	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
…	…
1006	1006	*/
1007	1007	VMMR0DECL(int) CPUMR0Init(PVM pVM);
1008		VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx);
1009		VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx);
1010		VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6);
1011		VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6);
	1008	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
	1009	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
	1010	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
	1011	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
1012	1012
1013	1013	/** @} */

trunk/include/VBox/vm.h

r13898	r13960
107	107	struct CPUMCPU s;
108	108	#endif
109		char padding[~~4096~~]; /* multiple of 32 */
	109	char padding[2048]; /* multiple of 32 */
110	110	} cpum;
111	111	/** VMM part. */
…	…
570	570	STAMPROFILEADV StatSwitcherTSS;
571	571
572		/** @todo Realign everything on 64 byte boundraries to better match the
	572	/** @todo Realign everything on 64 byte boundaries to better match the
573	573	* cache-line size. */
574	574	/* padding - the unions must be aligned on 32 bytes boundraries. */
…	…
581	581	struct CPUM s;
582	582	#endif
583		char padding[4416]; /* multiple of 32 */
	583	char padding[4096]; /* multiple of 32 */
584	584	} cpum;
585	585

trunk/include/VBox/vm.mac

r13831	r13960
95	95
96	96	alignb 64
97		.cpum resb 4416
	97	.cpum resb 4096
98	98	.vmm resb 1024
99	99
100	100	endstruc
101	101
	102	;;
	103	; This is part of the VMCPU structure.
	104	struc VMCPU
	105	.fForcedActions resd 1
	106	.enmState resd 1
	107	.pVMR3 RTR3PTR_RES 1
	108	.pVMR0 RTR0PTR_RES 1
	109	.pVMRC RTRCPTR_RES 1
	110	.idCpu resd 1
	111
	112	.hNativeThread RTR0PTR_RES 1
	113
	114	alignb 64
	115
	116	.cpum resb 2048
	117	endstruc
	118
102	119
103	120	%endif

trunk/src/VBox/VMM/CPUM.cpp

r13840	r13960
129	129	/* Hidden selector registers are invalid by default. */
130	130	pVM->cpum.s.fValidHiddenSelRegs = false;
	131
	132	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
	133	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
	134	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
	135
	136	/* Calculate the offset from CPUMCPU to CPUM. */
	137	for (unsigned i=0;i<pVM->cCPUs;i++)
	138	{
	139	pVM->aCpus[i].cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
	140	Assert((uintptr_t)&pVM->aCpus[i].cpum - pVM->aCpus[i].cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
	141	}
131	142
132	143	/*
…	…
628	639
629	640	/**
630		* Queries the pointer to the internal CPUMCTX structure
631		*
632		* @returns VBox status code.
633		* @param pVM Handle to the virtual machine.
634		* @param ppCtx Receives the CPUMCTX GC pointer when successful.
635		*/
636		~~VMMR3DECL(int) CPUMR3QueryGuestCtxRCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)~~
637		{
638		~~LogFlow(("CPUMR3QueryGuestCtxRCPtr\n"));~~
639		/*
640		* Store the address. (Later we might check how's calling, thus the RC.)
641		*/
642		*ppCtx = VM_RC_ADDR(pVM, &pVM->cpum.s.Guest);
643		~~return VINF_SUCCESS;~~
644		}
645
646
647		/**
648	641	* Terminates the CPUM.
649	642	*
…	…
684	677	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
685	678	{
686		PCPUMCTX pCtx = &pVM->cpum.s.Guest;
687
688		/*
689		* Initialize everything to ZERO first.
690		*/
691		uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
692		memset(pCtx, 0, sizeof(*pCtx));
693		pVM->cpum.s.fUseFlags = fUseFlags;
694
695		pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
696		pCtx->eip = 0x0000fff0;
697		pCtx->edx = 0x00000600; /* P6 processor */
698		pCtx->eflags.Bits.u1Reserved0 = 1;
699
700		pCtx->cs = 0xf000;
701		pCtx->csHid.u64Base = UINT64_C(0xffff0000);
702		pCtx->csHid.u32Limit = 0x0000ffff;
703		pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
704		pCtx->csHid.Attr.n.u1Present = 1;
705		pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
706
707		pCtx->dsHid.u32Limit = 0x0000ffff;
708		pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
709		pCtx->dsHid.Attr.n.u1Present = 1;
710		pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
711
712		pCtx->esHid.u32Limit = 0x0000ffff;
713		pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
714		pCtx->esHid.Attr.n.u1Present = 1;
715		pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
716
717		pCtx->fsHid.u32Limit = 0x0000ffff;
718		pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
719		pCtx->fsHid.Attr.n.u1Present = 1;
720		pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
721
722		pCtx->gsHid.u32Limit = 0x0000ffff;
723		pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
724		pCtx->gsHid.Attr.n.u1Present = 1;
725		pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
726
727		pCtx->ssHid.u32Limit = 0x0000ffff;
728		pCtx->ssHid.Attr.n.u1Present = 1;
729		pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
730		pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
731
732		pCtx->idtr.cbIdt = 0xffff;
733		pCtx->gdtr.cbGdt = 0xffff;
734
735		pCtx->ldtrHid.u32Limit = 0xffff;
736		pCtx->ldtrHid.Attr.n.u1Present = 1;
737		pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
738
739		pCtx->trHid.u32Limit = 0xffff;
740		pCtx->trHid.Attr.n.u1Present = 1;
741		pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
742
743		pCtx->dr[6] = X86_DR6_INIT_VAL;
744		pCtx->dr[7] = X86_DR7_INIT_VAL;
745
746		pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
747		pCtx->fpu.FCW = 0x37f;
748
749		/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
750		pCtx->fpu.MXCSR = 0x1F80;
751
752		/* Init PAT MSR */
753		pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
754
755		/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
756		* The Intel docs don't mention it.
757		*/
758		pCtx->msrEFER = 0;
	679	/* @todo anything different for VCPU > 0? */
	680	for (unsigned i=0;i<pVM->cCPUs;i++)
	681	{
	682	PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
	683
	684	/*
	685	* Initialize everything to ZERO first.
	686	*/
	687	uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
	688	memset(pCtx, 0, sizeof(*pCtx));
	689	pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
	690
	691	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
	692	pCtx->eip = 0x0000fff0;
	693	pCtx->edx = 0x00000600; /* P6 processor */
	694	pCtx->eflags.Bits.u1Reserved0 = 1;
	695
	696	pCtx->cs = 0xf000;
	697	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
	698	pCtx->csHid.u32Limit = 0x0000ffff;
	699	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
	700	pCtx->csHid.Attr.n.u1Present = 1;
	701	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
	702
	703	pCtx->dsHid.u32Limit = 0x0000ffff;
	704	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
	705	pCtx->dsHid.Attr.n.u1Present = 1;
	706	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
	707
	708	pCtx->esHid.u32Limit = 0x0000ffff;
	709	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
	710	pCtx->esHid.Attr.n.u1Present = 1;
	711	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
	712
	713	pCtx->fsHid.u32Limit = 0x0000ffff;
	714	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
	715	pCtx->fsHid.Attr.n.u1Present = 1;
	716	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
	717
	718	pCtx->gsHid.u32Limit = 0x0000ffff;
	719	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
	720	pCtx->gsHid.Attr.n.u1Present = 1;
	721	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
	722
	723	pCtx->ssHid.u32Limit = 0x0000ffff;
	724	pCtx->ssHid.Attr.n.u1Present = 1;
	725	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
	726	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
	727
	728	pCtx->idtr.cbIdt = 0xffff;
	729	pCtx->gdtr.cbGdt = 0xffff;
	730
	731	pCtx->ldtrHid.u32Limit = 0xffff;
	732	pCtx->ldtrHid.Attr.n.u1Present = 1;
	733	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
	734
	735	pCtx->trHid.u32Limit = 0xffff;
	736	pCtx->trHid.Attr.n.u1Present = 1;
	737	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
	738
	739	pCtx->dr[6] = X86_DR6_INIT_VAL;
	740	pCtx->dr[7] = X86_DR7_INIT_VAL;
	741
	742	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
	743	pCtx->fpu.FCW = 0x37f;
	744
	745	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
	746	pCtx->fpu.MXCSR = 0x1F80;
	747
	748	/* Init PAT MSR */
	749	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
	750
	751	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
	752	* The Intel docs don't mention it.
	753	*/
	754	pCtx->msrEFER = 0;
	755	}
759	756	}
760	757
…	…
776	773	*/
777	774	SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
778		SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
779		SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
780		SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
	775
	776	for (unsigned i=0;i<pVM->cCPUs;i++)
	777	{
	778	SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
	779	SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fUseFlags);
	780	SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fChanged);
	781	}
781	782
782	783	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
…	…
809	810	{
810	811	#define CPUMCTX16_LOADREG(RegName) \
811		pVM->cpum.s.Guest.RegName = pCpumctx16->RegName;
	812	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
812	813
813	814	#define CPUMCTX16_LOADDRXREG(RegName) \
814		pVM->cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
	815	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
815	816
816	817	#define CPUMCTX16_LOADHIDREG(RegName) \
817		pVM->cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
818		pVM->cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
819		pVM->cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
	818	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
	819	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
	820	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
820	821
821	822	#define CPUMCTX16_LOADSEGREG(RegName) \
822		pVM->cpum.s.Guest.RegName = pCpumctx16->RegName; \
	823	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
823	824	CPUMCTX16_LOADHIDREG(RegName);
824	825
825		pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
	826	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
826	827
827	828	CPUMCTX16_LOADREG(rax);
…	…
866	867	CPUMCTX16_LOADDRXREG(7);
867	868
868		pVM->cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
869		pVM->cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
870		pVM->cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
871		pVM->cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
	869	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
	870	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
	871	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
	872	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
872	873
873	874	CPUMCTX16_LOADREG(ldtr);
874	875	CPUMCTX16_LOADREG(tr);
875	876
876		pVM->cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
	877	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
877	878
878	879	CPUMCTX16_LOADREG(msrEFER);
…	…
931	932	{
932	933	CPUMCTX_VER1_6 cpumctx16;
933		memset(&pVM->~~cpum.s.Guest, 0, sizeof(pVM->~~cpum.s.Guest));
	934	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
934	935	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
935	936
936	937	/* Save the old cpumctx state into the new one. */
937	938	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
	939
	940	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
	941	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
938	942	}
939	943	else
940		SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
941
942		SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
943		SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
	944	{
	945	for (unsigned i=0;i<pVM->cCPUs;i++)
	946	{
	947	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
	948	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
	949	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
	950	}
	951	}
	952
944	953
945	954	uint32_t cElements;
…	…
1304	1313	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1305	1314	pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1306		cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
	1315	/* @todo SMP */
	1316	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
	1317	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1307	1318	}
1308	1319
…	…
1359	1370	* Format the EFLAGS.
1360	1371	*/
1361		PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
	1372	/* @todo SMP */
	1373	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1362	1374	#if HC_ARCH_BITS == 32
1363	1375	uint32_t efl = pCtx->eflags.u32;
…	…
2333	2345	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2334	2346	{
2335		pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
	2347	/* @todo SMP */
	2348	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(pVM);
2336	2349	}
2337	2350

trunk/src/VBox/VMM/CPUMInternal.h

r13742	r13960
251	251	{
252	252	/**
253		* Saved host context. Only valid while inside GC.
254		* Aligned on a 64-byte boundrary.
255		*/
256		~~CPUMHOSTCTX Host;~~
257
258		/**
259	253	* Hypervisor context.
260	254	* Aligned on a 64-byte boundrary.
261	255	*/
262	256	CPUMCTX Hyper;
263
264		/**
265		* Guest context.
266		* Aligned on a 64-byte boundrary.
267		*/
268		~~CPUMCTX Guest;~~
269	257
270	258	/** Pointer to the current hypervisor core context - R3Ptr. */
…	…
275	263	RCPTRTYPE(PCPUMCTXCORE) pHyperCoreRC;
276	264
277		/** Use flags.
278		* These flags indicates both what is to be used and what have been used.
279		*/
280		uint32_t fUseFlags;
281
282		/** Changed flags.
283		* These flags indicates to REM (and others) which important guest
284		* registers which has been changed since last time the flags were cleared.
285		* See the CPUM_CHANGED_* defines for what we keep track of.
286		*/
287		uint32_t fChanged;
	265	/* Offset from CPUM to CPUMCPU for the first CPU. */
	266	uint32_t ulOffCPUMCPU;
288	267
289	268	/** Hidden selector registers state.
…	…
333	312
334	313	/** Align the next member, and thereby the structure, on a 64-byte boundrary. */
335		uint8_t abPadding2[HC_ARCH_BITS == 32 ? ~~56 : 44~~];
	314	uint8_t abPadding2[HC_ARCH_BITS == 32 ? 60 : 48];
336	315
337	316	/**
…	…
350	329	{
351	330	/**
	331	* Saved host context. Only valid while inside GC.
	332	* Aligned on a 64-byte boundrary.
	333	*/
	334	CPUMHOSTCTX Host;
	335
	336	/**
352	337	* Guest context.
353	338	* Aligned on a 64-byte boundrary.
354	339	*/
355	340	CPUMCTX Guest;
356		} CPUMCPU;
	341
	342	/** Use flags.
	343	* These flags indicates both what is to be used and what has been used.
	344	*/
	345	uint32_t fUseFlags;
	346
	347	/** Changed flags.
	348	* These flags indicates to REM (and others) which important guest
	349	* registers which has been changed since last time the flags were cleared.
	350	* See the CPUM_CHANGED_* defines for what we keep track of.
	351	*/
	352	uint32_t fChanged;
	353
	354	/* Offset to CPUM. (subtract from the pointer to get to CPUM) */
	355	uint32_t ulOffCPUM;
	356
	357	/* Round to 16 byte size. */
	358	uint32_t uPadding;
	359	} CPUMCPU, *PCPUMCPU;
357	360	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
358	361	typedef CPUMCPU *PCPUMCPU;
…	…
360	363	__BEGIN_DECLS
361	364
362		DECLASM(int) CPUMHandleLazyFPUAsm(PCPUM pCPUM);
363		DECLASM(int) CPUMRestoreHostFPUStateAsm(PCPUM pCPUM);
	365	DECLASM(int) CPUMHandleLazyFPUAsm(PCPUMCPU pCPUM);
	366	DECLASM(int) CPUMRestoreHostFPUStateAsm(PCPUMCPU pCPUM);
364	367	DECLASM(void) CPUMLoadFPUAsm(PCPUMCTX pCtx);
365	368	DECLASM(void) CPUMSaveFPUAsm(PCPUMCTX pCtx);

trunk/src/VBox/VMM/CPUMInternal.mac

r12657	r13960
50	50
51	51	struc CPUM
	52	;
	53	; Hypervisor Context.
	54	;
	55	alignb 64 ; the padding
	56	.Hyper.fpu resb FPUSTATE_SIZE
	57
	58	.Hyper.edi resq 1
	59	.Hyper.esi resq 1
	60	.Hyper.ebp resq 1
	61	.Hyper.eax resq 1
	62	.Hyper.ebx resq 1
	63	.Hyper.edx resq 1
	64	.Hyper.ecx resq 1
	65	.Hyper.esp resq 1
	66	.Hyper.lss_esp resd 1
	67	.Hyper.ss resw 1
	68	.Hyper.ssPadding resw 1
	69	.Hyper.gs resw 1
	70	.Hyper.gsPadding resw 1
	71	.Hyper.fs resw 1
	72	.Hyper.fsPadding resw 1
	73	.Hyper.es resw 1
	74	.Hyper.esPadding resw 1
	75	.Hyper.ds resw 1
	76	.Hyper.dsPadding resw 1
	77	.Hyper.cs resw 1
	78	.Hyper.csPadding resw 3
	79	.Hyper.eflags resq 1
	80	.Hyper.eip resq 1
	81	.Hyper.r8 resq 1
	82	.Hyper.r9 resq 1
	83	.Hyper.r10 resq 1
	84	.Hyper.r11 resq 1
	85	.Hyper.r12 resq 1
	86	.Hyper.r13 resq 1
	87	.Hyper.r14 resq 1
	88	.Hyper.r15 resq 1
	89
	90	.Hyper.esHid.u64Base resq 1
	91	.Hyper.esHid.u32Limit resd 1
	92	.Hyper.esHid.Attr resd 1
	93
	94	.Hyper.csHid.u64Base resq 1
	95	.Hyper.csHid.u32Limit resd 1
	96	.Hyper.csHid.Attr resd 1
	97
	98	.Hyper.ssHid.u64Base resq 1
	99	.Hyper.ssHid.u32Limit resd 1
	100	.Hyper.ssHid.Attr resd 1
	101
	102	.Hyper.dsHid.u64Base resq 1
	103	.Hyper.dsHid.u32Limit resd 1
	104	.Hyper.dsHid.Attr resd 1
	105
	106	.Hyper.fsHid.u64Base resq 1
	107	.Hyper.fsHid.u32Limit resd 1
	108	.Hyper.fsHid.Attr resd 1
	109
	110	.Hyper.gsHid.u64Base resq 1
	111	.Hyper.gsHid.u32Limit resd 1
	112	.Hyper.gsHid.Attr resd 1
	113
	114	.Hyper.cr0 resq 1
	115	.Hyper.cr2 resq 1
	116	.Hyper.cr3 resq 1
	117	.Hyper.cr4 resq 1
	118
	119	.Hyper.dr resq 8
	120
	121	.Hyper.gdtr resb 10 ; GDT limit + linear address
	122	.Hyper.gdtrPadding resw 1
	123	.Hyper.idtr resb 10 ; IDT limit + linear address
	124	.Hyper.idtrPadding resw 1
	125	.Hyper.ldtr resw 1
	126	.Hyper.ldtrPadding resw 1
	127	.Hyper.tr resw 1
	128	.Hyper.trPadding resw 1
	129
	130	.Hyper.SysEnter.cs resb 8
	131	.Hyper.SysEnter.eip resb 8
	132	.Hyper.SysEnter.esp resb 8
	133
	134	.Hyper.msrEFER resb 8
	135	.Hyper.msrSTAR resb 8
	136	.Hyper.msrPAT resb 8
	137	.Hyper.msrLSTAR resb 8
	138	.Hyper.msrCSTAR resb 8
	139	.Hyper.msrSFMASK resb 8
	140	.Hyper.msrKERNELGSBASE resb 8
	141
	142	.Hyper.ldtrHid.u64Base resq 1
	143	.Hyper.ldtrHid.u32Limit resd 1
	144	.Hyper.ldtrHid.Attr resd 1
	145
	146	.Hyper.trHid.u64Base resq 1
	147	.Hyper.trHid.u32Limit resd 1
	148	.Hyper.trHid.Attr resd 1
	149
	150	;
	151	; Other stuff.
	152	;
	153	alignb 64
	154	; hypervisor core context.
	155	.pHyperCoreR3 RTR3PTR_RES 1
	156	.pHyperCoreR0 RTR0PTR_RES 1
	157	.pHyperCoreRC RTRCPTR_RES 1
	158	;...
	159	.ulOffCPUMCPU resd 1
	160	.fValidHiddenSelRegs resd 1
	161
	162	; CPUID eax=1
	163	.CPUFeatures.edx resd 1
	164	.CPUFeatures.ecx resd 1
	165
	166	; CPUID eax=0x80000001
	167	.CPUFeaturesExt.edx resd 1
	168	.CPUFeaturesExt.ecx resd 1
	169
	170	.enmCPUVendor resd 1
	171
	172	; CR4 masks
	173	.CR4.AndMask resd 1
	174	.CR4.OrMask resd 1
	175	; entered rawmode?
	176	.fRawEntered resb 1
	177	%if RTHCPTR_CB == 8
	178	.abPadding resb 7
	179	%else
	180	.abPadding resb 3
	181	%endif
	182
	183	; CPUID leafs
	184	.aGuestCpuIdStd resb 16*6
	185	.aGuestCpuIdExt resb 16*10
	186	.aGuestCpuIdCentaur resb 16*4
	187	.GuestCpuIdDef resb 16
	188
	189	alignb 64
	190	; CPUMCTX debug stuff...
	191	.GuestEntry resb 1024
	192	endstruc
	193
	194	struc CPUMCPU
52	195	;
53	196	; Host context state
…	…
160	303	%endif ; 64-bit
161	304
162
163		;
164		~~; Hypervisor Context.~~
165		;
166		~~alignb 64 ; the padding~~
167		~~.Hyper.fpu resb FPUSTATE_SIZE~~
168
169		~~.Hyper.edi resq 1~~
170		~~.Hyper.esi resq 1~~
171		~~.Hyper.ebp resq 1~~
172		~~.Hyper.eax resq 1~~
173		~~.Hyper.ebx resq 1~~
174		~~.Hyper.edx resq 1~~
175		~~.Hyper.ecx resq 1~~
176		~~.Hyper.esp resq 1~~
177		~~.Hyper.lss_esp resd 1~~
178		~~.Hyper.ss resw 1~~
179		~~.Hyper.ssPadding resw 1~~
180		~~.Hyper.gs resw 1~~
181		~~.Hyper.gsPadding resw 1~~
182		~~.Hyper.fs resw 1~~
183		~~.Hyper.fsPadding resw 1~~
184		~~.Hyper.es resw 1~~
185		~~.Hyper.esPadding resw 1~~
186		~~.Hyper.ds resw 1~~
187		~~.Hyper.dsPadding resw 1~~
188		~~.Hyper.cs resw 1~~
189		~~.Hyper.csPadding resw 3~~
190		~~.Hyper.eflags resq 1~~
191		~~.Hyper.eip resq 1~~
192		~~.Hyper.r8 resq 1~~
193		~~.Hyper.r9 resq 1~~
194		~~.Hyper.r10 resq 1~~
195		~~.Hyper.r11 resq 1~~
196		~~.Hyper.r12 resq 1~~
197		~~.Hyper.r13 resq 1~~
198		~~.Hyper.r14 resq 1~~
199		~~.Hyper.r15 resq 1~~
200
201		~~.Hyper.esHid.u64Base resq 1~~
202		~~.Hyper.esHid.u32Limit resd 1~~
203		~~.Hyper.esHid.Attr resd 1~~
204
205		~~.Hyper.csHid.u64Base resq 1~~
206		~~.Hyper.csHid.u32Limit resd 1~~
207		~~.Hyper.csHid.Attr resd 1~~
208
209		~~.Hyper.ssHid.u64Base resq 1~~
210		~~.Hyper.ssHid.u32Limit resd 1~~
211		~~.Hyper.ssHid.Attr resd 1~~
212
213		~~.Hyper.dsHid.u64Base resq 1~~
214		~~.Hyper.dsHid.u32Limit resd 1~~
215		~~.Hyper.dsHid.Attr resd 1~~
216
217		~~.Hyper.fsHid.u64Base resq 1~~
218		~~.Hyper.fsHid.u32Limit resd 1~~
219		~~.Hyper.fsHid.Attr resd 1~~
220
221		~~.Hyper.gsHid.u64Base resq 1~~
222		~~.Hyper.gsHid.u32Limit resd 1~~
223		~~.Hyper.gsHid.Attr resd 1~~
224
225		~~.Hyper.cr0 resq 1~~
226		~~.Hyper.cr2 resq 1~~
227		~~.Hyper.cr3 resq 1~~
228		~~.Hyper.cr4 resq 1~~
229
230		~~.Hyper.dr resq 8~~
231
232		~~.Hyper.gdtr resb 10 ; GDT limit + linear address~~
233		~~.Hyper.gdtrPadding resw 1~~
234		~~.Hyper.idtr resb 10 ; IDT limit + linear address~~
235		~~.Hyper.idtrPadding resw 1~~
236		~~.Hyper.ldtr resw 1~~
237		~~.Hyper.ldtrPadding resw 1~~
238		~~.Hyper.tr resw 1~~
239		~~.Hyper.trPadding resw 1~~
240
241		~~.Hyper.SysEnter.cs resb 8~~
242		~~.Hyper.SysEnter.eip resb 8~~
243		~~.Hyper.SysEnter.esp resb 8~~
244
245		~~.Hyper.msrEFER resb 8~~
246		~~.Hyper.msrSTAR resb 8~~
247		~~.Hyper.msrPAT resb 8~~
248		~~.Hyper.msrLSTAR resb 8~~
249		~~.Hyper.msrCSTAR resb 8~~
250		~~.Hyper.msrSFMASK resb 8~~
251		~~.Hyper.msrKERNELGSBASE resb 8~~
252
253		~~.Hyper.ldtrHid.u64Base resq 1~~
254		~~.Hyper.ldtrHid.u32Limit resd 1~~
255		~~.Hyper.ldtrHid.Attr resd 1~~
256
257		~~.Hyper.trHid.u64Base resq 1~~
258		~~.Hyper.trHid.u32Limit resd 1~~
259		~~.Hyper.trHid.Attr resd 1~~
260
261
262	305	;
263	306	; Guest context state
…	…
359	402	.Guest.trHid.Attr resd 1
360	403
361
362		;
363		~~; Other stuff.~~
364		;
365		~~alignb 64~~
366		~~; hypervisor core context.~~
367		~~.pHyperCoreR3 RTR3PTR_RES 1~~
368		~~.pHyperCoreR0 RTR0PTR_RES 1~~
369		~~.pHyperCoreRC RTRCPTR_RES 1~~
370		~~;...~~
371	404	.fUseFlags resd 1
372	405	.fChanged resd 1
373		.fValidHiddenSelRegs resd 1
374
375		; CPUID eax=1
376		.CPUFeatures.edx resd 1
377		.CPUFeatures.ecx resd 1
378
379		; CPUID eax=0x80000001
380		.CPUFeaturesExt.edx resd 1
381		.CPUFeaturesExt.ecx resd 1
382
383		.enmCPUVendor resd 1
384
385		; CR4 masks
386		.CR4.AndMask resd 1
387		.CR4.OrMask resd 1
388		; entered rawmode?
389		.fRawEntered resb 1
390		%if RTHCPTR_CB == 8
391		.abPadding resb 7
392		%else
393		.abPadding resb 3
394		%endif
395
396		; CPUID leafs
397		.aGuestCpuIdStd resb 16*6
398		.aGuestCpuIdExt resb 16*10
399		.aGuestCpuIdCentaur resb 16*4
400		.GuestCpuIdDef resb 16
401
402		alignb 64
403		; CPUMCTX debug stuff...
404		.GuestEntry resb 1024
	406	.ulOffCPUM resd 1
	407	.uPadding resd 1
405	408	endstruc
406	409
	410
	411	;;
	412	; Converts the CPUM pointer to CPUMCPU (for the first VMCPU)
	413	; @param %1 register name
	414	%macro CPUMCPU_FROM_CPUM 1
	415	add %1, [%1 + CPUM.ulOffCPUMCPU]
	416	%endmacro
	417
	418	;;
	419	; Converts the CPUMCPU pointer to CPUM (for the first VMCPU)
	420	; @param %1 register name
	421	%macro CPUM_FROM_CPUMCPU 1
	422	sub %1, [%1 + CPUMCPU.ulOffCPUM]
	423	%endmacro

trunk/src/VBox/VMM/PATM/PATM.cpp

r13834	r13960
346	346
347	347	/* Needed for future patching of sldt/sgdt/sidt/str etc. */
348		rc = CPUMR3QueryGuestCtxRCPtr(pVM, &pVM->patm.s.pCPUMCtxGC);
349		AssertRCReturn(rc, rc);
	348	pVM->patm.s.pCPUMCtxGC = VM_RC_ADDR(pVM, CPUMQueryGuestCtxPtr(pVM));
350	349
351	350	Assert(pVM->patm.s.PatchLookupTreeHC);

trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm

r13832	r13960
41	41	%define ENABLE_WRITE_PROTECTION 1
42	42
43		~~;; @def CPUM_REG~~
44		~~; The register which we load the CPUM pointer into.~~
45		~~%ifdef RT_ARCH_AMD64~~
46		~~%define CPUM_REG rdx~~
47		~~%else~~
48		~~%define CPUM_REG edx~~
49		~~%endif~~
50
51	43	BEGINCODE
52	44
…	…
64	56	; @returns 0 if caller should continue execution.
65	57	; @returns VINF_EM_RAW_GUEST_TRAP if a guest trap should be generated.
66		; @param pCPUM ~~x86:[esp+4] GCC:rdi MSC:rcx CPUM~~ pointer
	58	; @param pCPUMCPU x86:[esp+4] GCC:rdi MSC:rcx CPUMCPU pointer
67	59	;
68	60	align 16
…	…
107	99	mov xDX, dword [esp + 4]
108	100	%endif
109		test dword [xDX + CPUM.fUseFlags], CPUM_USED_FPU
	101	test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
110	102	jz hlfpua_not_loaded
111	103	jmp hlfpua_to_host
…	…
116	108	align 16
117	109	hlfpua_not_loaded:
118		mov eax, [xDX + CPUM.Guest.cr0]
	110	mov eax, [xDX + CPUMCPU.Guest.cr0]
119	111	and eax, X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS
120	112	%ifdef RT_ARCH_AMD64
…	…
164	156	%endif
165	157	%ifndef RT_ARCH_AMD64
166		test dword [xDX + CPUM.CPUFeatures.edx], X86_CPUID_FEATURE_EDX_FXSR
	158	mov eax, edx
	159	; Calculate the PCPUM pointer
	160	sub eax, [edx + CPUMCPU.ulOffCPUM]
	161	test dword [eax + CPUM.CPUFeatures.edx], X86_CPUID_FEATURE_EDX_FXSR
167	162	jz short hlfpua_no_fxsave
168	163	%endif
169	164
170		fxsave [xDX + CPUM.Host.fpu]
171		or dword [xDX + CPUM.fUseFlags], (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)
172		fxrstor [xDX + CPUM.Guest.fpu]
	165	fxsave [xDX + CPUMCPU.Host.fpu]
	166	or dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)
	167	fxrstor [xDX + CPUMCPU.Guest.fpu]
173	168	hlfpua_finished_switch:
174	169	%ifdef IN_RC
…	…
182	177	; legacy support.
183	178	hlfpua_no_fxsave:
184		fnsave [xDX + CPUM.Host.fpu]
185		or dword [xDX + CPUM.fUseFlags], dword (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM) ; yasm / nasm
186		mov eax, [xDX + CPUM.Guest.fpu] ; control word
	179	fnsave [xDX + CPUMCPU.Host.fpu]
	180	or dword [xDX + CPUMCPU.fUseFlags], dword (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_RE