Changeset 13879
- Timestamp:
- 11/05/08 17:11:03 (2 months ago)
- Files:
-
- trunk/include/VBox/hwaccm.h (modified) (1 diff)
- trunk/include/VBox/vm.h (modified) (1 diff)
- trunk/src/VBox/VMM/HWACCM.cpp (modified) (4 diffs)
- trunk/src/VBox/VMM/HWACCMInternal.h (modified) (9 diffs)
- trunk/src/VBox/VMM/VMMInternal.h (modified) (2 diffs)
- trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp (modified) (9 diffs)
- trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (17 diffs)
- trunk/src/VBox/VMM/VMMR0/HWSVMR0.h (modified) (5 diffs)
- trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (35 diffs)
- trunk/src/VBox/VMM/VMMR0/HWVMXR0.h (modified) (5 diffs)
- trunk/src/VBox/VMM/VMMR0/VMMR0.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
trunk/include/VBox/hwaccm.h
r13873 r13879 124 124 */ 125 125 VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM); 126 VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, uintptr_t idVCpu);127 VMMR0DECL(int) HWACCMR0Enter(PVM pVM, RTCPUID idVCpu);128 VMMR0DECL(int) HWACCMR0Leave(PVM pVM, RTCPUID idVCpu);129 VMMR0DECL(int) HWACCMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt);126 VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu); 127 VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu); 128 VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu); 129 VMMR0DECL(int) HWACCMR0InvalidatePage(PVM pVM, PVMCPU pVCpu); 130 130 VMMR0DECL(int) HWACCMR0FlushTLB(PVM pVM); 131 131 VMMR0DECL(bool) HWACCMR0SuspendPending(); trunk/include/VBox/vm.h
r13832 r13879 133 133 struct HWACCMCPU s; 134 134 #endif 135 char padding[ 32]; /* multiple of 32 */135 char padding[512]; /* multiple of 32 */ 136 136 } hwaccm; 137 137 trunk/src/VBox/VMM/HWACCM.cpp
r13826 r13879 106 106 /* On first entry we'll sync everything. */ 107 107 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL; 108 109 pVM->hwaccm.s.vmx.cr0_mask = 0;110 pVM->hwaccm.s.vmx.cr4_mask = 0;111 108 112 109 /* … … 586 583 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum)); 587 584 588 LogRel(("HWACCM: VMCS physaddr = %RHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));589 585 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys)); 590 586 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys)); 587 588 for (unsigned i=0;i<pVM->cCPUs;i++) 589 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys)); 591 590 592 591 #ifdef HWACCM_VTX_WITH_EPT … … 878 877 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL; 879 878 880 pVM->hwaccm.s.vmx.cr0_mask = 0; 881 pVM->hwaccm.s.vmx.cr4_mask = 0; 879 for (unsigned i=0;i<pVM->cCPUs;i++) 880 { 881 pVM->aCpus[i].hwaccm.s.vmx.cr0_mask = 0; 882 pVM->aCpus[i].hwaccm.s.vmx.cr4_mask = 0; 883 } 882 884 883 885 pVM->hwaccm.s.Event.fPending = false; … … 1060 1062 VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode) 1061 1063 { 1062 switch(iStatusCode) 1063 { 1064 case VERR_VMX_INVALID_VMCS_FIELD: 1065 break; 1066 1067 case VERR_VMX_INVALID_VMCS_PTR: 1068 LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current pointer %RGp vs %RGp\n", pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->hwaccm.s.vmx.pVMCSPhys)); 1069 LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current VMCS version %x\n", pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision)); 1070 break; 1071 1072 case VERR_VMX_UNABLE_TO_START_VM: 1073 LogRel(("VERR_VMX_UNABLE_TO_START_VM: instruction error %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastInstrError)); 1074 LogRel(("VERR_VMX_UNABLE_TO_START_VM: exit reason %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastExitReason)); 1075 break; 1076 1077 case VERR_VMX_UNABLE_TO_RESUME_VM: 1078 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: instruction error %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastInstrError)); 1079 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: exit reason %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastExitReason)); 1080 break; 1081 1082 case VERR_VMX_INVALID_VMXON_PTR: 1083 break; 1064 for (unsigned i=0;i<pVM->cCPUs;i++) 1065 { 1066 switch(iStatusCode) 1067 { 1068 case VERR_VMX_INVALID_VMCS_FIELD: 1069 break; 1070 1071 case VERR_VMX_INVALID_VMCS_PTR: 1072 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys)); 1073 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision)); 1074 break; 1075 1076 case VERR_VMX_UNABLE_TO_START_VM: 1077 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->hwaccm.s.vmx.lasterror.ulLastInstrError)); 1078 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->hwaccm.s.vmx.lasterror.ulLastExitReason)); 1079 break; 1080 1081 case VERR_VMX_UNABLE_TO_RESUME_VM: 1082 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->hwaccm.s.vmx.lasterror.ulLastInstrError)); 1083 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->hwaccm.s.vmx.lasterror.ulLastExitReason)); 1084 break; 1085 1086 case VERR_VMX_INVALID_VMXON_PTR: 1087 break; 1088 } 1084 1089 } 1085 1090 } trunk/src/VBox/VMM/HWACCMInternal.h
r13872 r13879 133 133 #define HWACCM_SSM_VERSION 3 134 134 135 /* Per-cpu information. */135 /* Per-cpu information. (host) */ 136 136 typedef struct 137 137 { … … 229 229 bool fVPID; 230 230 231 /** R0 memory object for the VM control structure (VMCS). */232 RTR0MEMOBJ pMemObjVMCS;233 /** Physical address of the VM control structure (VMCS). */234 RTHCPHYS pVMCSPhys;235 /** Virtual address of the VM control structure (VMCS). */236 R0PTRTYPE(void *) pVMCS;237 238 231 /** Virtual address of the TSS page used for real mode emulation. */ 239 232 R3PTRTYPE(PVBOXTSS) pRealModeTSS; … … 278 271 279 272 /** Ring 0 handlers for VT-x. */ 280 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));281 273 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM)); 282 274 … … 287 279 /** Host CR4 value (set by ring-0 VMX init) */ 288 280 uint64_t hostCR4; 289 290 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */291 uint64_t proc_ctls;292 293 /** Current CR0 mask. */294 uint64_t cr0_mask;295 /** Current CR4 mask. */296 uint64_t cr4_mask;297 298 /** Current EPTP. */299 RTHCPHYS GCPhysEPTP;300 281 301 282 /** VMX MSR values */ … … 356 337 bool fAlwaysFlushTLB; 357 338 358 /** R0 memory object for the VM control block (VMCB). */359 RTR0MEMOBJ pMemObjVMCB;360 /** Physical address of the VM control block (VMCB). */361 RTHCPHYS pVMCBPhys;362 /** Virtual address of the VM control block (VMCB). */363 R0PTRTYPE(void *) pVMCB;364 365 339 /** R0 memory object for the host VM control block (VMCB). */ 366 340 RTR0MEMOBJ pMemObjVMCBHost; … … 383 357 /** Virtual address of the MSR bitmap. */ 384 358 R0PTRTYPE(void *) pMSRBitmap; 385 386 /** Ring 0 handlers for VT-x. */387 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));388 359 389 360 /** SVM revision. */ … … 501 472 * See HWACCMCPU2VM(). */ 502 473 RTUINT offVMCPU; 474 475 struct 476 { 477 /** R0 memory object for the VM control structure (VMCS). */ 478 RTR0MEMOBJ pMemObjVMCS; 479 /** Physical address of the VM control structure (VMCS). */ 480 RTHCPHYS pVMCSPhys; 481 /** Virtual address of the VM control structure (VMCS). */ 482 R0PTRTYPE(void *) pVMCS; 483 484 /** Ring 0 handlers for VT-x. */ 485 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx)); 486 487 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */ 488 uint64_t proc_ctls; 489 490 /** Current CR0 mask. */ 491 uint64_t cr0_mask; 492 /** Current CR4 mask. */ 493 uint64_t cr4_mask; 494 495 /** Current EPTP. */ 496 RTHCPHYS GCPhysEPTP; 497 } vmx; 498 499 struct 500 { 501 /** R0 memory object for the VM control block (VMCB). */ 502 RTR0MEMOBJ pMemObjVMCB; 503 /** Physical address of the VM control block (VMCB). */ 504 RTHCPHYS pVMCBPhys; 505 /** Virtual address of the VM control block (VMCB). */ 506 R0PTRTYPE(void *) pVMCB; 507 508 /** Ring 0 handlers for VT-x. */ 509 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx)); 510 511 } svm; 512 503 513 } HWACCMCPU; 504 514 /** Pointer to HWACCM VM instance data. */ … … 519 529 520 530 /* Dummy callback handlers. */ 521 VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, RTCPUID idVCpu, PHWACCM_CPUINFO pCpu);522 VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx);531 VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu); 532 VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 523 533 VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys); 524 534 VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys); … … 526 536 VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM); 527 537 VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM); 528 VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx);529 VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, RTCPUID idVCpu);530 VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx);538 VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 539 VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu); 540 VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 531 541 532 542 #endif /* IN_RING0 */ trunk/src/VBox/VMM/VMMInternal.h
r13873 r13879 450 450 * @param pVM The VM handle. 451 451 */ 452 typedef DECLCALLBACK(int) FNVMMR0SETJMP(PVM pVM, uintptr_t idCpu);452 typedef DECLCALLBACK(int) FNVMMR0SETJMP(PVM pVM, PVMCPU pVCpu); 453 453 /** Pointer to FNVMMR0SETJMP(). */ 454 454 typedef FNVMMR0SETJMP *PFNVMMR0SETJMP; … … 466 466 * @param pVM The argument of that function. 467 467 */ 468 DECLASM(int) vmmR0CallHostSetJmp(PVMMR0JMPBUF pJmpBuf, PFNVMMR0SETJMP pfn, PVM pVM, uintptr_t idCpu);468 DECLASM(int) vmmR0CallHostSetJmp(PVMMR0JMPBUF pJmpBuf, PFNVMMR0SETJMP pfn, PVM pVM, PVMCPU pVCpu); 469 469 470 470 /** trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp
r13873 r13879 65 65 66 66 /** Ring 0 handlers for VT-x and AMD-V. */ 67 DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, RTCPUID idVCpu, PHWACCM_CPUINFO pCpu));68 DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx));69 DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, RTCPUID idVCpu));70 DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx));71 DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx));67 DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)); 68 DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)); 69 DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu)); 70 DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)); 71 DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)); 72 72 DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)); 73 73 DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)); … … 865 865 * @returns VBox status code. 866 866 * @param pVM The VM to operate on. 867 * @param idVCpu VMCPUD id.868 */ 869 VMMR0DECL(int) HWACCMR0Enter(PVM pVM, RTCPUID idVCpu)867 * @param pVCpu VMCPUD id. 868 */ 869 VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu) 870 870 { 871 871 PCPUMCTX pCtx; … … 895 895 pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF); 896 896 897 rc = HWACCMR0Globals.pfnEnterSession(pVM, idVCpu, pCpu);897 rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu); 898 898 AssertRC(rc); 899 899 /* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */ 900 rc |= HWACCMR0Globals.pfnSaveHostState(pVM, idVCpu);900 rc |= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu); 901 901 AssertRC(rc); 902 rc |= HWACCMR0Globals.pfnLoadGuestState(pVM, idVCpu, pCtx);902 rc |= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx); 903 903 AssertRC(rc); 904 904 … … 920 920 * @returns VBox status code. 921 921 * @param pVM The VM to operate on. 922 * @param idVCpu VMCPUD id.923 */ 924 VMMR0DECL(int) HWACCMR0Leave(PVM pVM, RTCPUID idVCpu)922 * @param pVCpu VMCPUD id. 923 */ 924 VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu) 925 925 { 926 926 PCPUMCTX pCtx; … … 946 946 } 947 947 948 rc = HWACCMR0Globals.pfnLeaveSession(pVM, idVCpu, pCtx);948 rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx); 949 949 950 950 #ifdef VBOX_STRICT … … 963 963 * @returns VBox status code. 964 964 * @param pVM The VM to operate on. 965 * @param idVCpu VMCPUD id.966 */ 967 VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, uintptr_t idVCpu)965 * @param pVCpu VMCPUD id. 966 */ 967 VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu) 968 968 { 969 969 CPUMCTX *pCtx; 970 int rc;971 970 RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu); 972 971 #ifdef VBOX_STRICT … … 981 980 pCtx = CPUMQueryGuestCtxPtr(pVM); 982 981 983 return HWACCMR0Globals.pfnRunGuestCode(pVM, idVCpu, pCtx);982 return HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx); 984 983 } 985 984 … … 1280 1279 1281 1280 /* Dummy callback handlers. */ 1282 VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, RTCPUID idVCpu, PHWACCM_CPUINFO pCpu)1281 VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu) 1283 1282 { 1284 1283 return VINF_SUCCESS; 1285 1284 } 1286 1285 1287 VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx)1286 VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 1288 1287 { 1289 1288 return VINF_SUCCESS; … … 1315 1314 } 1316 1315 1317 VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx)1316 VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 1318 1317 { 1319 1318 return VINF_SUCCESS; 1320 1319 } 1321 1320 1322 VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, RTCPUID idVCpu)1321 VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu) 1323 1322 { 1324 1323 return VINF_SUCCESS; 1325 1324 } 1326 1325 1327 VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx)1326 VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 1328 1327 { 1329 1328 return VINF_SUCCESS; trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r13873 r13879 125 125 int rc; 126 126 127 pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;128 127 pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ; 129 128 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ; 130 129 pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ; 131 132 133 /* Allocate one page for the VM control block (VMCB). */134 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);135 if (RT_FAILURE(rc))136 return rc;137 138 pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);139 pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);140 ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCB);141 130 142 131 /* Allocate one page for the host context */ … … 199 188 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true; 200 189 } 190 191 /* Allocate VMCBs for all guest CPUs. */ 192 for (unsigned i=0;i<pVM->cCPUs;i++) 193 { 194 pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ; 195 196 /* Allocate one page for the VM control block (VMCB). */ 197 rc = RTR0MemObjAllocCont(&pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */); 198 if (RT_FAILURE(rc)) 199 return rc; 200 201 pVM->aCpus[i].hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB); 202 pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 0); 203 ASMMemZeroPage(pVM->aCpus[i].hwaccm.s.svm.pVMCB); 204 } 205 201 206 return VINF_SUCCESS; 202 207 } … … 210 215 VMMR0DECL(int) SVMR0TermVM(PVM pVM) 211 216 { 212 if (pVM->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ) 213 { 214 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false); 215 pVM->hwaccm.s.svm.pVMCB = 0; 216 pVM->hwaccm.s.svm.pVMCBPhys = 0; 217 pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ; 217 for (unsigned i=0;i<pVM->cCPUs;i++) 218 { 219 if (pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ) 220 { 221 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, false); 222 pVM->aCpus[i].hwaccm.s.svm.pVMCB = 0; 223 pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = 0; 224 pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ; 225 } 218 226 } 219 227 if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ) … … 256 264 Assert(pVM->hwaccm.s.svm.fSupported); 257 265 258 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB; 259 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR); 260 261 /* Program the control fields. Most of them never have to be changed again. */ 262 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */ 263 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */ 264 if (!pVM->hwaccm.s.fNestedPaging) 265 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4); 266 else 267 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4); 268 269 /* 270 * CR0/3/4 writes must be intercepted for obvious reasons. 271 */ 272 if (!pVM->hwaccm.s.fNestedPaging) 273 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4); 274 else 275 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8); 276 277 /* Intercept all DRx reads and writes by default. Changed later on. */ 278 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF; 279 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF; 280 281 /* Currently we don't care about DRx reads or writes. DRx registers are trashed. 282 * All breakpoints are automatically cleared when the VM exits. 283 */ 284 285 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK; 266 for (unsigned i=0;i<pVM->cCPUs;i++) 267 { 268 pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB; 269 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR); 270 271 /* Program the control fields. Most of them never have to be changed again. */ 272 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */ 273 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */ 274 if (!pVM->hwaccm.s.fNestedPaging) 275 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4); 276 else 277 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4); 278 279 /* 280 * CR0/3/4 writes must be intercepted for obvious reasons. 281 */ 282 if (!pVM->hwaccm.s.fNestedPaging) 283 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4); 284 else 285 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8); 286 287 /* Intercept all DRx reads and writes by default. Changed later on. */ 288 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF; 289 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF; 290 291 /* Currently we don't care about DRx reads or writes. DRx registers are trashed. 292 * All breakpoints are automatically cleared when the VM exits. 293 */ 294 295 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK; 286 296 #ifndef DEBUG 287 if (pVM->hwaccm.s.fNestedPaging)288 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */297 if (pVM->hwaccm.s.fNestedPaging) 298 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */ 289 299 #endif 290 300 291 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR 292 | SVM_CTRL1_INTERCEPT_VINTR 293 | SVM_CTRL1_INTERCEPT_NMI 294 | SVM_CTRL1_INTERCEPT_SMI 295 | SVM_CTRL1_INTERCEPT_INIT 296 | SVM_CTRL1_INTERCEPT_RDPMC 297 | SVM_CTRL1_INTERCEPT_CPUID 298 | SVM_CTRL1_INTERCEPT_RSM 299 | SVM_CTRL1_INTERCEPT_HLT 300 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP 301 | SVM_CTRL1_INTERCEPT_MSR_SHADOW 302 | SVM_CTRL1_INTERCEPT_INVLPG 303 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */ 304 | SVM_CTRL1_INTERCEPT_TASK_SWITCH 305 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */ 306 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */ 307 ; 308 /* With nested paging we don't care about invlpg anymore. */ 309 if (pVM->hwaccm.s.fNestedPaging) 310 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG; 311 312 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */ 313 | SVM_CTRL2_INTERCEPT_VMMCALL 314 | SVM_CTRL2_INTERCEPT_VMLOAD 315 | SVM_CTRL2_INTERCEPT_VMSAVE 316 | SVM_CTRL2_INTERCEPT_STGI 317 | SVM_CTRL2_INTERCEPT_CLGI 318 | SVM_CTRL2_INTERCEPT_SKINIT 319 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */ 320 | SVM_CTRL2_INTERCEPT_WBINVD 321 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */ 322 ; 323 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException)); 324 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1)); 325 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2)); 326 327 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */ 328 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1; 329 /* Ignore the priority in the TPR; just deliver it when we tell it to. */ 330 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; 331 332 /* Set IO and MSR bitmap addresses. */ 333 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys; 334 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys; 335 336 /* No LBR virtualization. */ 337 pVMCB->ctrl.u64LBRVirt = 0; 338 339 /** The ASID must start at 1; the host uses 0. */ 340 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1; 341 342 /** Setup the PAT msr (nested paging only) */ 343 pVMCB->guest.u64GPAT = 0x0007040600070406ULL; 301 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR 302 | SVM_CTRL1_INTERCEPT_VINTR 303 | SVM_CTRL1_INTERCEPT_NMI 304 | SVM_CTRL1_INTERCEPT_SMI 305 | SVM_CTRL1_INTERCEPT_INIT 306 | SVM_CTRL1_INTERCEPT_RDPMC 307 | SVM_CTRL1_INTERCEPT_CPUID 308 | SVM_CTRL1_INTERCEPT_RSM 309 | SVM_CTRL1_INTERCEPT_HLT 310 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP 311 | SVM_CTRL1_INTERCEPT_MSR_SHADOW 312 | SVM_CTRL1_INTERCEPT_INVLPG 313 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */ 314 | SVM_CTRL1_INTERCEPT_TASK_SWITCH 315 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */ 316 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */ 317 ; 318 /* With nested paging we don't care about invlpg anymore. */ 319 if (pVM->hwaccm.s.fNestedPaging) 320 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG; 321 322 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */ 323 | SVM_CTRL2_INTERCEPT_VMMCALL 324 | SVM_CTRL2_INTERCEPT_VMLOAD 325 | SVM_CTRL2_INTERCEPT_VMSAVE 326 | SVM_CTRL2_INTERCEPT_STGI 327 | SVM_CTRL2_INTERCEPT_CLGI 328 | SVM_CTRL2_INTERCEPT_SKINIT 329 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */ 330 | SVM_CTRL2_INTERCEPT_WBINVD 331 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */ 332 ; 333 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException)); 334 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1)); 335 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2)); 336 337 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */ 338 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1; 339 /* Ignore the priority in the TPR; just deliver it when we tell it to. */ 340 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; 341 342 /* Set IO and MSR bitmap addresses. */ 343 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys; 344 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys; 345 346 /* No LBR virtualization. */ 347 pVMCB->ctrl.u64LBRVirt = 0; 348 349 /** The ASID must start at 1; the host uses 0. */ 350 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1; 351 352 /** Setup the PAT msr (nested paging only) */ 353 pVMCB->guest.u64GPAT = 0x0007040600070406ULL; 354 } 344 355 return rc; 345 356 } … … 514 525 * @returns VBox status code. 515 526 * @param pVM The VM to operate on. 516 * @param idVCpu VPCPU id.527 * @param pVMCPU The VM CPU to operate on. 517 528 */ 518 VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, RTCPUID idVCpu)529 VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu) 519 530 { 520 531 NOREF(pVM); 521 NOREF( idVCpu);532 NOREF(pVCpu); 522 533 /* Nothing to do here. */ 523 534 return VINF_SUCCESS; … … 531 542 * @returns VBox status code. 532 543 * @param pVM The VM to operate on. 533 * @param idVCpu VPCPU id.544 * @param pVMCPU The VM CPU to operate on. 534 545 * @param pCtx Guest context 535 546 */ 536 VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx)547 VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 537 548 { 538 549 RTGCUINTPTR val; … … 545 556 Assert(pVM->hwaccm.s.svm.fSupported); 546 557 547 pVMCB = (SVM_VMCB *)pV M->hwaccm.s.svm.pVMCB;558 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB; 548 559 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR); 549 560 … … 736 747 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE; 737 748 #else 738 pV M->hwaccm.s.svm.pfnVMRun = SVMVMRun64;749 pVCpu->hwaccm.s.svm.pfnVMRun = SVMVMRun64; 739 750 #endif 740 751 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */ … … 747 758 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME; 748 759 749 pV M->hwaccm.s.svm.pfnVMRun = SVMVMRun;760 pVCpu->hwaccm.s.svm.pfnVMRun = SVMVMRun; 750 761 } 751 762 … … 789 800 * @returns VBox status code. 790 801 * @param pVM The VM to operate on. 791 * @param idVCpu VPCPU id.802 * @param pVMCPU The VM CPU to operate on. 792 803 * @param pCtx Guest context 793 804 */ 794 VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx)805 VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 795 806 { 796 807 int rc = VINF_SUCCESS; … … 807 818 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x); 808 819 809 pVMCB = (SVM_VMCB *)pV M->hwaccm.s.svm.pVMCB;820 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB; 810 821 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR); 811 822 … … 934 945 935 946 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */ 936 rc = SVMR0LoadGuestState(pVM, idVCpu, pCtx);947 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx); 937 948 if (rc != VINF_SUCCESS) 938 949 { … … 1001 1012 pVM->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB; 1002 1013 1003 Assert(sizeof(pV M->hwaccm.s.svm.pVMCBPhys) == 8);1014 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8); 1004 1015 Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */ 1005 1016 | SVM_CTRL2_INTERCEPT_VMMCALL … … 1022 1033 #endif 1023 1034 TMNotifyStartOfExecution(pVM); 1024 pV M->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);1035 pVCpu->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx); 1025 1036 TMNotifyEndOfExecution(pVM); 1026 1037 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x); … … 2048 2059 * @returns VBox status code. 2049 2060 * @param pVM The VM to operate on. 2050 * @param idVCpu VPCPU id.2061 * @param pVCpu The VM CPU to operate on. 2051 2062 * @param pCpu CPU info struct 2052 2063 */ 2053 VMMR0DECL(int) SVMR0Enter(PVM pVM, RTCPUID idVCpu, PHWACCM_CPUINFO pCpu)2064 VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu) 2054 2065 { 2055 2066 Assert(pVM->hwaccm.s.svm.fSupported); … … 2070 2081 * @returns VBox status code. 2071 2082 * @param pVM The VM to operate on. 2072 * @param idVCpu VPCPU id.2083 * @param pVCpu The VM CPU to operate on. 2073 2084 * @param pCtx CPU context 2074 2085 */ 2075 VMMR0DECL(int) SVMR0Leave(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx)2086 VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 2076 2087 { 2077 SVM_VMCB *pVMCB = (SVM_VMCB *)pV M->hwaccm.s.svm.pVMCB;2088 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB; 2078 2089 2079 2090 Assert(pVM->hwaccm.s.svm.fSupported); … … 2203 2214 Assert(pVM->hwaccm.s.svm.fSupported); 2204 2215 2205 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB; 2216 /* @todo SMP */ 2217 pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB; 2206 2218 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR); 2207 2219 trunk/src/VBox/VMM/VMMR0/HWSVMR0.h
r13872 r13879 47 47 * @returns VBox status code. 48 48 * @param pVM The VM to operate on. 49 * @param idVCpu VPCPU id.49 * @param pVCpu VPCPU id. 50 50 * @param pCpu CPU info struct 51 51 */ 52 VMMR0DECL(int) SVMR0Enter(PVM pVM, RTCPUID idVCpu, PHWACCM_CPUINFO pCpu);52 VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu); 53 53 54 54 /** … … 57 57 * @returns VBox status code. 58 58 * @param pVM The VM to operate on. 59 * @param idVCpu VPCPU id.59 * @param pVCpu VPCPU id. 60 60 * @param pCtx CPU context 61 61 */ 62 VMMR0DECL(int) SVMR0Leave(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx);62 VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 63 63 64 64 /** … … 113 113 * @returns VBox status code. 114 114 * @param pVM The VM to operate on. 115 * @param idVCpu VPCPU id.115 * @param pVCpu VPCPU id. 116 116 * @param pCtx Guest context 117 117 */ 118 VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx);118 VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 119 119 120 120 … … 124 124 * @returns VBox status code. 125 125 * @param pVM The VM to operate on. 126 * @param idVCpu VPCPU id.126 * @param pVCpu VPCPU id. 127 127 */ 128 VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, RTCPUID idVCpu);128 VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu); 129 129 130 130 /** … … 133 133 * @returns VBox status code. 134 134 * @param pVM The VM to operate on. 135 * @param idVCpu VPCPU id.135 * @param pVCpu VPCPU id. 136 136 * @param pCtx Guest context 137 137 */ 138 VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, RTCPUID idVCpu, PCPUMCTX pCtx);138 VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 139 139 140 140 trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r13872 r13879 152 152 SUPR0Printf("VMXR0InitVM %x\n", pVM); 153 153 #endif 154 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ; 154 155 155 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ; 156 157 158 /* Allocate one page for the VM control structure (VMCS). */159 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);160 AssertRC(rc);161 if (RT_FAILURE(rc))162 return rc;163 164 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);165 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);166 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);167 156 168 157 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) … … 198 187 } 199 188 189 /* Allocate VMCBs for all guest CPUs. */ 190 for (unsigned i=0;i<pVM->cCPUs;i++) 191 { 192 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ; 193 194 /* Allocate one page for the VM control structure (VMCS). */ 195 rc = RTR0MemObjAllocCont(&pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */); 196 AssertRC(rc); 197 if (RT_FAILURE(rc)) 198 return rc; 199 200 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS); 201 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, 0); 202 ASMMemZero32(pVM->aCpus[i].hwaccm.s.vmx.pVMCS, PAGE_SIZE); 203 204 pVM->aCpus[i].hwaccm.s.vmx.cr0_mask = 0; 205 pVM->aCpus[i].hwaccm.s.vmx.cr4_mask = 0; 206 207 #ifdef LOG_ENABLED 208 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->aCpus[i].hwaccm.s.vmx.pVMCS, (uint32_t)pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys); 209 #endif 210 } 211 200 212 /* Current guest paging mode. */ 201 213 pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL; 202 214 203 #ifdef LOG_ENABLED204 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);205 #endif206 215 return VINF_SUCCESS; 207 216 } … … 215 224 VMMR0DECL(int) VMXR0TermVM(PVM pVM) 216 225 { 217 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ) 218 { 219 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false); 220 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ; 221 pVM->hwaccm.s.vmx.pVMCS = 0; 222 pVM->hwaccm.s.vmx.pVMCSPhys = 0; 226 for (unsigned i=0;i<pVM->cCPUs;i++) 227 { 228 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ) 229 { 230 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false); 231 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ; 232 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0; 233 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0; 234 } 223 235 } 224 236 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ) … … 251 263 252 264 AssertReturn(pVM, VERR_INVALID_PARAMETER); 253 Assert(pVM->hwaccm.s.vmx.pVMCS); 254 255 /* Set revision dword at the beginning of the VMCS structure. */ 256 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info); 257 258

