Changeset 13839
- Timestamp:
- 11/05/08 04:27:47 (2 months ago)
- Files:
-
- trunk/src/VBox/Additions/common/VBoxGuestLib/SysHlp.cpp (modified) (3 diffs)
- trunk/src/VBox/Disassembler/DisasmReg.cpp (modified) (1 diff)
- trunk/src/VBox/HostDrivers/Support/SUPDrv.c (modified) (1 diff)
- trunk/src/VBox/HostDrivers/Support/testcase/tstPin.cpp (modified) (1 diff)
- trunk/src/VBox/HostServices/SharedOpenGL/vboxgl.cpp (modified) (1 diff)
- trunk/src/VBox/Runtime/r0drv/darwin/memobj-r0drv-darwin.cpp (modified) (1 diff)
- trunk/src/VBox/Runtime/r0drv/os2/memobj-r0drv-os2.cpp (modified) (1 diff)
- trunk/src/VBox/Runtime/r0drv/solaris/memobj-r0drv-solaris.c (modified) (2 diffs)
- trunk/src/VBox/Runtime/r0drv/solaris/vbi/memobj-r0drv-solaris.c (modified) (1 diff)
- trunk/src/VBox/Runtime/testcase/tstLog.cpp (modified) (2 diffs)
- trunk/src/recompiler/cpu-all.h (modified) (3 diffs)
- trunk/src/recompiler/cpu-exec.c (modified) (11 diffs)
- trunk/src/recompiler/target-i386/helper.c (modified) (6 diffs)
- trunk/src/recompiler/target-i386/translate.c (modified) (1 diff)
- trunk/src/recompiler_new/cpu-all.h (modified) (4 diffs)
- trunk/src/recompiler_new/cpu-exec.c (modified) (6 diffs)
- trunk/src/recompiler_new/target-i386/translate.c (modified) (67 diffs)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
trunk/src/VBox/Additions/common/VBoxGuestLib/SysHlp.cpp
r11922 r13839 42 42 { 43 43 rc = VERR_NOT_SUPPORTED; 44 AssertMsgFailed(("IoAllocateMdl % VGv%x failed!!\n", pv, u32Size));44 AssertMsgFailed(("IoAllocateMdl %p %x failed!!\n", pv, u32Size)); 45 45 } 46 46 else … … 58 58 IoFreeMdl (pMdl); 59 59 rc = VERR_INVALID_PARAMETER; 60 AssertMsgFailed(("MmProbeAndLockPages % VGv%x failed!!\n", pv, u32Size));60 AssertMsgFailed(("MmProbeAndLockPages %p %x failed!!\n", pv, u32Size)); 61 61 } 62 62 } … … 280 280 281 281 irp->AssociatedIrp.SystemBuffer = pvData; /* Output buffer. */ 282 irp->MdlAddress = NULL; 282 irp->MdlAddress = NULL; 283 283 284 284 /* A completion routine is required to signal the Event. */ trunk/src/VBox/Disassembler/DisasmReg.cpp
r13836 r13839 721 721 pParamVal->size = sizeof(uint16_t); 722 722 pParamVal->val.val16 = (uint16_t)pParam->parval; 723 AssertMsg(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=% VGv\n", pParamVal->size, pParam->size, pCtx->eip) );723 AssertMsg(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->size, pCtx->eip) ); 724 724 } 725 725 else trunk/src/VBox/HostDrivers/Support/SUPDrv.c
r13836 r13839 2154 2154 { 2155 2155 paPages[iPage] = RTR0MemObjGetPagePhysAddr(Mem.MemObj, iPage); 2156 AssertMsg(!(paPages[iPage] & (PAGE_SIZE - 1)), ("iPage=%d Phys=% VHp\n", paPages[iPage]));2156 AssertMsg(!(paPages[iPage] & (PAGE_SIZE - 1)), ("iPage=%d Phys=%RHp\n", paPages[iPage])); 2157 2157 } 2158 2158 *ppvR0 = RTR0MemObjAddress(Mem.MemObj); trunk/src/VBox/HostDrivers/Support/testcase/tstPin.cpp
r11822 r13839 96 96 if (aPinnings[i].aPages[j].Phys >= _4G) 97 97 { 98 RTPrintf("%2d: vrt=%p phys=% VHp\n", j, (char *)aPinnings[i].pvAligned + (j << PAGE_SHIFT), aPinnings[i].aPages[j].Phys);98 RTPrintf("%2d: vrt=%p phys=%RHp\n", j, (char *)aPinnings[i].pvAligned + (j << PAGE_SHIFT), aPinnings[i].aPages[j].Phys); 99 99 c4GPluss++; 100 100 } trunk/src/VBox/HostServices/SharedOpenGL/vboxgl.cpp
r8155 r13839 121 121 122 122 #ifdef DEBUG 123 Log(("Flush: last return value=% VX64\n", *pLastRetVal));123 Log(("Flush: last return value=%RX64\n", *pLastRetVal)); 124 124 switch(*pLastError) 125 125 { trunk/src/VBox/Runtime/r0drv/darwin/memobj-r0drv-darwin.cpp
r9063 r13839 695 695 AssertMsgReturn(Addr, ("iPage=%u\n", iPage), NIL_RTHCPHYS); 696 696 PhysAddr = Addr; 697 AssertMsgReturn(PhysAddr == Addr, ("PhysAddr=% VHp Addr=%RX64\n", PhysAddr, (uint64_t)Addr), NIL_RTHCPHYS);697 AssertMsgReturn(PhysAddr == Addr, ("PhysAddr=%RHp Addr=%RX64\n", PhysAddr, (uint64_t)Addr), NIL_RTHCPHYS); 698 698 } 699 699 trunk/src/VBox/Runtime/r0drv/os2/memobj-r0drv-os2.cpp
r8245 r13839 197 197 int rtR0MemObjNativeAllocPhys(PPRTR0MEMOBJINTERNAL ppMem, size_t cb, RTHCPHYS PhysHighest) 198 198 { 199 AssertMsgReturn(PhysHighest >= 16 *_1M, ("PhysHigest=% VHp\n", PhysHighest), VERR_NOT_IMPLEMENTED);199 AssertMsgReturn(PhysHighest >= 16 *_1M, ("PhysHigest=%RHp\n", PhysHighest), VERR_NOT_IMPLEMENTED); 200 200 201 201 /* create the object. */ trunk/src/VBox/Runtime/r0drv/solaris/memobj-r0drv-solaris.c
r10457 r13839 237 237 int rtR0MemObjNativeAllocPhys(PPRTR0MEMOBJINTERNAL ppMem, size_t cb, RTHCPHYS PhysHighest) 238 238 { 239 AssertMsgReturn(PhysHighest >= 16 *_1M, ("PhysHigest=% VHp\n", PhysHighest), VERR_NOT_IMPLEMENTED);239 AssertMsgReturn(PhysHighest >= 16 *_1M, ("PhysHigest=%RHp\n", PhysHighest), VERR_NOT_IMPLEMENTED); 240 240 241 241 return rtR0MemObjNativeAllocCont(ppMem, cb, false); … … 305 305 pMemSolaris->ppShadowPages = NULL; 306 306 *ppMem = &pMemSolaris->Core; 307 return VINF_SUCCESS; 307 return VINF_SUCCESS; 308 308 } 309 309 trunk/src/VBox/Runtime/r0drv/solaris/vbi/memobj-r0drv-solaris.c
r9176 r13839 175 175 int rtR0MemObjNativeAllocPhys(PPRTR0MEMOBJINTERNAL ppMem, size_t cb, RTHCPHYS PhysHighest) 176 176 { 177 AssertMsgReturn(PhysHighest >= 16 *_1M, ("PhysHigest=% VHp\n", PhysHighest), VERR_NOT_IMPLEMENTED);177 AssertMsgReturn(PhysHighest >= 16 *_1M, ("PhysHigest=%RHp\n", PhysHighest), VERR_NOT_IMPLEMENTED); 178 178 179 179 return rtR0MemObjNativeAllocCont(ppMem, cb, false); trunk/src/VBox/Runtime/testcase/tstLog.cpp
r13837 r13839 47 47 RTLogPrintf("%%Rra %d: %Rra\n", VERR_INVALID_PARAMETER, VERR_INVALID_PARAMETER); 48 48 49 RTLogPrintf("%% Vt: %Vt\n");49 RTLogPrintf("%%Rt: %Rt\n"); 50 50 51 51 static uint8_t au8Hex[256]; 52 52 for (unsigned iHex = 0; iHex < sizeof(au8Hex); iHex++) 53 53 au8Hex[iHex] = (uint8_t)iHex; 54 RTLogPrintf("%% Vhxs : %Vhxs\n", &au8Hex[0]);54 RTLogPrintf("%%Rhxs : %Rhxs\n", &au8Hex[0]); 55 55 RTLogPrintf("%%.32Vhxs: %.32Vhxs\n", &au8Hex[0]); 56 56 57 RTLogPrintf("%% Vhxd :\n%Vhxd\n", &au8Hex[0]);57 RTLogPrintf("%%Rhxd :\n%Rhxd\n", &au8Hex[0]); 58 58 RTLogPrintf("%%.64Vhxd:\n%.64Vhxd\n", &au8Hex[0]); 59 59 RTLogPrintf("%%.*Vhxd:\n%.*Vhxd\n", 64, &au8Hex[0]); … … 64 64 RTLogPrintf("%%*.*Vhxd : \n%*.*Vhxd\n", 7, 32, &au8Hex[0]); 65 65 66 RTLogPrintf("%% VGp: %VGp\n", (RTGCPHYS)0x87654321);67 RTLogPrintf("%% VGv: %VGv\n", (RTGCPTR)0x87654321);68 RTLogPrintf("%% VHp: %VHp\n", (RTGCPHYS)0x87654321);69 RTLogPrintf("%% VHv: %VHv\n", (RTGCPTR)0x87654321);66 RTLogPrintf("%%RGp: %RGp\n", (RTGCPHYS)0x87654321); 67 RTLogPrintf("%%RGv: %RGv\n", (RTGCPTR)0x87654321); 68 RTLogPrintf("%%RHp: %RHp\n", (RTGCPHYS)0x87654321); 69 RTLogPrintf("%%RHv: %RHv\n", (RTGCPTR)0x87654321); 70 70 71 RTLogPrintf("%% VI8 : %VI8\n", (uint8_t)808);72 RTLogPrintf("%% VI16: %VI16\n", (uint16_t)16016);73 RTLogPrintf("%% VI32: %VI32\n", _1G);74 RTLogPrintf("%% VI64: %VI64\n", _1E);71 RTLogPrintf("%%RI8 : %RI8\n", (uint8_t)808); 72 RTLogPrintf("%%RI16: %RI16\n", (uint16_t)16016); 73 RTLogPrintf("%%RI32: %RI32\n", _1G); 74 RTLogPrintf("%%RI64: %RI64\n", _1E); 75 75 76 RTLogPrintf("%% VU8 : %VU8\n", (uint8_t)808);77 RTLogPrintf("%% VU16: %VU16\n", (uint16_t)16016);78 RTLogPrintf("%% VU32: %VU32\n", _2G32);79 RTLogPrintf("%% VU64: %VU64\n", _2E);76 RTLogPrintf("%%RU8 : %RU8\n", (uint8_t)808); 77 RTLogPrintf("%%RU16: %RU16\n", (uint16_t)16016); 78 RTLogPrintf("%%RU32: %RU32\n", _2G32); 79 RTLogPrintf("%%RU64: %RU64\n", _2E); 80 80 81 RTLogPrintf("%% VX8 : %VX8 %#VX8\n", (uint8_t)808, (uint8_t)808);82 RTLogPrintf("%% VX16: %VX16 %#VX16\n", (uint16_t)16016, (uint16_t)16016);83 RTLogPrintf("%% VX32: %VX32 %#VX32\n", _2G32, _2G32);84 RTLogPrintf("%% VX64: %VX64 %#VX64\n", _2E, _2E);81 RTLogPrintf("%%RX8 : %RX8 %#VX8\n", (uint8_t)808, (uint8_t)808); 82 RTLogPrintf("%%RX16: %RX16 %#VX16\n", (uint16_t)16016, (uint16_t)16016); 83 RTLogPrintf("%%RX32: %RX32 %#VX32\n", _2G32, _2G32); 84 RTLogPrintf("%%RX64: %RX64 %#VX64\n", _2E, _2E); 85 85 86 86 RTLogFlush(NULL); trunk/src/recompiler/cpu-all.h
r11982 r13839 1066 1066 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size)) 1067 1067 { 1068 Log(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));1069 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));*/1068 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr)); 1069 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/ 1070 1070 return 0; 1071 1071 } … … 1080 1080 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size)) 1081 1081 { 1082 Log(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));1083 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));*/1082 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr)); 1083 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/ 1084 1084 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */ 1085 1085 } … … 1093 1093 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size)) 1094 1094 { 1095 Log(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));1096 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));*/1095 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr)); 1096 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/ 1097 1097 return; 1098 1098 } trunk/src/recompiler/cpu-exec.c
r13117 r13839 362 362 double or triple faults yet. */ 363 363 RAWEx_ProfileStart(env, STATS_IRQ_HANDLING); 364 Log(("do_interrupt %d %d % VGv\n", env->exception_index, env->exception_is_int, env->exception_next_eip));364 Log(("do_interrupt %d %d %RGv\n", env->exception_index, env->exception_is_int, env->exception_next_eip)); 365 365 do_interrupt(env->exception_index, 366 366 env->exception_is_int, … … 388 388 env->exception_index = EXCP_SINGLE_INSTR; 389 389 if (emulate_single_instr(env) == -1) 390 AssertMsgFailed(("REM: emulate_single_instr failed for EIP=% VGv!!\n", env->eip));390 AssertMsgFailed(("REM: emulate_single_instr failed for EIP=%RGv!!\n", env->eip)); 391 391 392 392 /* When we receive an external interrupt during execution of this single … … 497 497 if(!(env->state & CPU_EMULATE_SINGLE_STEP)) 498 498 { 499 Log(("EMR0: % VGv ESP=%VGv IF=%d TF=%d CPL=%d\n", env->eip, ESP, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3));499 Log(("EMR0: %RGv ESP=%RGv IF=%d TF=%d CPL=%d\n", env->eip, ESP, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3)); 500 500 } 501 501 } … … 507 507 if(env->eflags & VM_MASK) 508 508 { 509 Log(("EMV86: %04X:% VGv IF=%d TF=%d CPL=%d CR0=%RGr\n", env->segs[R_CS].selector, env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, env->cr[0]));509 Log(("EMV86: %04X:%RGv IF=%d TF=%d CPL=%d CR0=%RGr\n", env->segs[R_CS].selector, env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, env->cr[0])); 510 510 } 511 511 else 512 512 { 513 Log(("EMR3: % VGv ESP=%VGv IF=%d TF=%d CPL=%d IOPL=%d CR0=%RGr\n", env->eip, ESP, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, ((env->eflags >> IOPL_SHIFT) & 3), env->cr[0]));513 Log(("EMR3: %RGv ESP=%RGv IF=%d TF=%d CPL=%d IOPL=%d CR0=%RGr\n", env->eip, ESP, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, ((env->eflags >> IOPL_SHIFT) & 3), env->cr[0])); 514 514 } 515 515 } … … 518 518 { 519 519 /* Seriously slows down realmode booting. */ 520 LogFlow(("EMRM: %04X:% VGv SS:ESP=%04X:%VGv IF=%d TF=%d CPL=%d PE=%d PG=%d\n", env->segs[R_CS].selector, env->eip, env->segs[R_SS].selector, ESP, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, env->cr[0] & X86_CR0_PE, env->cr[0] & X86_CR0_PG));520 LogFlow(("EMRM: %04X:%RGv SS:ESP=%04X:%RGv IF=%d TF=%d CPL=%d PE=%d PG=%d\n", env->segs[R_CS].selector, env->eip, env->segs[R_SS].selector, ESP, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, env->cr[0] & X86_CR0_PE, env->cr[0] & X86_CR0_PG)); 521 521 } 522 522 #endif /* !DEBUG_bird */ … … 542 542 if(emulate_single_instr(env) == -1) 543 543 { 544 Log(("emulate_single_instr failed for EIP=% VGv!!\n", env->eip));544 Log(("emulate_single_instr failed for EIP=%RGv!!\n", env->eip)); 545 545 } 546 546 } … … 802 802 env->exception_index = EXCP_SINGLE_INSTR; 803 803 if (emulate_single_instr(env) == -1) 804 AssertMsgFailed(("REM: emulate_single_instr failed for EIP=% VGv!!\n", env->eip));804 AssertMsgFailed(("REM: emulate_single_instr failed for EIP=%RGv!!\n", env->eip)); 805 805 806 806 /* When we receive an external interrupt during execution of this single … … 1201 1201 if(!(env->state & CPU_EMULATE_SINGLE_STEP)) 1202 1202 { 1203 Log(("EMR0: % VGv IF=%d TF=%d CPL=%d\n", env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3));1203 Log(("EMR0: %RGv IF=%d TF=%d CPL=%d\n", env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3)); 1204 1204 } 1205 1205 } … … 1211 1211 if(env->eflags & VM_MASK) 1212 1212 { 1213 Log(("EMV86: % VGv IF=%d TF=%d CPL=%d flags=%08X CR0=%RGr\n", env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, flags, env->cr[0]));1213 Log(("EMV86: %RGv IF=%d TF=%d CPL=%d flags=%08X CR0=%RGr\n", env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, flags, env->cr[0])); 1214 1214 } 1215 1215 else 1216 1216 { 1217 Log(("EMR3: % VGv IF=%d TF=%d CPL=%d IOPL=%d flags=%08X CR0=%RGr\n", env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, ((env->eflags >> IOPL_SHIFT) & 3), flags, env->cr[0]));1217 Log(("EMR3: %RGv IF=%d TF=%d CPL=%d IOPL=%d flags=%08X CR0=%RGr\n", env->eip, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, ((env->eflags >> IOPL_SHIFT) & 3), flags, env->cr[0])); 1218 1218 } 1219 1219 } … … 1240 1240 if(emulate_single_instr(env) == -1) 1241 1241 { 1242 printf("emulate_single_instr failed for EIP=% VGv!!\n", env->eip);1242 printf("emulate_single_instr failed for EIP=%RGv!!\n", env->eip); 1243 1243 } 1244 1244 } … … 1422 1422 if (ret == 1) { 1423 1423 #if 0 1424 printf("PF exception: EIP=0x% VGv CR2=0x%VGv error=0x%x\n",1424 printf("PF exception: EIP=0x%RGv CR2=0x%RGv error=0x%x\n", 1425 1425 env->eip, env->cr[2], env->error_code); 1426 1426 #endif trunk/src/recompiler/target-i386/helper.c
r13449 r13839 1410 1410 { 1411 1411 #if defined(VBOX) && defined(DEBUG) 1412 NOT_DMIK(Log2(("raise_interrupt: %x %x %x % VGv\n", intno, is_int, error_code, env->eip + next_eip_addend)));1412 NOT_DMIK(Log2(("raise_interrupt: %x %x %x %RGv\n", intno, is_int, error_code, env->eip + next_eip_addend))); 1413 1413 #endif 1414 1414 env->exception_index = intno; … … 1978 1978 target_ulong ptr; 1979 1979 #ifdef VBOX 1980 Log(("helper_lldt_T0: old ldtr=%RTsel {.base=% VGv, .limit=%VGv} new=%RTsel\n",1980 Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%RGv, .limit=%RGv} new=%RTsel\n", 1981 1981 (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff))); 1982 1982 #endif … … 2021 2021 env->ldt.selector = selector; 2022 2022 #ifdef VBOX 2023 Log(("helper_lldt_T0: new ldtr=%RTsel {.base=% VGv, .limit=%VGv}\n",2023 Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%RGv, .limit=%RGv}\n", 2024 2024 (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit)); 2025 2025 #endif … … 2035 2035 2036 2036 #ifdef VBOX 2037 Log(("helper_ltr_T0: old tr=%RTsel {.base=% VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",2037 Log(("helper_ltr_T0: old tr=%RTsel {.base=%RGv, .limit=%RGv, .flags=%RX32} new=%RTsel\n", 2038 2038 (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit, 2039 2039 env->tr.flags, (RTSEL)(T0 & 0xffff))); … … 2084 2084 env->tr.selector = selector; 2085 2085 #ifdef VBOX 2086 Log(("helper_ltr_T0: new tr=%RTsel {.base=% VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",2086 Log(("helper_ltr_T0: new tr=%RTsel {.base=%RGv, .limit=%RGv, .flags=%RX32} new=%RTsel\n", 2087 2087 (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit, 2088 2088 env->tr.flags, (RTSEL)(T0 & 0xffff))); … … 4651 4651 if (env->hflags & HF_INHIBIT_IRQ_MASK) 4652 4652 { 4653 Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK) at % VGv\n", env->eip));4653 Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK) at %RGv\n", env->eip)); 4654 4654 env->hflags &= ~HF_INHIBIT_IRQ_MASK; 4655 4655 emulate_single_instr(env); trunk/src/recompiler/target-i386/translate.c
r12421 r13839 3353 3353 /* illegal sequence. The s->pc is past the lock prefix and that 3354 3354 is sufficient for the TB, I think. */ 3355 Log(("illegal lock sequence % VGv (b=%#x)\n", pc_start, b));3355 Log(("illegal lock sequence %RGv (b=%#x)\n", pc_start, b)); 3356 3356 return true; 3357 3357 } trunk/src/recompiler_new/cpu-all.h
r13559 r13839 1192 1192 1193 1193 /* MMIO pages are identified by a combination of an IO device index and 1194 3 flags. The ROMD code stores the page ram offset in iotlb entry, 1194 3 flags. The ROMD code stores the page ram offset in iotlb entry, 1195 1195 so only a limited number of ids are avaiable. */ 1196 1196 … … 1291 1291 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size)) 1292 1292 { 1293 Log(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));1294 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));*/1293 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr)); 1294 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/ 1295 1295 return 0; 1296 1296 } … … 1311 1311 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size)) 1312 1312 { 1313 Log(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));1314 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));*/1313 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr)); 1314 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/ 1315 1315 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */ 1316 1316 } … … 1329 1329 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size)) 1330 1330 { 1331 Log(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));1332 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: % VGp\n", (RTGCPHYS)addr));*/1331 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr)); 1332 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/ 1333 1333 return; 1334 1334 } trunk/src/recompiler_new/cpu-exec.c
r13726 r13839 326 326 double or triple faults yet. */ 327 327 RAWEx_ProfileStart(env, STATS_IRQ_HANDLING); 328 Log(("do_interrupt %d %d % VGv\n", env->exception_index, env->exception_is_int, env->exception_next_eip));328 Log(("do_interrupt %d %d %RGv\n", env->exception_index, env->exception_is_int, env->exception_next_eip)); 329 329 do_interrupt(env->exception_index, 330 330 env->exception_is_int, … … 360 360 env->exception_index = EXCP_SINGLE_INSTR; 361 361 if (emulate_single_instr(env) == -1) 362 AssertMsgFailed(("REM: emulate_single_instr failed for EIP=% VGv!!\n", env->eip));362 AssertMsgFailed(("REM: emulate_single_instr failed for EIP=%RGv!!\n", env->eip)); 363 363 364 364 /* When we receive an external interrupt during execution of this single … … 504 504 } 505 505 } 506 506 507 507 /* reset soft MMU for next block (it can currently 508 508 only be set by a memory fault) */ … … 695 695 next_tb = 0; 696 696 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 697 (((env->hflags2 & HF2_VINTR_MASK) && 697 (((env->hflags2 & HF2_VINTR_MASK) && 698 698 (env->hflags2 & HF2_HIF_MASK)) || 699 (!(env->hflags2 & HF2_VINTR_MASK) && 700 (env->eflags & IF_MASK && 699 (!(env->hflags2 & HF2_VINTR_MASK) && 700 (env->eflags & IF_MASK && 701 701 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 702 702 int intno; … … 713 713 #if !defined(CONFIG_USER_ONLY) 714 714 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && 715 (env->eflags & IF_MASK) && 715 (env->eflags & IF_MASK) && 716 716 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 717 717 int intno; … … 1096 1096 if (ret == 1) { 1097 1097 #if 0 1098 printf("PF exception: EIP=0x% VGv CR2=0x%VGv error=0x%x\n",1098 printf("PF exception: EIP=0x%RGv CR2=0x%RGv error=0x%x\n", 1099 1099 env->eip, env->cr[2], env->error_code); 1100 1100 #endif trunk/src/recompiler_new/target-i386/translate.c
r13672 r13839 519 519 } 520 520 #endif 521 521 522 522 static void gen_add_A0_im(DisasContext *s, int val) 523 523 { … … 624 624 { 625 625 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); 626 if (shift != 0) 626 if (shift != 0) 627 627 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); 628 628 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); … … 690 690 { 691 691 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); 692 if (shift != 0) 692 if (shift != 0) 693 693 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); 694 694 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); … … 826 826 int skip_label; 827 827 TCGv t0; 828 828 829 829 skip_label = gen_new_label(); 830 830 /* t0 = tcg_temp_local_new(TCG_TYPE_TL); */ 831 t0 = cpu_tmp0; 831 t0 = cpu_tmp0; 832 832 833 833 tcg_gen_ld32u_tl(t0, cpu_env, offsetof(CPUState, interrupt_request)); 834 834 /* Keep in sync with helper_check_external_event() */ 835 tcg_gen_andi_tl(t0, t0, 835 tcg_gen_andi_tl(t0, t0, 836 836 CPU_INTERRUPT_EXTERNAL_EXIT 837 837 | CPU_INTERRUPT_EXTERNAL_TIMER … … 923 923 924 924 #ifndef VBOX 925 static inline void gen_op_movl_T0_Dshift(int ot) 925 static inline void gen_op_movl_T0_Dshift(int ot) 926 926 #else /* VBOX */ 927 DECLINLINE(void) gen_op_movl_T0_Dshift(int ot) 927 DECLINLINE(void) gen_op_movl_T0_Dshift(int ot) 928 928 #endif /* VBOX */ 929 929 { … … 1109 1109 #if TCG_TARGET_REG_BITS == 32 1110 1110 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); 1111 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1111 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1112 1112 (long)cc_table + offsetof(CCTable, compute_c)); 1113 1113 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); 1114 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1114 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1115 1115 1, &cpu_tmp2_i32, 0, NULL); 1116 1116 #else 1117 1117 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); 1118 1118 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); 1119 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1119 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1120 1120 (long)cc_table + offsetof(CCTable, compute_c)); 1121 1121 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); 1122 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1122 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1123 1123 1, &cpu_tmp2_i32, 0, NULL); 1124 1124 #endif … … 1131 1131 #if TCG_TARGET_REG_BITS == 32 1132 1132 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); 1133 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1133 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1134 1134 (long)cc_table + offsetof(CCTable, compute_all)); 1135 1135 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); 1136 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1136 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1137 1137 1, &cpu_tmp2_i32, 0, NULL); 1138 1138 #else 1139 1139 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); 1140 1140 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); 1141 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1141 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1142 1142 (long)cc_table + offsetof(CCTable, compute_all)); 1143 1143 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); 1144 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1144 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1145 1145 1, &cpu_tmp2_i32, 0, NULL); 1146 1146 #endif … … 1277 1277 case CC_OP_SUBL: 1278 1278 case CC_OP_SUBQ: 1279 1279 1280 1280 size = cc_op - CC_OP_SUBB; 1281 1281 switch(jcc_op) { … … 1308 1308 case 0: 1309 1309 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80); 1310 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1310 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1311 1311 0, l1); 1312 1312 break; 1313 1313 case 1: 1314 1314 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000); 1315 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1315 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1316 1316 0, l1); 1317 1317 break; … … 1319 1319 case 2: 1320 1320 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000); 1321 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1321 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1322 1322 0, l1); 1323 1323 break; 1324 1324 #endif 1325 1325 default: 1326 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, 1326 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, 1327 1327 0, l1); 1328 1328 break; 1329 1329 } 1330 1330 break; 1331 1331 1332 1332 case JCC_B: 1333 1333 cond = inv ? TCG_COND_GEU : TCG_COND_LTU; … … 1361 1361 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); 1362 1362 break; 1363 1363 1364 1364 case JCC_L: 1365 1365 cond = inv ? TCG_COND_GE : TCG_COND_LT; … … 1393 1393 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); 1394 1394 break; 1395 1395 1396 1396 default: 1397 1397 goto slow_jcc; 1398 1398 } 1399 1399 break; 1400 1400 1401 1401 /* some jumps are easy to compute */ 1402 1402 case CC_OP_ADDB: … … 1404 1404 case CC_OP_ADDL: 1405 1405 case CC_OP_ADDQ: 1406 1406 1407 1407 case CC_OP_ADCB: 1408 1408 case CC_OP_ADCW: 1409 1409 case CC_OP_ADCL: 1410 1410 case CC_OP_ADCQ: 1411 1411 1412 1412 case CC_OP_SBBB: 1413 1413 case CC_OP_SBBW: 1414 1414 case CC_OP_SBBL: 1415 1415 case CC_OP_SBBQ: 1416 1416 1417 1417 case CC_OP_LOGICB: 1418 1418 case CC_OP_LOGICW: 1419 1419 case CC_OP_LOGICL: 1420 1420 case CC_OP_LOGICQ: 1421 1421 1422 1422 case CC_OP_INCB: 1423 1423 case CC_OP_INCW: 1424 1424 case CC_OP_INCL: 1425 1425 case CC_OP_INCQ: 1426 1426 1427 1427 case CC_OP_DECB: 1428 1428 case CC_OP_DECW: 1429 1429 case CC_OP_DECL: 1430 1430 case CC_OP_DECQ: 1431 1431 1432 1432 case CC_OP_SHLB: 1433 1433 case CC_OP_SHLW: 1434 1434 case CC_OP_SHLL: 1435 1435 case CC_OP_SHLQ: 1436 1436 1437 1437 case CC_OP_SARB: 1438 1438 case CC_OP_SARW: … … 1453 1453 slow_jcc: 1454 1454 gen_setcc_slow_T0(s, jcc_op); 1455 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, 1455 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, 1456 1456 cpu_T[0], 0, l1); 1457 1457 break; … … 1802 1802 } 1803 1803 1804 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, 1804 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, 1805 1805 int is_right, int is_arith) 1806 1806 { … … 1844 1844 else 1845 1845 gen_op_mov_reg_T0(ot, op1); 1846 1846 1847 1847 /* update eflags if non zero shift */ 1848 1848 if (s->cc_op != CC_OP_DYNAMIC) … … 1865 1865 else 1866 1866 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); 1867 1867 1868 1868 gen_set_label(shift_label); 1869 1869 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ … … 1877 1877 { 1878 1878 int mask; 1879 1879 1880 1880 if (ot == OT_QUAD) 1881 1881 mask = 0x3f; … … 1912 1912 else 1913 1913 gen_op_mov_reg_T0(ot, op1); 1914 1914 1915 1915 /* update eflags if non zero shift */ 1916 1916 if (op2 != 0) { … … 1937 1937 1938 1938 /* XXX: add faster immediate case */ 1939 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, 1939 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, 1940 1940 int is_right) 1941 1941 { … … 1971 1971 label1 = gen_new_label(); 1972 1972 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); 1973 1973 1974 1974 if (ot <= OT_WORD) 1975 1975 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); 1976 1976 else 1977 1977 tcg_gen_mov_tl(cpu_tmp0, t1); 1978 1978 1979 1979 gen_extu(ot, t0); 1980 1980 tcg_gen_mov_tl(t2, t0); … … 2001 2001 gen_op_mov_reg_v(ot, op1, t0); 2002 2002 } 2003 2003 2004 2004 /* update eflags */ 2005 2005 if (s->cc_op != CC_OP_DYNAMIC) … … 2020 2020 tcg_gen_andi_tl(t0, t0, CC_C); 2021 2021 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); 2022 2022 2023 2023 tcg_gen_discard_tl(cpu_cc_dst); 2024 2024 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); 2025 2025 2026 2026 gen_set_label(label2); 2027 2027 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ … … 2045 2045 2046 2046 /* XXX: add faster immediate = 1 case */ 2047 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, 2047 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, 2048 2048 int is_right) 2049 2049 { … … 2058 2058 else 2059 2059 gen_op_mov_TN_reg(ot, 0, op1); 2060 2060 2061 2061 tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)], 2062 2062 cpu_T[0], cpu_T[0], cpu_T[1]); … … 2074 2074 tcg_gen_discard_tl(cpu_cc_dst); 2075 2075 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); 2076 2076 2077 2077 gen_set_label(label1); 2078 2078 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ … … 2080 2080 2081 2081 /* XXX: add faster immediate case */ 2082 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, 2082 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, 2083 2083 int is_right) 2084 2084 { … … 2114 2114 label1 = gen_new_label(); 2115 2115 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); 2116 2116 2117 2117 tcg_gen_addi_tl(cpu_tmp5, t2, -1); 2118 2118 if (ot == OT_WORD) { … … 2125 2125 2126 2126 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); 2127 2127 2128 2128 /* only needed if count > 16, but a test would complicate */ 2129 2129 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2); … … 2139 2139 tcg_gen_or_tl(t1, t1, t0); 2140 2140 tcg_gen_ext32u_tl(t1, t1); 2141 2141 2142 2142 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); 2143 2143 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5); … … 2162 2162 tcg_gen_shl_tl(t1, t1, cpu_tmp5); 2163 2163 tcg_gen_or_tl(t0, t0, t1); 2164 2164 2165 2165 } else { 2166 2166 if (ot == OT_LONG) … … 2168 2168 2169 2169 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); 2170 2170 2171 2171 tcg_gen_shl_tl(t0, t0, t2); 2172 2172 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2); … …

