Changeset 13382
- Timestamp:
- 10/19/08 22:45:30 (3 months ago)
- Files:
-
- trunk/src/recompiler_new/VBoxRecompiler.c (modified) (62 diffs)
- trunk/src/recompiler_new/bswap.h (modified) (6 diffs)
- trunk/src/recompiler_new/cpu-all.h (modified) (29 diffs)
- trunk/src/recompiler_new/cpu-exec.c (modified) (1 diff)
- trunk/src/recompiler_new/exec-all.h (modified) (9 diffs)
- trunk/src/recompiler_new/exec.c (modified) (22 diffs)
- trunk/src/recompiler_new/hostregs_helper.h (modified) (1 diff)
- trunk/src/recompiler_new/osdep.h (modified) (3 diffs)
- trunk/src/recompiler_new/softmmu_header.h (modified) (11 diffs)
- trunk/src/recompiler_new/softmmu_template.h (modified) (2 diffs)
- trunk/src/recompiler_new/target-i386/cpu.h (modified) (6 diffs)
- trunk/src/recompiler_new/target-i386/exec.h (modified) (19 diffs)
- trunk/src/recompiler_new/translate-all.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
trunk/src/recompiler_new/VBoxRecompiler.c
r13358 r13382 245 245 uint32_t u32Dummy; 246 246 unsigned i; 247 int rc; 247 248 248 249 /* … … 276 277 277 278 /* ctx. */ 278 intrc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx);279 rc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx); 279 280 if (VBOX_FAILURE(rc)) 280 281 { … … 451 452 static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM) 452 453 { 453 LogFlow(("remR3Save:\n"));454 455 454 /* 456 455 * Save the required CPU Env bits. … … 458 457 */ 459 458 PREM pRem = &pVM->rem.s; 459 LogFlow(("remR3Save:\n")); 460 460 Assert(!pRem->fInREM); 461 461 SSMR3PutU32(pSSM, pRem->Env.hflags); … … 482 482 uint32_t u32Dummy; 483 483 uint32_t fRawRing0 = false; 484 uint32_t u32Sep; 485 int rc; 486 PREM pRem; 484 487 LogFlow(("remR3Load:\n")); 485 488 … … 509 512 * (Not much because we're never in REM when doing the save.) 510 513 */ 511 PREMpRem = &pVM->rem.s;514 pRem = &pVM->rem.s; 512 515 Assert(!pRem->fInREM); 513 516 SSMR3GetU32(pSSM, &pRem->Env.hflags); … … 519 522 } 520 523 521 uint32_t u32Sep; 522 int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */ 524 rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */ 523 525 if (VBOX_FAILURE(rc)) 524 526 return rc; … … 536 538 if (u32Version == REM_SAVED_STATE_VERSION_VER1_6) 537 539 { 540 unsigned i; 541 538 542 /* 539 543 * Load the REM stuff. … … 547 551 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED; 548 552 } 549 unsigned i;550 553 for (i = 0; i < pRem->cInvalidatedPages; i++) 551 554 SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]); … … 608 611 REMR3DECL(int) REMR3Step(PVM pVM) 609 612 { 613 int rc, interrupt_request; 614 RTGCPTR GCPtrPC; 615 bool fBp; 616 610 617 /* 611 618 * Lock the REM - we don't wanna have anyone interrupting us … … 613 620 * pending interrupts and suchlike. 614 621 */ 615 int interrupt_request = pVM->rem.s.Env.interrupt_request;622 interrupt_request = pVM->rem.s.Env.interrupt_request; 616 623 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_TIMER))); 617 624 pVM->rem.s.Env.interrupt_request = 0; … … 621 628 * If we're standing at a breakpoint, that have to be disabled before we start stepping. 622 629 */ 623 RTGCPTRGCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;624 boolfBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);630 GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base; 631 fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC); 625 632 626 633 /* … … 629 636 * just flip it on and off to make sure it moves 630 637 */ 631 intrc = cpu_exec(&pVM->rem.s.Env);638 rc = cpu_exec(&pVM->rem.s.Env); 632 639 if (rc == EXCP_DEBUG) 633 640 { … … 728 735 REMR3DECL(int) REMR3EmulateInstruction(PVM pVM) 729 736 { 737 int rc, rc2; 730 738 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM))); 731 739 … … 739 747 * Sync the state and enable single instruction / single stepping. 740 748 */ 741 intrc = REMR3State(pVM, false /* no need to flush the TBs; we always compile. */);749 rc = REMR3State(pVM, false /* no need to flush the TBs; we always compile. */); 742 750 if (VBOX_SUCCESS(rc)) 743 751 { … … 951 959 #endif 952 960 pVM->rem.s.Env.interrupt_request = interrupt_request; 953 intrc2 = REMR3StateBack(pVM);961 rc2 = REMR3StateBack(pVM); 954 962 AssertRC(rc2); 955 963 } … … 975 983 REMR3DECL(int) REMR3Run(PVM pVM) 976 984 { 985 int rc; 977 986 Log2(("REMR3Run: (cs:eip=%04x:%VGv)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip)); 978 987 Assert(pVM->rem.s.fInREM); 979 988 980 989 TMNotifyStartOfExecution(pVM); 981 intrc = cpu_exec(&pVM->rem.s.Env);990 rc = cpu_exec(&pVM->rem.s.Env); 982 991 TMNotifyEndOfExecution(pVM); 983 992 switch (rc) … … 1104 1113 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */ 1105 1114 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */ 1115 uint32_t u32CR0; 1106 1116 1107 1117 /* Update counter. */ … … 1110 1120 if (HWACCMIsEnabled(env->pVM)) 1111 1121 { 1122 CPUMCTX Ctx; 1123 1112 1124 env->state |= CPU_RAW_HWACC; 1113 1125 … … 1115 1127 * Create partial context for HWACCMR3CanExecuteGuest 1116 1128 */ 1117 CPUMCTX Ctx;1118 1129 Ctx.cr0 = env->cr[0]; 1119 1130 Ctx.cr3 = env->cr[3]; … … 1215 1226 } 1216 1227 1217 u int32_t u32CR0 = env->cr[0];1228 u32CR0 = env->cr[0]; 1218 1229 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE)) 1219 1230 { … … 1344 1355 { 1345 1356 PVM pVM = env->pVM; 1357 PCPUMCTX pCtx; 1358 int rc; 1346 1359 1347 1360 /* … … 1359 1372 * Update the control registers before calling PGMFlushPage. 1360 1373 */ 1361 PCPUMCTXpCtx = (PCPUMCTX)pVM->rem.s.pCtx;1374 pCtx = (PCPUMCTX)pVM->rem.s.pCtx; 1362 1375 pCtx->cr0 = env->cr[0]; 1363 1376 pCtx->cr3 = env->cr[3]; … … 1367 1380 * Let PGM do the rest. 1368 1381 */ 1369 intrc = PGMInvalidatePage(pVM, GCPtr);1382 rc = PGMInvalidatePage(pVM, GCPtr); 1370 1383 if (VBOX_FAILURE(rc)) 1371 1384 { … … 1426 1439 { 1427 1440 PVM pVM = env->pVM; 1441 PCPUMCTX pCtx; 1428 1442 1429 1443 /* … … 1445 1459 * Update the control registers before calling PGMR3FlushTLB. 1446 1460 */ 1447 PCPUMCTXpCtx = (PCPUMCTX)pVM->rem.s.pCtx;1461 pCtx = (PCPUMCTX)pVM->rem.s.pCtx; 1448 1462 pCtx->cr0 = env->cr[0]; 1449 1463 pCtx->cr3 = env->cr[3]; … … 1466 1480 int rc; 1467 1481 PVM pVM = env->pVM; 1482 PCPUMCTX pCtx; 1468 1483 1469 1484 /* … … 1479 1494 * as it may need to map whatever cr3 is pointing to. 1480 1495 */ 1481 PCPUMCTXpCtx = (PCPUMCTX)pVM->rem.s.pCtx;1496 pCtx = (PCPUMCTX)pVM->rem.s.pCtx; 1482 1497 pCtx->cr0 = env->cr[0]; 1483 1498 pCtx->cr3 = env->cr[3]; … … 1628 1643 REMR3DECL(int) REMR3State(PVM pVM, bool fFlushTBs) 1629 1644 { 1645 register const CPUMCTX *pCtx; 1646 register unsigned fFlags; 1647 bool fHiddenSelRegsValid; 1648 unsigned i; 1649 TRPMEVENT enmType; 1650 uint8_t u8TrapNo; 1651 int rc; 1652 1630 1653 Log2(("REMR3State:\n")); 1631 1654 STAM_PROFILE_START(&pVM->rem.s.StatsState, a); 1632 register const CPUMCTX *pCtx = pVM->rem.s.pCtx; 1633 register unsigned fFlags; 1634 bool fHiddenSelRegsValid = CPUMAreHiddenSelRegsValid(pVM); 1635 unsigned i; 1655 1656 pCtx = pVM->rem.s.pCtx; 1657 fHiddenSelRegsValid = CPUMAreHiddenSelRegsValid(pVM); 1636 1658 1637 1659 Assert(!pVM->rem.s.fInREM); … … 1716 1738 if (pVM->rem.s.cInvalidatedPages) 1717 1739 { 1740 RTUINT i; 1741 1718 1742 pVM->rem.s.fIgnoreInvlPg = true; 1719 RTUINT i;1720 1743 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++) 1721 1744 { … … 1976 1999 */ 1977 2000 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */ 1978 TRPMEVENT enmType; 1979 uint8_t u8TrapNo; 1980 int rc = TRPMQueryTrap(pVM, &u8TrapNo, &enmType); 2001 rc = TRPMQueryTrap(pVM, &u8TrapNo, &enmType); 1981 2002 if (VBOX_SUCCESS(rc)) 1982 2003 { … … 2076 2097 REMR3DECL(int) REMR3StateBack(PVM pVM) 2077 2098 { 2099 register PCPUMCTX pCtx = pVM->rem.s.pCtx; 2100 unsigned i; 2101 2078 2102 Log2(("REMR3StateBack:\n")); 2079 2103 Assert(pVM->rem.s.fInREM); 2080 2104 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a); 2081 register PCPUMCTX pCtx = pVM->rem.s.pCtx; 2082 unsigned i; 2083 2084 /* 2105 /* 2085 2106 * Copy back the registers. 2086 2107 * This is done in the order they are declared in the CPUMCTX structure. … … 2269 2290 && pVM->rem.s.Env.exception_index < 256) 2270 2291 { 2292 int rc; 2293 2271 2294 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int)); 2272 intrc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, (pVM->rem.s.Env.exception_is_int) ? TRPM_SOFTWARE_INT : TRPM_HARDWARE_INT);2295 rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, (pVM->rem.s.Env.exception_is_int) ? TRPM_SOFTWARE_INT : TRPM_HARDWARE_INT); 2273 2296 AssertRC(rc); 2274 2297 switch (pVM->rem.s.Env.exception_index) … … 2301 2324 static void remR3StateUpdate(PVM pVM) 2302 2325 { 2303 Assert(pVM->rem.s.fInREM);2304 2326 register PCPUMCTX pCtx = pVM->rem.s.pCtx; 2305 2327 unsigned i; 2306 2328 2329 Assert(pVM->rem.s.fInREM); 2330 2307 2331 /* 2308 2332 * Copy back the registers. … … 2492 2516 REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable) 2493 2517 { 2518 bool fSaved; 2519 2494 2520 LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable)); 2495 2521 VM_ASSERT_EMT(pVM); 2496 2522 2497 boolfSaved = pVM->rem.s.fIgnoreAll; /* just in case. */2523 fSaved = pVM->rem.s.fIgnoreAll; /* just in case. */ 2498 2524 pVM->rem.s.fIgnoreAll = fSaved || !pVM->rem.s.fInREM; 2499 2525 … … 2512 2538 REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM) 2513 2539 { 2540 RTUINT i; 2541 2514 2542 VM_ASSERT_EMT(pVM); 2515 2543 … … 2526 2554 */ 2527 2555 pVM->rem.s.fIgnoreInvlPg = true; 2528 RTUINT i;2529 2556 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++) 2530 2557 { … … 2545 2572 REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM) 2546 2573 { 2574 /* 2575 * Replay the flushes. 2576 */ 2577 RTUINT i; 2578 const RTUINT c = pVM->rem.s.cHandlerNotifications; 2579 2547 2580 LogFlow(("REMR3ReplayInvalidatedPages:\n")); 2548 2581 VM_ASSERT_EMT(pVM); 2549 2582 2550 /*2551 * Replay the flushes.2552 */2553 RTUINT i;2554 const RTUINT c = pVM->rem.s.cHandlerNotifications;2555 2583 pVM->rem.s.cHandlerNotifications = 0; 2556 2584 for (i = 0; i < c; i++) … … 2745 2773 int rc; 2746 2774 PVM pVM = cpu_single_env->pVM; 2775 const RTGCPHYS GCPhys = physaddr; 2747 2776 2748 2777 LogFlow(("remR3GrowDynRange %VGp\n", physaddr)); 2749 const RTGCPHYS GCPhys = physaddr;2750 2778 rc = PGM3PhysGrowRange(pVM, &GCPhys); 2751 2779 if (VBOX_SUCCESS(rc)) … … 3274 3302 static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32) 3275 3303 { 3304 int rc; 3276 3305 Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32)); 3277 intrc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);3306 rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1); 3278 3307 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc); 3279 3308 } … … 3282 3311 static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32) 3283 3312 { 3313 int rc; 3284 3314 Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32)); 3285 intrc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);3315 rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2); 3286 3316 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc); 3287 3317 } … … 3290 3320 static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32) 3291 3321 { 3322 int rc; 3292 3323 Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32)); 3293 intrc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);3324 rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4); 3294 3325 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc); 3295 3326 } … … 3303 3334 static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys) 3304 3335 { 3336 uint8_t u8; 3305 3337 Log2(("remR3HandlerReadU8: GCPhys=%VGp\n", GCPhys)); 3306 uint8_t u8;3307 3338 PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8)); 3308 3339 return u8; … … 3311 3342 static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys) 3312 3343 { 3344 uint16_t u16; 3313 3345 Log2(("remR3HandlerReadU16: GCPhys=%VGp\n", GCPhys)); 3314 uint16_t u16;3315 3346 PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16)); 3316 3347 return u16; … … 3319 3350 static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys) 3320 3351 { 3352 uint32_t u32; 3321 3353 Log2(("remR3HandlerReadU32: GCPhys=%VGp\n", GCPhys)); 3322 uint32_t u32;3323 3354 PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32)); 3324 3355 return u32; … … 3434 3465 bool remR3DisasBlock(CPUState *env, int f32BitCode, int nrInstructions, char *pszPrefix) 3435 3466 { 3436 int i; 3467 int i, rc; 3468 RTGCPTR GCPtrPC; 3469 uint8_t *pvPC; 3470 RTINTPTR off; 3471 DISCPUSTATE Cpu; 3437 3472 3438 3473 /* … … 3446 3481 * We don't care to much about cross page correctness presently. 3447 3482 */ 3448 RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip; 3449 void *pvPC; 3483 GCPtrPC = env->segs[R_CS].base + env->eip; 3450 3484 if (f32BitCode && (env->cr[0] & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)) 3451 3485 { … … 3453 3487 3454 3488 /* convert eip to physical address. */ 3455 intrc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM,3456 GCPtrPC,3457 env->cr[3],3458 env->cr[4] & (X86_CR4_PSE | X86_CR4_PAE), /** @todo add longmode flag */3459 &pvPC);3489 rc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM, 3490 GCPtrPC, 3491 env->cr[3], 3492 env->cr[4] & (X86_CR4_PSE | X86_CR4_PAE), /** @todo add longmode flag */ 3493 &pvPC); 3460 3494 if (VBOX_FAILURE(rc)) 3461 3495 { … … 3469 3503 { 3470 3504 /* physical address */ 3471 intrc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions * 16, &pvPC);3505 rc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions * 16, &pvPC); 3472 3506 if (VBOX_FAILURE(rc)) 3473 3507 return false; … … 3477 3511 * Disassemble. 3478 3512 */ 3479 RTINTPTR off = env->eip - (RTGCUINTPTR)pvPC; 3480 DISCPUSTATE Cpu; 3513 off = env->eip - (RTGCUINTPTR)pvPC; 3481 3514 Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT; 3482 3515 Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */ … … 3518 3551 { 3519 3552 #ifdef USE_OLD_DUMP_AND_DISASSEMBLY 3520 PVM pVM = env->pVM; 3553 PVM pVM = env->pVM; 3554 RTGCPTR GCPtrPC; 3555 uint8_t *pvPC; 3556 char szOutput[256]; 3557 uint32_t cbOp; 3558 RTINTPTR off; 3559 DISCPUSTATE Cpu; 3560 3521 3561 3522 3562 /* Doesn't work in long mode. */ … … 3543 3583 * We don't care to much about cross page correctness presently. 3544 3584 */ 3545 RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip; 3546 void *pvPC; 3585 GCPtrPC = env->segs[R_CS].base + env->eip; 3547 3586 if ((env->cr[0] & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)) 3548 3587 { … … 3573 3612 * Disassemble. 3574 3613 */ 3575 RTINTPTR off = env->eip - (RTGCUINTPTR)pvPC; 3576 DISCPUSTATE Cpu; 3614 off = env->eip - (RTGCUINTPTR)pvPC; 3577 3615 Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT; 3578 3616 Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */ … … 3580 3618 //Cpu.dwUserData[1] = (uintptr_t)pvPC; 3581 3619 //Cpu.dwUserData[2] = GCPtrPC; 3582 char szOutput[256];3583 uint32_t cbOp;3584 3620 if (RT_FAILURE(DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))) 3585 3621 return false; … … 3691 3727 { 3692 3728 PVM pVM = cpu_single_env->pVM; 3729 RTSEL cs; 3730 RTGCUINTPTR eip; 3693 3731 3694 3732 /* … … 3701 3739 */ 3702 3740 RTLogPrintf("Guest Code: PC=%VGp #VGp (%VGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags); 3703 RTSELcs = cpu_single_env->segs[R_CS].selector;3704 RTGCUINTPTReip = uCode - cpu_single_env->segs[R_CS].base;3741 cs = cpu_single_env->segs[R_CS].selector; 3742 eip = uCode - cpu_single_env->segs[R_CS].base; 3705 3743 for (;;) 3706 3744 { … … 4120 4158 void cpu_outb(CPUState *env, int addr, int val) 4121 4159 { 4160 int rc; 4161 4122 4162 if (addr != 0x80 && addr != 0x70 && addr != 0x61) 4123 4163 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val)); 4124 4164 4125 intrc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);4165 rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1); 4126 4166 if (RT_LIKELY(rc == VINF_SUCCESS)) 4127 4167 return; … … 4152 4192 void cpu_outl(CPUState *env, int addr, int val) 4153 4193 { 4194 int rc; 4154 4195 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val)); 4155 intrc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);4196 rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4); 4156 4197 if (RT_LIKELY(rc == VINF_SUCCESS)) 4157 4198 return; … … 4286 4327 void cpu_abort(CPUState *env, const char *pszFormat, ...) 4287 4328 { 4329 va_list args; 4330 PVM pVM; 4331 4288 4332 /* 4289 4333 * Bitch about it. 4290 4334 */ 4335 #ifndef _MSC_VER 4336 /** @todo: MSVC is right - it's not valid C */ 4291 4337 RTLogFlags(NULL, "nodisabled nobuffered"); 4292 va_list args; 4338 #endif 4293 4339 va_start(args, pszFormat); 4294 4340 RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args); … … 4302 4348 * the EMs failure handling. 4303 4349 */ 4304 PVMpVM = cpu_single_env->pVM;4350 pVM = cpu_single_env->pVM; 4305 4351 if (pVM->rem.s.fInREM) 4306 4352 REMR3StateBack(pVM); … … 4318 4364 static void remAbort(int rc, const char *pszTip) 4319 4365 { 4366 PVM pVM; 4367 4320 4368 /* 4321 4369 * Bitch about it. … … 4327 4375 * Jump back to where we entered the recompiler. 4328 4376 */ 4329 PVMpVM = cpu_single_env->pVM;4377 pVM = cpu_single_env->pVM; 4330 4378 if (pVM->rem.s.fInREM) 4331 4379 REMR3StateBack(pVM); trunk/src/recompiler_new/bswap.h
r2422 r13382 79 79 80 80 #ifndef bswap16 /* BSD endian.h clash */ 81 #ifndef VBOX 81 82 static inline uint16_t bswap16(uint16_t x) 83 #else 84 DECLINLINE(uint16_t) bswap16(uint16_t x) 85 #endif 82 86 { 83 87 return bswap_16(x); … … 86 90 87 91 #ifndef bswap32 /* BSD endian.h clash */ 92 #ifndef VBOX 88 93 static inline uint32_t bswap32(uint32_t x) 94 #else 95 DECLINLINE(uint32_t) bswap32(uint32_t x) 96 #endif 89 97 { 90 98 return bswap_32(x); … … 93 101 94 102 #ifndef bswap64 /* BSD endian.h clash. */ 103 #ifndef VBOX 95 104 static inline uint64_t bswap64(uint64_t x) 105 #else 106 DECLINLINE(uint64_t) bswap64(uint64_t x) 107 #endif 96 108 { 97 109 return bswap_64(x); … … 99 111 #endif 100 112 113 #ifndef VBOX 101 114 static inline void bswap16s(uint16_t *s) 115 #else 116 DECLINLINE(void) bswap16s(uint16_t *s) 117 #endif 102 118 { 103 119 *s = bswap16(*s); 104 120 } 105 121 122 #ifndef VBOX 106 123 static inline void bswap32s(uint32_t *s) 124 #else 125 DECLINLINE(void) bswap32s(uint32_t *s) 126 #endif 107 127 { 108 128 *s = bswap32(*s); 109 129 } 110 130 131 #ifndef VBOX 111 132 static inline void bswap64s(uint64_t *s) 133 #else 134 DECLINLINE(void) bswap64s(uint64_t *s) 135 #endif 112 136 { 113 137 *s = bswap64(*s); … … 126 150 #endif 127 151 152 #ifndef VBOX 128 153 #define CPU_CONVERT(endian, size, type)\ 129 154 static inline type endian ## size ## _to_cpu(type v)\ … … 156 181 *p = cpu_to_ ## endian ## size(v);\ 157 182 } 183 #else /* VBOX */ 184 #define CPU_CONVERT(endian, size, type)\ 185 DECLINLINE(type) endian ## size ## _to_cpu(type v)\ 186 {\ 187 return endian ## _bswap(v, size);\ 188 }\ 189 \ 190 DECLINLINE(type) cpu_to_ ## endian ## size(type v)\ 191 {\ 192 return endian ## _bswap(v, size);\ 193 }\ 194 \ 195 DECLINLINE(void) endian ## size ## _to_cpus(type *p)\ 196 {\ 197 endian ## _bswaps(p, size)\ 198 }\ 199 \ 200 DECLINLINE(void) cpu_to_ ## endian ## size ## s(type *p)\ 201 {\ 202 endian ## _bswaps(p, size)\ 203 }\ 204 \ 205 DECLINLINE(type) endian ## size ## _to_cpup(const type *p)\ 206 {\ 207 return endian ## size ## _to_cpu(*p);\ 208 }\ 209 \ 210 DECLINLINE(void) cpu_to_ ## endian ## size ## w(type *p, type v)\ 211 {\ 212 *p = cpu_to_ ## endian ## size(v);\ 213 } 214 #endif /* VBOX */ 158 215 159 216 CPU_CONVERT(be, 16, uint16_t) trunk/src/recompiler_new/cpu-all.h
r13230 r13382 32 32 #ifdef VBOX 33 33 # ifndef LOG_GROUP 34 # include <VBox/log.h>35 34 # define LOG_GROUP LOG_GROUP_REM 36 35 # endif 36 # include <VBox/log.h> 37 37 # include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */ 38 38 #endif … … 95 95 #else 96 96 97 #ifndef VBOX 97 98 static inline uint16_t tswap16(uint16_t s) 99 #else 100 DECLINLINE(uint16_t) tswap16(uint16_t s) 101 #endif 98 102 { 99 103 return s; 100 104 } 101 105 106 #ifndef VBOX 102 107 static inline uint32_t tswap32(uint32_t s) 108 #else 109 DECLINLINE(uint32_t) tswap32(uint32_t s) 110 #endif 103 111 { 104 112 return s; 105 113 } 106 114 115 #ifndef VBOX 107 116 static inline uint64_t tswap64(uint64_t s) 117 #else 118 DECLINLINE(uint64_t) tswap64(uint64_t s) 119 #endif 108 120 { 109 121 return s; 110 122 } 111 123 124 #ifndef VBOX 112 125 static inline void tswap16s(uint16_t *s) 113 { 114 } 115 126 #else 127 DECLINLINE(void) tswap16s(uint16_t *s) 128 #endif 129 { 130 } 131 132 #ifndef VBOX 116 133 static inline void tswap32s(uint32_t *s) 117 { 118 } 119 134 #else 135 DECLINLINE(void) tswap32s(uint32_t *s) 136 #endif 137 { 138 } 139 140 #ifndef VBOX 120 141 static inline void tswap64s(uint64_t *s) 142 #else 143 DECLINLINE(void) tswap64s(uint64_t *s) 144 #endif 121 145 { 122 146 } … … 249 273 #endif 250 274 251 static inline intldub_p(void *ptr)275 DECLINLINE(int) ldub_p(void *ptr) 252 276 { 253 277 VBOX_CHECK_ADDR(ptr); … … 255 279 } 256 280 257 static inline intldsb_p(void *ptr)281 DECLINLINE(int) ldsb_p(void *ptr) 258 282 { 259 283 VBOX_CHECK_ADDR(ptr); … … 261 285 } 262 286 263 static inline voidstb_p(void *ptr, int v)287 DECLINLINE(void) stb_p(void *ptr, int v) 264 288 { 265 289 VBOX_CHECK_ADDR(ptr); … … 267 291 } 268 292 269 static inline intlduw_le_p(void *ptr)293 DECLINLINE(int) lduw_le_p(void *ptr) 270 294 { 271 295 VBOX_CHECK_ADDR(ptr); … … 273 297 } 274 298 275 static inline intldsw_le_p(void *ptr)299 DECLINLINE(int) ldsw_le_p(void *ptr) 276 300 { 277 301 VBOX_CHECK_ADDR(ptr); … … 279 303 } 280 304 281 static inline voidstw_le_p(void *ptr, int v)305 DECLINLINE(void) stw_le_p(void *ptr, int v) 282 306 { 283 307 VBOX_CHECK_ADDR(ptr); … … 285 309 } 286 310 287 static inline intldl_le_p(void *ptr)311 DECLINLINE(int) ldl_le_p(void *ptr) 288 312 { 289 313 VBOX_CHECK_ADDR(ptr); … … 291 315 } 292 316 293 static inline voidstl_le_p(void *ptr, int v)317 DECLINLINE(void) stl_le_p(void *ptr, int v) 294 318 { 295 319 VBOX_CHECK_ADDR(ptr); … … 297 321 } 298 322 299 static inline voidstq_le_p(void *ptr, uint64_t v)323 DECLINLINE(void) stq_le_p(void *ptr, uint64_t v) 300 324 { 301 325 VBOX_CHECK_ADDR(ptr); … … 303 327 } 304 328 305 static inline uint64_tldq_le_p(void *ptr)329 DECLINLINE(uint64_t) ldq_le_p(void *ptr) 306 330 { 307 331 VBOX_CHECK_ADDR(ptr); … … 313 337 /* float access */ 314 338 315 static inline float32ldfl_le_p(void *ptr)339 DECLINLINE(float32) ldfl_le_p(void *ptr) 316 340 { 317 341 union { … … 323 347 } 324 348 325 static inline voidstfl_le_p(void *ptr, float32 v)349 DECLINLINE(void) stfl_le_p(void *ptr, float32 v) 326 350 { 327 351 union { … … 333 357 } 334 358 335 static inline float64ldfq_le_p(void *ptr)359 DECLINLINE(float64) ldfq_le_p(void *ptr) 336 360 { 337 361 CPU_DoubleU u; 338 362 u.l.lower = ldl_le_p(ptr); 339 u.l.upper = ldl_le_p( ptr + 4);363 u.l.upper = ldl_le_p((uint8_t*)ptr + 4); 340 364 return u.d; 341 365 } 342 366 343 static inline voidstfq_le_p(void *ptr, float64 v)367 DECLINLINE(void) stfq_le_p(void *ptr, float64 v) 344 368 { 345 369 CPU_DoubleU u; 346 370 u.d = v; 347 371 stl_le_p(ptr, u.l.lower); 348 stl_le_p( ptr + 4, u.l.upper);372 stl_le_p((uint8_t*)ptr + 4, u.l.upper); 349 373 } 350 374 … … 549 573 #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) 550 574 575 #ifndef VBOX 551 576 static inline int lduw_be_p(void *ptr) 552 577 { … … 563 588 #endif 564 589 } 565 590 #else /* VBOX */ 591 DECLINLINE(int) lduw_be_p(void *ptr) 592 { 593 #if defined(__i386__) && !defined(_MSC_VER) 594 int val; 595 asm volatile ("movzwl %1, %0\n" 596 "xchgb %b0, %h0\n" 597 : "=q" (val) 598 : "m" (*(uint16_t *)ptr)); 599 return val; 600 #else 601 uint8_t *b = (uint8_t *) ptr; 602 return ((b[0] << 8) | b[1]); 603 #endif 604 } 605 #endif 606 607 #ifndef VBOX 566 608 static inline int ldsw_be_p(void *ptr) 567 609 { … … 578 620 #endif 579 621 } 580 622 #else 623 DECLINLINE(int) ldsw_be_p(void *ptr) 624 { 625 #if defined(__i386__) && !defined(_MSC_VER) 626 int val; 627 asm volatile ("movzwl %1, %0\n" 628 "xchgb %b0, %h0\n" 629 : "=q" (val) 630 : "m" (*(uint16_t *)ptr)); 631 return (int16_t)val; 632 #else 633 uint8_t *b = (uint8_t *) ptr; 634 return (int16_t)((b[0] << 8) | b[1]); 635 #endif 636 } 637 #endif 638 639 #ifndef VBOX 581 640 static inline int ldl_be_p(void *ptr) 582 641 { … … 593 652 #endif 594 653 } 595 654 #else 655 DECLINLINE(int) ldl_be_p(void *ptr) 656 { 657 #if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER) 658 int val; 659 asm volatile ("movl %1, %0\n" 660 "bswap %0\n" 661 : "=r" (val) 662 : "m" (*(uint32_t *)ptr)); 663 return val; 664 #else 665 uint8_t *b = (uint8_t *) ptr; 666 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; 667 #endif 668 } 669 #endif 670 671 #ifndef VBOX 596 672 static inline uint64_t ldq_be_p(void *ptr) 673 #else 674 DECLINLINE(uint64_t) ldq_be_p(void *ptr) 675 #endif 597 676 { 598 677 uint32_t a,b; 599 678 a = ldl_be_p(ptr); 600 b = ldl_be_p( ptr+4);679 b = ldl_be_p((uint8_t*)ptr+4); 601 680 return (((uint64_t)a<<32)|b); 602 681 } 603 682 683 #ifndef VBOX 604 684 static inline void stw_be_p(void *ptr, int v) 605 685 { … … 615 695 #endif 616 696 } 617 697 #else 698 DECLINLINE(void) stw_be_p(void *ptr, int v) 699 { 700 #if defined(__i386__) && !defined(_MSC_VER) 701 asm volatile ("xchgb %b0, %h0\n" 702 "movw %w0, %1\n" 703 : "=q" (v) 704 : "m" (*(uint16_t *)ptr), "0" (v)); 705 #else 706 uint8_t *d = (uint8_t *) ptr; 707 d[0] = v >> 8; 708 d[1] = v; 709 #endif 710 } 711 712 #endif /* VBOX */ 713 714 #ifndef VBOX 618 715 static inline void stl_be_p(void *ptr, int v) 619 716 { … … 631 728 #endif 632 729 } 633 730 #else 731 DECLINLINE(void) stl_be_p(void *ptr, int v) 732 { 733 #if !defined(_MSC_VER) && (defined(__i386__) || defined(__x86_64__)) 734 asm volatile ("bswap %0\n" 735 "movl %0, %1\n" 736 : "=r" (v) 737 : "m" (*(uint32_t *)ptr), "0" (v)); 738 #else 739 uint8_t *d = (uint8_t *) ptr; 740 d[0] = v >> 24; 741 d[1] = v >> 16; 742 d[2] = v >> 8; 743 d[3] = v; 744 #endif 745 } 746 #endif /* VBOX */ 747 748 #ifndef VBOX 634 749 static inline void stq_be_p(void *ptr, uint64_t v) 750 #else 751 DECLINLINE(void) stq_be_p(void *ptr, uint64_t v) 752 #endif 635 753 { 636 754 stl_be_p(ptr, v >> 32); 637 stl_be_p( ptr + 4, v);755 stl_be_p((uint8_t*)ptr + 4, v); 638 756 } 639 757 640 758 /* float access */ 641 759 #ifndef VBOX 642 760 static inline float32 ldfl_be_p(void *ptr) 761 #else 762 DECLINLINE(float32) ldfl_be_p(void *ptr) 763 #endif 643 764 { 644 765 union { … … 650 771 } 651 772 773 #ifndef VBOX 652 774 static inline void stfl_be_p(void *ptr, float32 v) 775 #else 776 DECLINLINE(void) stfl_be_p(void *ptr, float32 v) 777 #endif 653 778 { 654 779 union { … … 660 785 } 661 786 787 #ifndef VBOX 662 788 static inline float64 ldfq_be_p(void *ptr) 789 #else 790 DECLINLINE(float64) ldfq_be_p(void *ptr) 791 #endif 663 792 { 664 793 CPU_DoubleU u; 665 794 u.l.upper = ldl_be_p(ptr); 666 u.l.lower = ldl_be_p( ptr + 4);795 u.l.lower = ldl_be_p((uint8_t*)ptr + 4); 667 796 return u.d; 668 797 } 669 798 799 #ifndef VBOX 670 800 static inline void stfq_be_p(void *ptr, float64 v) 801 #else 802 DECLINLINE(void) stfq_be_p(void *ptr, float64 v) 803 #endif 671 804 { 672 805 CPU_DoubleU u; 673 806 u.d = v; 674 807 stl_be_p(ptr, u.l.upper); 675 stl_be_p( ptr + 4, u.l.lower);808 stl_be_p((uint8_t*)ptr + 4, u.l.lower); 676 809 } 677 810 … … 1103 1236 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, 1104 1237 int len, int is_write); 1238 #ifndef VBOX 1105 1239 static inline void cpu_physical_memory_read(target_phys_addr_t addr, 1106 1240 uint8_t *buf, int len) 1241 #else 1242 DECLINLINE(void) cpu_physical_memory_read(target_phys_addr_t addr, 1243 uint8_t *buf, int len) 1244 #endif 1107 1245 { 1108 1246 cpu_physical_memory_rw(addr, bu

