Changeset 13197

Timestamp:

10/13/08 10:52:06 (3 months ago)

Author:

vboxsync

Message:

Backed out 37737&37738. (regressions)

Files:

• trunk/include/VBox/hwacc_vmx.h (modified) (2 diffs)
• trunk/include/VBox/pgm.h (modified) (1 diff)
• trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (1 diff)
• trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (70 diffs)
• trunk/src/VBox/VMM/VMMR0/HWVMXR0.h (modified) (2 diffs)

trunk/include/VBox/hwacc_vmx.h

@@ -1380 +1380 @@
- * @returns VBox status code
- * @param   idxField        VMCS index
+ * @param   u64Val          16, 32 or 64 bits value
+ */
+DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
+
+/**
+ * Executes VMWRITE
+ *
+ * @returns VBox status code
+ * @param   idxField        VMCS index
- * @param   u32Val          32 bits value
- */
-
-
-
-
-
-
+
-DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
-#else
@@ -1432 +1436 @@
-#endif
-
-/**
- * Executes VMWRITE
- *
- * @returns VBox status code
- * @param   idxField        VMCS index
- * @param   u64Val          16, 32 or 64 bits value
- */
-#if HC_ARCH_BITS == 64
-
+
-#else
-
-
-
-
-
-
-
-
-
+
+
-
-

trunk/include/VBox/pgm.h

@@ -336 +336 @@
-VMMDECL(int)    PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
-VMMDECL(int)    PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
-VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdPt);
-
-VMMDECL(int)    PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
-VMMDECL(int)    PGMUpdateCR3(PVM pVM, uint64_t cr3);

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -1211 +1211 @@
-}
-
-/**
- * Gets the specified page directory pointer table entry.
- *
- * @returns PDP entry
- * @param   pPGM        Pointer to the PGM instance data.
- * @param   iPdpt       PDPT index
- */
-VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
-{
-    Assert(iPdpt <= 3);
-    return pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[iPdpt & 3];
-}
-
-
-/**

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -52 +52 @@
-*******************************************************************************/
-#ifdef VBOX_STRICT
-vmx
+VMX
-#else
-#define VMXR0ReportWorldSwitchError(a, b, c)      do { } while (0);
-#endif /* VBOX_STRICT */
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-{
-    if (rc == VERR_VMX_GENERIC)
@@ -111 +110 @@
-    if (VBOX_FAILURE(rc))
-    {
-vmx
+VMX
-        ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
-        return VERR_VMX_VMXON_FAILED;
@@ -279 +278 @@
-    val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
-
-32
+
-    AssertRC(rc);
-
@@ -329 +328 @@
-    pVM->hwaccm.s.vmx.proc_ctls = val;
-
-32
+
-    AssertRC(rc);
-
@@ -354 +353 @@
-        val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
-
-32
+
-        AssertRC(rc);
-    }
@@ -361 +360 @@
-     * Set required bits to one and zero according to the MSR capabilities.
-     */
-32
+
-    AssertRC(rc);
-
@@ -378 +377 @@
-    val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
-    /* Don't acknowledge external interrupts on VM-exit. */
-32
+
-    AssertRC(rc);
-
@@ -398 +397 @@
-        pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_PF);   /* no longer need to intercept #PF. */
-#endif
-32
+
-    AssertRC(rc);
-
-    /* Don't filter page faults; all of them should cause a switch. */
-32
-32
+
+
-    AssertRC(rc);
-
-    /* Init TSC offset to zero. */
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-    AssertRC(rc);
-
@@ -420 +428 @@
-    {
-        /* Optional */
-
+
+
+
+
-        AssertRC(rc);
-    }
-
-    /* Clear MSR controls. */
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-    AssertRC(rc);
-
@@ -436 +452 @@
-        Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
-        /* Optional */
-
-
+
+
+
+
+
-        AssertRC(rc);
-    }
-
-    /* Set link pointer to -1. Not currently used. */
-
+
+
+
+
+
+
-    AssertRC(rc);
-
@@ -452 +476 @@
-    if (pVM->hwaccm.s.fNestedPaging)
-    {
-vmx
+VMX
-
-        /* Default values for flushing. */
@@ -472 +496 @@
-    if (pVM->hwaccm.s.vmx.fVPID)
-    {
-vmx
+VMX
-
-        /* Default values for flushing. */
@@ -490 +514 @@
-#endif /* HWACCM_VTX_WITH_VPID */
-    else
-vmx
+VMX
-
-
-vmx_end:
-vmx
+VMX
-    return rc;
-}
@@ -549 +573 @@
-
-    /* Set event injection state. */
-32
-
-32
-32
+
+
+
+
-
-    AssertRC(rc);
@@ -592 +616 @@
-                LogFlow(("Enable irq window exit!\n"));
-                pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
-32
+
-                AssertRC(rc);
-            }
@@ -708 +732 @@
-
-        /* Control registers */
-32
-32
-32
+
+
+
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
@@ -717 +741 @@
-
-        /* Selector registers. */
-32
+
-        /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
-32
-32
+
+
-#if HC_ARCH_BITS == 32
-32
-32
-
-32
+
+
+
+
-        SelTR = ASMGetTR();
-32
+
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
@@ -739 +763 @@
-        /* GDTR & IDTR */
-        ASMGetGDTR(&gdtr);
-32
+
-        ASMGetIDTR(&idtr);
-32
+
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
@@ -759 +783 @@
-        trBase = X86DESC_BASE(*pDesc);
-#endif
-32
+
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
@@ -774 +798 @@
-        /* Sysenter MSRs. */
-        /** @todo expensive!! */
-32
+
-        Log2(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
-#if HC_ARCH_BITS == 32
-32
-32
+
+
-        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
-        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
@@ -794 +818 @@
-}
-
-/**
- * Prefetch the 4 PDPT pointers (PAE and nested paging only)
- *
- * @param   pVM         The VM to operate on.
- * @param   pCtx        Guest context
- */
-static void vmxR0PrefetchPAEPdptrs(PVM pVM, PCPUMCTX pCtx)
-{
-    if (    (pCtx->cr4 & X86_CR4_PAE)
-        &&  !CPUMIsGuestInLongModeEx(pCtx))
-    {
-        X86PDPE Pdpe;
-
-        for (unsigned i=0;i<4;i++)
-        {
-            Pdpe = PGMGstGetPaePDPtr(pVM, i);
-            int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
-            AssertRC(rc);
-        }
-    }
-}
-
-/**
@@ -957 +960 @@
-        if (pCtx->ldtr == 0)
-        {
-32
-32
-32
+
+
+
-            /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
-32
+
-        }
-        else
-        {
-32
-32
-32
-32
+
+
+
+
-        }
-        AssertRC(rc);
@@ -985 +988 @@
-            AssertRC(rc);
-
-32
-32
-32
+
+
+
-
-            X86DESCATTR attr;
@@ -999 +1002 @@
-#endif /* HWACCM_VMX_EMULATE_REALMODE */
-        {
-32
-32
-32
+
+
+
-
-            val = pCtx->trHid.Attr.u;
@@ -1013 +1016 @@
-
-        }
-32
+
-        AssertRC(rc);
-    }
@@ -1019 +1022 @@
-    if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
-    {
-32
-32
+
+
-        AssertRC(rc);
-    }
@@ -1026 +1029 @@
-    if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
-    {
-32
-32
+
+
-        AssertRC(rc);
-    }
@@ -1034 +1037 @@
-     * Sysenter MSRs (unconditional)
-     */
-32
-32
-32
+
+
+
-    AssertRC(rc);
-
@@ -1043 +1046 @@
-    {
-        val = pCtx->cr0;
-32
+
-        Log2(("Guest CR0-shadow %08x\n", val));
-        if (CPUMIsGuestFPUStateActive(pVM) == false)
@@ -1061 +1064 @@
-                {
-                    pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
-32
+
-                    AssertRC(rc);
-                    pVM->hwaccm.s.fFPUOldStyleOverride = true;
@@ -1085 +1088 @@
-                                               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
-            }
-32
+
-            AssertRC(rc);
-        }
@@ -1097 +1100 @@
-        val &= ~(X86_CR0_CD|X86_CR0_NW);
-
-32
+
-        Log2(("Guest CR0 %08x\n", val));
-        /* CR0 flags owned by the host; if the guests attempts to change them, then
@@ -1113 +1116 @@
-        pVM->hwaccm.s.vmx.cr0_mask = val;
-
-32
+
-        Log2(("Guest CR0-mask %08x\n", val));
-        AssertRC(rc);
@@ -1120 +1123 @@
-    {
-        /* CR4 */
-32
+
-        Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
-        /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
@@ -1168 +1171 @@
-#endif /* HWACCM_VMX_EMULATE_REALMODE */
-
-32
+
-        Log2(("Guest CR4 %08x\n", val));
-        /* CR4 flags owned by the host; if the guests attempts to change them, then
@@ -1183 +1186 @@
-        pVM->hwaccm.s.vmx.cr4_mask = val;
-
-32
+
-        Log2(("Guest CR4-mask %08x\n", val));
-        AssertRC(rc);
@@ -1200 +1203 @@
-                                           | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
-            
-
+
+
+
+
-            AssertRC(rc);
-
@@ -1220 +1226 @@
-                /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
-                val = pCtx->cr3;
-
-                /* Prefetch the four PDPT entries in PAE mode. */
-                vmxR0PrefetchPAEPdptrs(pVM, pCtx);
-            }
-        }
@@ -1232 +1235 @@
-
-        /* Save our shadow CR3 register. */
-32
+
-        AssertRC(rc);
-    }
@@ -1247 +1250 @@
-
-        /* Resync DR7 */
-32
+
-        AssertRC(rc);
-
@@ -1259 +1262 @@
-            /* Disable drx move intercepts. */
-            pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
-32
+
-            AssertRC(rc);
-
@@ -1268 +1271 @@
-
-        /* IA32_DEBUGCTL MSR. */
-32
-32
+
+
-        AssertRC(rc);
-
-        /** @todo do we really ever need this? */
-32
+
-        AssertRC(rc);
-    }
-
-    /* EIP, ESP and EFLAGS */
-32
-32
+
+
-    AssertRC(rc);
-
@@ -1295 +1298 @@
-    }
-#endif /* HWACCM_VMX_EMULATE_REALMODE */
-32
+
-    AssertRC(rc);
-
@@ -1304 +1307 @@
-    {
-        /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
-
+
+
+
+
-        AssertRC(rc);
-
-        pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
-32
+
-        AssertRC(rc);
-        STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
@@ -1315 +1321 @@
-    {
-        pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
-32
+
-        AssertRC(rc);
-        STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
@@ -1334 +1340 @@
-    /* Mask away the bits that the CPU doesn't support */
-    val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
-32
+
-    AssertRC(rc);
-
@@ -1346 +1352 @@
-#endif
-        /* Unconditionally update these as wrmsr might have changed them. */
-32
-
-32
+
+
+
-        AssertRC(rc);
-    }
@@ -1363 +1369 @@
-        pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
-
-32
+
-#endif
-
@@ -1376 +1382 @@
-        pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_GP);
-# endif /* HWACCM_VMX_EMULATE_REALMODE */
-32
+
-    AssertRC(rc);
-#endif
@@ -1448 +1454 @@
-            PGMUpdateCR3(pVM, val);
-        }
-        /* Prefetch the four PDPT entries in PAE mode. */
-        vmxR0PrefetchPAEPdptrs(pVM, pCtx);
-    }
-
@@ -1512 +1516 @@
- * @param   pVM         The VM to operate on.
- */
-vmx
+VMX
-{
-    return;
@@ -1523 +1527 @@
- * @param   pVM         The VM to operate on.
- */
-vmx
+VMX
-{
-    PHWACCM_CPUINFO pCpu;
@@ -1548 +1552 @@
-
-    if (pVM->hwaccm.s.fForceTLBFlush)
-vmx
+VMX
-
-#ifdef VBOX_WITH_STATISTICS
@@ -1565 +1569 @@
- * @param   pVM         The VM to operate on.
- */
-vmx
+VMX
-{
-    PHWACCM_CPUINFO pCpu;
@@ -1618 +1622 @@
-    AssertMsg(pVM->hwaccm.s.uCurrentASID >= 1 && pVM->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.uCurrentASID));
-
-32
+
-    AssertRC(rc);
-
-    if (pVM->hwaccm.s.fForceTLBFlush)
-vmxr0
+VMXR0F
-
-#ifdef VBOX_WITH_STATISTICS
@@ -1737 +1741 @@
-            VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
-            /* Irq inhibition is no longer active; clear the corresponding VMX state. */
-32
+
-            AssertRC(rc);
-        }
@@ -1744 +1748 @@
-    {
-        /* Irq inhibition is no longer active; clear the corresponding VMX state. */
-32
+
-        AssertRC(rc);
-    }
@@ -1800 +1804 @@
-         *   -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
-         */
-32
+
-        AssertRC(rc);
-
@@ -1855 +1859 @@
-    /* Non-register state Guest Context */
-    /** @todo change me according to cpu state */
-32
+
-    AssertRC(rc);
-
@@ -1896 +1900 @@
-    if (rc != VINF_SUCCESS)
-    {
-vmx
+VMX
-        goto end;
-    }
@@ -2175 +2179 @@
-
-                    /* Resync DR7 */
-32
+
-                    AssertRC(rc);
-
@@ -2336 +2340 @@
-        LogFlow(("VMX_EXIT_IRQ_WINDOW %VGv pending=%d IF=%d\n", pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
-        pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
-32
+
-        AssertRC(rc);
-        STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
@@ -2516 +2520 @@
-            /* Disable drx move intercepts. */
-            pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
-32
+
-            AssertRC(rc);
-
@@ -2684 +2688 @@
-
-                            /* Resync DR7 */
-32
+
-                            AssertRC(rc);
-
@@ -2958 +2962 @@
-        /* Enable drx move intercepts again. */
-        pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
-32
+
-        AssertRC(rc);
-
@@ -2982 +2986 @@
- * @param   GCPhys      Physical address of the page to flush
- */
-vmx
+VMX
-{
-    uint64_t descriptor[2];
@@ -3003 +3007 @@
- * @param   GCPtr       Virtual address of the page to flush
- */
-vmx
+VMX
-{
-    uint64_t descriptor[2];
@@ -3033 +3037 @@
-    if (   !fFlushPending 
-        && pVM->hwaccm.s.vmx.fVPID)
-vmx
+VMX
-#endif /* HWACCM_VTX_WITH_VPID */
-
@@ -3056 +3060 @@
-    /* Skip it if a TLB flush is already pending. */
-    if (!fFlushPending)
-vmx
+VMX
-
-    return VINF_SUCCESS;
@@ -3069 +3073 @@
- * @param   pCtx        Current CPU context (not updated)
- */
-vmx
+VMX
-{
-    switch (rc)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.h

@@ -137 +137 @@
-#define VMX_WRITE_SELREG(REG, reg) \
-{                                                                                               \
-32(VMX_VMCS_GUEST_FIELD_##REG,      pCtx->reg);
-32(VMX_VMCS_GUEST_##REG##_LIMIT,    pCtx->reg##Hid.u32Limit);
-64(VMX_VMCS_GUEST_##REG##_BASE,     pCtx->reg##Hid.u64Base);
+(VMX_VMCS_GUEST_FIELD_##REG,      pCtx->reg);  
+(VMX_VMCS_GUEST_##REG##_LIMIT,    pCtx->reg##Hid.u32Limit);  
+(VMX_VMCS_GUEST_##REG##_BASE,     pCtx->reg##Hid.u64Base);  
-        if ((pCtx->eflags.u32 & X86_EFL_VM))                                                    \
-            val = pCtx->reg##Hid.Attr.u;                                                        \
@@ -156 +156 @@
-            val = 0x10000;  /* Invalid guest state error otherwise. (BIT(16) = Unusable) */     \
-                                                                                                \
-32(VMX_VMCS_GUEST_##REG##_ACCESS_RIGHTS, val);
+(VMX_VMCS_GUEST_##REG##_ACCESS_RIGHTS, val);  
-}
-