Changeset 13195

Timestamp:

10/13/08 10:45:56 (3 months ago)

Author:

vboxsync

Message:

Prefetch the four PDPT entries in PAE mode (EPT only).

Files:

• trunk/include/VBox/hwacc_vmx.h (modified) (3 diffs)
• trunk/include/VBox/pgm.h (modified) (1 diff)
• trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (1 diff)
• trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (70 diffs)
• trunk/src/VBox/VMM/VMMR0/HWVMXR0.h (modified) (2 diffs)

trunk/include/VBox/hwacc_vmx.h

@@ -1382 +1382 @@
- * @param   u64Val          16, 32 or 64 bits value
- */
+#if HC_ARCH_BITS == 64
-DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
+#else
+DECLINLINE(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val)
+{
+    int rc;
+
+    rc  = VMXWriteVMCS32(idxField,    u64Val);
+    rc |= VMXWriteVMCS32(idxField+1,  u64Val >> 32ULL);
+    return rc;
+}
+#endif
-
-/**
@@ -1391 +1402 @@
- * @param   u32Val          32 bits value
- */
-
+
+
+
+
+
+
-DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
-#else
@@ -1435 +1451 @@
-}
-#endif
-
-#if HC_ARCH_BITS == 64
-#define VMXWriteVMCS VMXWriteVMCS64
-#else
-#define VMXWriteVMCS VMXWriteVMCS32
-#endif /* HC_ARCH_BITS == 64 */
-
-

trunk/include/VBox/pgm.h

@@ -336 +336 @@
-VMMDECL(int)    PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
-VMMDECL(int)    PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
+VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdPt);
+
-VMMDECL(int)    PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
-VMMDECL(int)    PGMUpdateCR3(PVM pVM, uint64_t cr3);

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -1211 +1211 @@
-}
-
+/**
+ * Gets the specified page directory pointer table entry.
+ *
+ * @returns PDP entry
+ * @param   pPGM        Pointer to the PGM instance data.
+ * @param   iPdpt       PDPT index
+ */
+VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
+{
+    Assert(iPdpt <= 3);
+    return pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[iPdpt & 3];
+}
+
-
-/**

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -52 +52 @@
-*******************************************************************************/
-#ifdef VBOX_STRICT
-VMX
+vmx
-#else
-#define VMXR0ReportWorldSwitchError(a, b, c)      do { } while (0);
-#endif /* VBOX_STRICT */
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
-{
-    if (rc == VERR_VMX_GENERIC)
@@ -110 +111 @@
-    if (VBOX_FAILURE(rc))
-    {
-VMX
+vmx
-        ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
-        return VERR_VMX_VMXON_FAILED;
@@ -278 +279 @@
-    val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
-
-
+32
-    AssertRC(rc);
-
@@ -328 +329 @@
-    pVM->hwaccm.s.vmx.proc_ctls = val;
-
-
+32
-    AssertRC(rc);
-
@@ -353 +354 @@
-        val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
-
-
+32
-        AssertRC(rc);
-    }
@@ -360 +361 @@
-     * Set required bits to one and zero according to the MSR capabilities.
-     */
-
+32
-    AssertRC(rc);
-
@@ -377 +378 @@
-    val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
-    /* Don't acknowledge external interrupts on VM-exit. */
-
+32
-    AssertRC(rc);
-
@@ -397 +398 @@
-        pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_PF);   /* no longer need to intercept #PF. */
-#endif
-
+32
-    AssertRC(rc);
-
-    /* Don't filter page faults; all of them should cause a switch. */
-
-
+32
+32
-    AssertRC(rc);
-
-    /* Init TSC offset to zero. */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-    AssertRC(rc);
-
@@ -428 +420 @@
-    {
-        /* Optional */
-
-
-
-
+
-        AssertRC(rc);
-    }
-
-    /* Clear MSR controls. */
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
-    AssertRC(rc);
-
@@ -452 +436 @@
-        Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
-        /* Optional */
-
-
-
-
-
+
+
-        AssertRC(rc);
-    }
-
-    /* Set link pointer to -1. Not currently used. */
-
-
-
-
-
-
+
-    AssertRC(rc);
-
@@ -476 +452 @@
-    if (pVM->hwaccm.s.fNestedPaging)
-    {
-VMX
+vmx
-
-        /* Default values for flushing. */
@@ -496 +472 @@
-    if (pVM->hwaccm.s.vmx.fVPID)
-    {
-VMX
+vmx
-
-        /* Default values for flushing. */
@@ -514 +490 @@
-#endif /* HWACCM_VTX_WITH_VPID */
-    else
-VMX
+vmx
-
-
-vmx_end:
-VMX
+vmx
-    return rc;
-}
@@ -573 +549 @@
-
-    /* Set event injection state. */
-
-
-
-
+32
+
+32
+32
-
-    AssertRC(rc);
@@ -616 +592 @@
-                LogFlow(("Enable irq window exit!\n"));
-                pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
-
+32
-                AssertRC(rc);
-            }
@@ -732 +708 @@
-
-        /* Control registers */
-
-
-
+32
+32
+32
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
@@ -741 +717 @@
-
-        /* Selector registers. */
-
+32
-        /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
-
-
+32
+32
-#if HC_ARCH_BITS == 32
-
-
-
-
+32
+32
+
+32
-        SelTR = ASMGetTR();
-
+32
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
@@ -763 +739 @@
-        /* GDTR & IDTR */
-        ASMGetGDTR(&gdtr);
-
+32
-        ASMGetIDTR(&idtr);
-
+32
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
@@ -783 +759 @@
-        trBase = X86DESC_BASE(*pDesc);
-#endif
-
+32
-        AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
@@ -798 +774 @@
-        /* Sysenter MSRs. */
-        /** @todo expensive!! */
-
+32
-        Log2(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
-#if HC_ARCH_BITS == 32
-
-
+32
+32
-        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
-        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
@@ -818 +794 @@
-}
-
+/**
+ * Prefetch the 4 PDPT pointers (PAE and nested paging only)
+ *
+ * @param   pVM         The VM to operate on.
+ * @param   pCtx        Guest context
+ */
+static void vmxR0PrefetchPAEPdptrs(PVM pVM, PCPUMCTX pCtx)
+{
+    if (    (pCtx->cr4 & X86_CR4_PAE)
+        &&  !CPUMIsGuestInLongModeEx(pCtx))
+    {
+        X86PDPE Pdpe;
+
+        for (unsigned i=0;i<4;i++)
+        {
+            Pdpe = PGMGstGetPaePDPtr(pVM, i);
+            int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
+            AssertRC(rc);
+        }
+    }
+}
-
-/**
@@ -960 +957 @@
-        if (pCtx->ldtr == 0)
-        {
-
-
-
+32
+32
+32
-            /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
-
+32
-        }
-        else
-        {
-
-
-
-
+32
+32
+32
+32
-        }
-        AssertRC(rc);
@@ -988 +985 @@
-            AssertRC(rc);
-
-
-
-
+32
+32
+32
-
-            X86DESCATTR attr;
@@ -1002 +999 @@
-#endif /* HWACCM_VMX_EMULATE_REALMODE */
-        {
-
-
-
+32
+32
+32
-
-            val = pCtx->trHid.Attr.u;
@@ -1016 +1013 @@
-
-        }
-
+32
-        AssertRC(rc);
-    }
@@ -1022 +1019 @@
-    if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
-    {
-
-
+32
+32
-        AssertRC(rc);
-    }
@@ -1029 +1026 @@
-    if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
-    {
-
-
+32
+32
-        AssertRC(rc);
-    }
@@ -1037 +1034 @@
-     * Sysenter MSRs (unconditional)
-     */
-
-
-
+32
+32
+32
-    AssertRC(rc);
-
@@ -1046 +1043 @@
-    {
-        val = pCtx->cr0;
-
+32
-        Log2(("Guest CR0-shadow %08x\n", val));
-        if (CPUMIsGuestFPUStateActive(pVM) == false)
@@ -1064 +1061 @@
-                {
-                    pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
-
+32
-                    AssertRC(rc);
-                    pVM->hwaccm.s.fFPUOldStyleOverride = true;
@@ -1088 +1085 @@
-                                               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
-            }
-
+32
-            AssertRC(rc);
-        }
@@ -1100 +1097 @@
-        val &= ~(X86_CR0_CD|X86_CR0_NW);
-
-
+32
-        Log2(("Guest CR0 %08x\n", val));
-        /* CR0 flags owned by the host; if the guests attempts to change them, then
@@ -1116 +1113 @@
-        pVM->hwaccm.s.vmx.cr0_mask = val;
-
-
+32
-        Log2(("Guest CR0-mask %08x\n", val));
-        AssertRC(rc);
@@ -1123 +1120 @@
-    {
-        /* CR4 */
-
+32
-        Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
-        /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
@@ -1171 +1168 @@
-#endif /* HWACCM_VMX_EMULATE_REALMODE */
-
-
+32
-        Log2(("Guest CR4 %08x\n", val));
-        /* CR4 flags owned by the host; if the guests attempts to change them, then
@@ -1186 +1183 @@
-        pVM->hwaccm.s.vmx.cr4_mask = val;
-
-
+32
-        Log2(("Guest CR4-mask %08x\n", val));
-        AssertRC(rc);
@@ -1203 +1200 @@
-                                           | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
-            
-
-
-
-
+
-            AssertRC(rc);
-
@@ -1226 +1220 @@
-                /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
-                val = pCtx->cr3;
+
+                /* Prefetch the four PDPT entries in PAE mode. */
+                vmxR0PrefetchPAEPdptrs(pVM, pCtx);
-            }
-        }
@@ -1235 +1232 @@
-
-        /* Save our shadow CR3 register. */
-
+32
-        AssertRC(rc);
-    }
@@ -1250 +1247 @@
-
-        /* Resync DR7 */
-
+32
-        AssertRC(rc);
-
@@ -1262 +1259 @@
-            /* Disable drx move intercepts. */
-            pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
-
+32
-            AssertRC(rc);
-
@@ -1271 +1268 @@
-
-        /* IA32_DEBUGCTL MSR. */
-
-
+32
+32
-        AssertRC(rc);
-
-        /** @todo do we really ever need this? */
-
+32
-        AssertRC(rc);
-    }
-
-    /* EIP, ESP and EFLAGS */
-
-
+32
+32
-    AssertRC(rc);
-
@@ -1298 +1295 @@
-    }
-#endif /* HWACCM_VMX_EMULATE_REALMODE */
-
+32
-    AssertRC(rc);
-
@@ -1307 +1304 @@
-    {
-        /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
-
-
-
-
+
-        AssertRC(rc);
-
-        pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
-
+32
-        AssertRC(rc);
-        STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
@@ -1321 +1315 @@
-    {
-        pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
-
+32
-        AssertRC(rc);
-        STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
@@ -1340 +1334 @@
-    /* Mask away the bits that the CPU doesn't support */
-    val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
-
+32
-    AssertRC(rc);
-
@@ -1352 +1346 @@
-#endif
-        /* Unconditionally update these as wrmsr might have changed them. */
-
-
-
+32
+
+32
-        AssertRC(rc);
-    }
@@ -1369 +1363 @@
-        pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
-
-
+32
-#endif
-
@@ -1382 +1376 @@
-        pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_GP);
-# endif /* HWACCM_VMX_EMULATE_REALMODE */
-
+32
-    AssertRC(rc);
-#endif
@@ -1454 +1448 @@
-            PGMUpdateCR3(pVM, val);
-        }
+        /* Prefetch the four PDPT entries in PAE mode. */
+        vmxR0PrefetchPAEPdptrs(pVM, pCtx);
-    }
-
@@ -1516 +1512 @@
- * @param   pVM         The VM to operate on.
- */
-VMX
+vmx
-{
-    return;
@@ -1527 +1523 @@
- * @param   pVM         The VM to operate on.
- */
-VMX
+vmx
-{
-    PHWACCM_CPUINFO pCpu;
@@ -1552 +1548 @@
-
-    if (pVM->hwaccm.s.fForceTLBFlush)
-VMX
+vmx
-
-#ifdef VBOX_WITH_STATISTICS
@@ -1569 +1565 @@
- * @param   pVM         The VM to operate on.
- */
-VMX
+vmx
-{
-    PHWACCM_CPUINFO pCpu;
@@ -1622 +1618 @@
-    AssertMsg(pVM->hwaccm.s.uCurrentASID >= 1 && pVM->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.uCurrentASID));
-
-
+32
-    AssertRC(rc);
-
-    if (pVM->hwaccm.s.fForceTLBFlush)
-VMXR0F
+vmxr0
-
-#ifdef VBOX_WITH_STATISTICS
@@ -1741 +1737 @@
-            VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
-            /* Irq inhibition is no longer active; clear the corresponding VMX state. */
-
+32
-            AssertRC(rc);
-        }
@@ -1748 +1744 @@
-    {
-        /* Irq inhibition is no longer active; clear the corresponding VMX state. */
-
+32
-        AssertRC(rc);
-    }
@@ -1804 +1800 @@
-         *   -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
-         */
-
+32
-        AssertRC(rc);
-
@@ -1859 +1855 @@
-    /* Non-register state Guest Context */
-    /** @todo change me according to cpu state */
-
+32
-    AssertRC(rc);
-
@@ -1900 +1896 @@
-    if (rc != VINF_SUCCESS)
-    {
-VMX
+vmx
-        goto end;
-    }
@@ -2179 +2175 @@
-
-                    /* Resync DR7 */
-
+32
-                    AssertRC(rc);
-
@@ -2340 +2336 @@
-        LogFlow(("VMX_EXIT_IRQ_WINDOW %VGv pending=%d IF=%d\n", pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
-        pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
-
+32
-        AssertRC(rc);
-        STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
@@ -2520 +2516 @@
-            /* Disable drx move intercepts. */
-            pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
-
+32
-            AssertRC(rc);
-
@@ -2688 +2684 @@
-
-                            /* Resync DR7 */
-
+32
-                            AssertRC(rc);
-
@@ -2962 +2958 @@
-        /* Enable drx move intercepts again. */
-        pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
-
+32
-        AssertRC(rc);
-
@@ -2986 +2982 @@
- * @param   GCPhys      Physical address of the page to flush
- */
-VMX
+vmx
-{
-    uint64_t descriptor[2];
@@ -3007 +3003 @@
- * @param   GCPtr       Virtual address of the page to flush
- */
-VMX
+vmx
-{
-    uint64_t descriptor[2];
@@ -3037 +3033 @@
-    if (   !fFlushPending 
-        && pVM->hwaccm.s.vmx.fVPID)
-VMX
+vmx
-#endif /* HWACCM_VTX_WITH_VPID */
-
@@ -3060 +3056 @@
-    /* Skip it if a TLB flush is already pending. */
-    if (!fFlushPending)
-VMX
+vmx
-
-    return VINF_SUCCESS;
@@ -3073 +3069 @@
- * @param   pCtx        Current CPU context (not updated)
- */
-VMX
+vmx
-{
-    switch (rc)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.h

@@ -137 +137 @@
-#define VMX_WRITE_SELREG(REG, reg) \
-{                                                                                               \
-(VMX_VMCS_GUEST_FIELD_##REG,      pCtx->reg);  
-(VMX_VMCS_GUEST_##REG##_LIMIT,    pCtx->reg##Hid.u32Limit);  
-(VMX_VMCS_GUEST_##REG##_BASE,     pCtx->reg##Hid.u64Base);  
+32(VMX_VMCS_GUEST_FIELD_##REG,      pCtx->reg);
+32(VMX_VMCS_GUEST_##REG##_LIMIT,    pCtx->reg##Hid.u32Limit);
+64(VMX_VMCS_GUEST_##REG##_BASE,     pCtx->reg##Hid.u64Base);
-        if ((pCtx->eflags.u32 & X86_EFL_VM))                                                    \
-            val = pCtx->reg##Hid.Attr.u;                                                        \
@@ -156 +156 @@
-            val = 0x10000;  /* Invalid guest state error otherwise. (BIT(16) = Unusable) */     \
-                                                                                                \
-(VMX_VMCS_GUEST_##REG##_ACCESS_RIGHTS, val);  
+32(VMX_VMCS_GUEST_##REG##_ACCESS_RIGHTS, val);
-}
-