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Changeset 10820

Timestamp:

07/23/08 09:18:14 (3 months ago)

Author:

vboxsync

Message:

Cleanup

Files:

trunk/include/VBox/hwacc_vmx.h (modified) (1 diff)
trunk/src/VBox/VMM/HWACCM.cpp (modified) (1 diff)

Legend:

: Unmodified
: Added
: Removed
: Modified
: Copied
: Moved

trunk/include/VBox/hwacc_vmx.h

r10818	r10820
325	325	* @{
326	326	*/
327		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
328		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
329		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
330		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
331		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
332		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
333		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
334		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
335		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
336		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
337		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
338		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
339		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
340		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
341		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
342		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
343		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
344		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
345		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
346		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
347		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
348		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
349		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
350		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
351		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
352		#define MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
	327	#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
	328	#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
	329	#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
	330	#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
	331	#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
	332	#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
	333	#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
	334	#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
	335	#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
	336	#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
	337	#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
	338	#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
	339	#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
	340	#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
	341	#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
	342	#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
	343	#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
	344	#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
	345	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
	346	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
	347	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
	348	#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
	349	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
	350	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
	351	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
	352	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
353	353
354	354	/** @} */

trunk/src/VBox/VMM/HWACCM.cpp

r10818	r10820
445	445	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
446	446
447		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
448		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
449		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
450		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
451		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
452		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
453		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_21_BITS)
454		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
455		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_30_BITS)
456		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
457		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_39_BITS)
458		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
459		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_48_BITS)
460		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
461		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_57_BITS)
462		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
463		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_UC)
464		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_UC\n"));
465		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WC)
466		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WC\n"));
467		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WT)
468		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WT\n"));
469		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WP)
470		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WP\n"));
471		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WB)
472		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_EMT_WB\n"));
473		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_21_BITS)
474		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
475		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_30_BITS)
476		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
477		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_39_BITS)
478		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
479		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_48_BITS)
480		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
481		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT)
482		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT\n"));
483		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
484		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
485		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
486		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
487		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
488		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
489		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID)
490		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID\n"));
491		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
492		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
493		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
494		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
495		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
496		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
497		if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
498		LogRel(("HWACCM: MSR~~VAL~~_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
	447	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
	448	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
	449	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
	450	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
	451	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
	452	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
	453	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
	454	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
	455	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
	456	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
	457	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
	458	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
	459	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
	460	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
	461	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
	462	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
	463	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
	464	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
	465	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
	466	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
	467	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
	468	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
	469	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
	470	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
	471	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
	472	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
	473	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
	474	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
	475	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
	476	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
	477	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
	478	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
	479	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
	480	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
	481	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
	482	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
	483	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
	484	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
	485	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
	486	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
	487	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
	488	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
	489	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
	490	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
	491	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
	492	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
	493	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
	494	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
	495	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
	496	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
	497	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
	498	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
499	499	}
500	500

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Changeset 10820

Legend:

trunk/include/VBox/hwacc_vmx.h

trunk/src/VBox/VMM/HWACCM.cpp

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