VirtualBox

source: vbox/trunk/src/recompiler_new/cpu-all.h@ 13762

Last change on this file since 13762 was 13559, checked in by vboxsync, 16 years ago

made TCG generate VBOX-aware phys mem access code, some more QEMU code merged
  • Property svn:eol-style set to native
File size: 36.4 KB
Line 
1/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#ifndef CPU_ALL_H
30#define CPU_ALL_H
31
32#ifdef VBOX
33# ifndef LOG_GROUP
34# define LOG_GROUP LOG_GROUP_REM
35# endif
36# include <VBox/log.h>
37# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
38#endif
39
40#if defined(__arm__) || defined(__sparc__)
41#define WORDS_ALIGNED
42#endif
43
44/* some important defines:
45 *
46 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
47 * memory accesses.
48 *
49 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
50 * otherwise little endian.
51 *
52 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
53 *
54 * TARGET_WORDS_BIGENDIAN : same for target cpu
55 */
56
57#include "bswap.h"
58
59#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
60#define BSWAP_NEEDED
61#endif
62
63#ifdef BSWAP_NEEDED
64
65static inline uint16_t tswap16(uint16_t s)
66{
67 return bswap16(s);
68}
69
70static inline uint32_t tswap32(uint32_t s)
71{
72 return bswap32(s);
73}
74
75static inline uint64_t tswap64(uint64_t s)
76{
77 return bswap64(s);
78}
79
80static inline void tswap16s(uint16_t *s)
81{
82 *s = bswap16(*s);
83}
84
85static inline void tswap32s(uint32_t *s)
86{
87 *s = bswap32(*s);
88}
89
90static inline void tswap64s(uint64_t *s)
91{
92 *s = bswap64(*s);
93}
94
95#else
96
97#ifndef VBOX
98static inline uint16_t tswap16(uint16_t s)
99#else
100DECLINLINE(uint16_t) tswap16(uint16_t s)
101#endif
102{
103 return s;
104}
105
106#ifndef VBOX
107static inline uint32_t tswap32(uint32_t s)
108#else
109DECLINLINE(uint32_t) tswap32(uint32_t s)
110#endif
111{
112 return s;
113}
114
115#ifndef VBOX
116static inline uint64_t tswap64(uint64_t s)
117#else
118DECLINLINE(uint64_t) tswap64(uint64_t s)
119#endif
120{
121 return s;
122}
123
124#ifndef VBOX
125static inline void tswap16s(uint16_t *s)
126#else
127DECLINLINE(void) tswap16s(uint16_t *s)
128#endif
129{
130}
131
132#ifndef VBOX
133static inline void tswap32s(uint32_t *s)
134#else
135DECLINLINE(void) tswap32s(uint32_t *s)
136#endif
137{
138}
139
140#ifndef VBOX
141static inline void tswap64s(uint64_t *s)
142#else
143DECLINLINE(void) tswap64s(uint64_t *s)
144#endif
145{
146}
147
148#endif
149
150#if TARGET_LONG_SIZE == 4
151#define tswapl(s) tswap32(s)
152#define tswapls(s) tswap32s((uint32_t *)(s))
153#define bswaptls(s) bswap32s(s)
154#else
155#define tswapl(s) tswap64(s)
156#define tswapls(s) tswap64s((uint64_t *)(s))
157#define bswaptls(s) bswap64s(s)
158#endif
159
160typedef union {
161 float32 f;
162 uint32_t l;
163} CPU_FloatU;
164
165/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
166 endian ! */
167typedef union {
168 float64 d;
169#if defined(WORDS_BIGENDIAN) \
170 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
171 struct {
172 uint32_t upper;
173 uint32_t lower;
174 } l;
175#else
176 struct {
177 uint32_t lower;
178 uint32_t upper;
179 } l;
180#endif
181 uint64_t ll;
182} CPU_DoubleU;
183
184#ifdef TARGET_SPARC
185typedef union {
186 float128 q;
187#if defined(WORDS_BIGENDIAN) \
188 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
189 struct {
190 uint32_t upmost;
191 uint32_t upper;
192 uint32_t lower;
193 uint32_t lowest;
194 } l;
195 struct {
196 uint64_t upper;
197 uint64_t lower;
198 } ll;
199#else
200 struct {
201 uint32_t lowest;
202 uint32_t lower;
203 uint32_t upper;
204 uint32_t upmost;
205 } l;
206 struct {
207 uint64_t lower;
208 uint64_t upper;
209 } ll;
210#endif
211} CPU_QuadU;
212#endif
213
214/* CPU memory access without any memory or io remapping */
215
216/*
217 * the generic syntax for the memory accesses is:
218 *
219 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
220 *
221 * store: st{type}{size}{endian}_{access_type}(ptr, val)
222 *
223 * type is:
224 * (empty): integer access
225 * f : float access
226 *
227 * sign is:
228 * (empty): for floats or 32 bit size
229 * u : unsigned
230 * s : signed
231 *
232 * size is:
233 * b: 8 bits
234 * w: 16 bits
235 * l: 32 bits
236 * q: 64 bits
237 *
238 * endian is:
239 * (empty): target cpu endianness or 8 bit access
240 * r : reversed target cpu endianness (not implemented yet)
241 * be : big endian (not implemented yet)
242 * le : little endian (not implemented yet)
243 *
244 * access_type is:
245 * raw : host memory access
246 * user : user mode access using soft MMU
247 * kernel : kernel mode access using soft MMU
248 */
249#ifdef VBOX
250
251void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb);
252uint8_t remR3PhysReadU8(RTGCPHYS SrcGCPhys);
253int8_t remR3PhysReadS8(RTGCPHYS SrcGCPhys);
254uint16_t remR3PhysReadU16(RTGCPHYS SrcGCPhys);
255int16_t remR3PhysReadS16(RTGCPHYS SrcGCPhys);
256uint32_t remR3PhysReadU32(RTGCPHYS SrcGCPhys);
257int32_t remR3PhysReadS32(RTGCPHYS SrcGCPhys);
258uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys);
259int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys);
260void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb);
261void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val);
262void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val);
263void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val);
264void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val);
265
266#ifndef VBOX_WITH_NEW_PHYS_CODE
267void remR3GrowDynRange(unsigned long physaddr);
268#endif
269#if 0 /*defined(RT_ARCH_AMD64) && defined(VBOX_STRICT)*/
270# define VBOX_CHECK_ADDR(ptr) do { if ((uintptr_t)(ptr) >= _4G) __asm__("int3"); } while (0)
271#else
272# define VBOX_CHECK_ADDR(ptr) do { } while (0)
273#endif
274
275DECLINLINE(int) ldub_p(void *ptr)
276{
277 VBOX_CHECK_ADDR(ptr);
278 return remR3PhysReadU8((uintptr_t)ptr);
279}
280
281DECLINLINE(int) ldsb_p(void *ptr)
282{
283 VBOX_CHECK_ADDR(ptr);
284 return remR3PhysReadS8((uintptr_t)ptr);
285}
286
287DECLINLINE(void) stb_p(void *ptr, int v)
288{
289 VBOX_CHECK_ADDR(ptr);
290 remR3PhysWriteU8((uintptr_t)ptr, v);
291}
292
293DECLINLINE(int) lduw_le_p(void *ptr)
294{
295 VBOX_CHECK_ADDR(ptr);
296 return remR3PhysReadU16((uintptr_t)ptr);
297}
298
299DECLINLINE(int) ldsw_le_p(void *ptr)
300{
301 VBOX_CHECK_ADDR(ptr);
302 return remR3PhysReadS16((uintptr_t)ptr);
303}
304
305DECLINLINE(void) stw_le_p(void *ptr, int v)
306{
307 VBOX_CHECK_ADDR(ptr);
308 remR3PhysWriteU16((uintptr_t)ptr, v);
309}
310
311DECLINLINE(int) ldl_le_p(void *ptr)
312{
313 VBOX_CHECK_ADDR(ptr);
314 return remR3PhysReadU32((uintptr_t)ptr);
315}
316
317DECLINLINE(void) stl_le_p(void *ptr, int v)
318{
319 VBOX_CHECK_ADDR(ptr);
320 remR3PhysWriteU32((uintptr_t)ptr, v);
321}
322
323DECLINLINE(void) stq_le_p(void *ptr, uint64_t v)
324{
325 VBOX_CHECK_ADDR(ptr);
326 remR3PhysWriteU64((uintptr_t)ptr, v);
327}
328
329DECLINLINE(uint64_t) ldq_le_p(void *ptr)
330{
331 VBOX_CHECK_ADDR(ptr);
332 return remR3PhysReadU64((uintptr_t)ptr);
333}
334
335#undef VBOX_CHECK_ADDR
336
337/* float access */
338
339DECLINLINE(float32) ldfl_le_p(void *ptr)
340{
341 union {
342 float32 f;
343 uint32_t i;
344 } u;
345 u.i = ldl_le_p(ptr);
346 return u.f;
347}
348
349DECLINLINE(void) stfl_le_p(void *ptr, float32 v)
350{
351 union {
352 float32 f;
353 uint32_t i;
354 } u;
355 u.f = v;
356 stl_le_p(ptr, u.i);
357}
358
359DECLINLINE(float64) ldfq_le_p(void *ptr)
360{
361 CPU_DoubleU u;
362 u.l.lower = ldl_le_p(ptr);
363 u.l.upper = ldl_le_p((uint8_t*)ptr + 4);
364 return u.d;
365}
366
367DECLINLINE(void) stfq_le_p(void *ptr, float64 v)
368{
369 CPU_DoubleU u;
370 u.d = v;
371 stl_le_p(ptr, u.l.lower);
372 stl_le_p((uint8_t*)ptr + 4, u.l.upper);
373}
374
375#else /* !VBOX */
376
377static inline int ldub_p(void *ptr)
378{
379 return *(uint8_t *)ptr;
380}
381
382static inline int ldsb_p(void *ptr)
383{
384 return *(int8_t *)ptr;
385}
386
387static inline void stb_p(void *ptr, int v)
388{
389 *(uint8_t *)ptr = v;
390}
391
392/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
393 kernel handles unaligned load/stores may give better results, but
394 it is a system wide setting : bad */
395#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
396
397/* conservative code for little endian unaligned accesses */
398static inline int lduw_le_p(void *ptr)
399{
400#ifdef __powerpc__
401 int val;
402 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
403 return val;
404#else
405 uint8_t *p = ptr;
406 return p[0] | (p[1] << 8);
407#endif
408}
409
410static inline int ldsw_le_p(void *ptr)
411{
412#ifdef __powerpc__
413 int val;
414 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
415 return (int16_t)val;
416#else
417 uint8_t *p = ptr;
418 return (int16_t)(p[0] | (p[1] << 8));
419#endif
420}
421
422static inline int ldl_le_p(void *ptr)
423{
424#ifdef __powerpc__
425 int val;
426 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
427 return val;
428#else
429 uint8_t *p = ptr;
430 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
431#endif
432}
433
434static inline uint64_t ldq_le_p(void *ptr)
435{
436 uint8_t *p = ptr;
437 uint32_t v1, v2;
438 v1 = ldl_le_p(p);
439 v2 = ldl_le_p(p + 4);
440 return v1 | ((uint64_t)v2 << 32);
441}
442
443static inline void stw_le_p(void *ptr, int v)
444{
445#ifdef __powerpc__
446 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
447#else
448 uint8_t *p = ptr;
449 p[0] = v;
450 p[1] = v >> 8;
451#endif
452}
453
454static inline void stl_le_p(void *ptr, int v)
455{
456#ifdef __powerpc__
457 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
458#else
459 uint8_t *p = ptr;
460 p[0] = v;
461 p[1] = v >> 8;
462 p[2] = v >> 16;
463 p[3] = v >> 24;
464#endif
465}
466
467static inline void stq_le_p(void *ptr, uint64_t v)
468{
469 uint8_t *p = ptr;
470 stl_le_p(p, (uint32_t)v);
471 stl_le_p(p + 4, v >> 32);
472}
473
474/* float access */
475
476static inline float32 ldfl_le_p(void *ptr)
477{
478 union {
479 float32 f;
480 uint32_t i;
481 } u;
482 u.i = ldl_le_p(ptr);
483 return u.f;
484}
485
486static inline void stfl_le_p(void *ptr, float32 v)
487{
488 union {
489 float32 f;
490 uint32_t i;
491 } u;
492 u.f = v;
493 stl_le_p(ptr, u.i);
494}
495
496static inline float64 ldfq_le_p(void *ptr)
497{
498 CPU_DoubleU u;
499 u.l.lower = ldl_le_p(ptr);
500 u.l.upper = ldl_le_p(ptr + 4);
501 return u.d;
502}
503
504static inline void stfq_le_p(void *ptr, float64 v)
505{
506 CPU_DoubleU u;
507 u.d = v;
508 stl_le_p(ptr, u.l.lower);
509 stl_le_p(ptr + 4, u.l.upper);
510}
511
512#else
513
514static inline int lduw_le_p(void *ptr)
515{
516 return *(uint16_t *)ptr;
517}
518
519static inline int ldsw_le_p(void *ptr)
520{
521 return *(int16_t *)ptr;
522}
523
524static inline int ldl_le_p(void *ptr)
525{
526 return *(uint32_t *)ptr;
527}
528
529static inline uint64_t ldq_le_p(void *ptr)
530{
531 return *(uint64_t *)ptr;
532}
533
534static inline void stw_le_p(void *ptr, int v)
535{
536 *(uint16_t *)ptr = v;
537}
538
539static inline void stl_le_p(void *ptr, int v)
540{
541 *(uint32_t *)ptr = v;
542}
543
544static inline void stq_le_p(void *ptr, uint64_t v)
545{
546 *(uint64_t *)ptr = v;
547}
548
549/* float access */
550
551static inline float32 ldfl_le_p(void *ptr)
552{
553 return *(float32 *)ptr;
554}
555
556static inline float64 ldfq_le_p(void *ptr)
557{
558 return *(float64 *)ptr;
559}
560
561static inline void stfl_le_p(void *ptr, float32 v)
562{
563 *(float32 *)ptr = v;
564}
565
566static inline void stfq_le_p(void *ptr, float64 v)
567{
568 *(float64 *)ptr = v;
569}
570#endif
571#endif /* !VBOX */
572
573#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
574
575#ifndef VBOX
576static inline int lduw_be_p(void *ptr)
577{
578#if defined(__i386__)
579 int val;
580 asm volatile ("movzwl %1, %0\n"
581 "xchgb %b0, %h0\n"
582 : "=q" (val)
583 : "m" (*(uint16_t *)ptr));
584 return val;
585#else
586 uint8_t *b = (uint8_t *) ptr;
587 return ((b[0] << 8) | b[1]);
588#endif
589}
590#else /* VBOX */
591DECLINLINE(int) lduw_be_p(void *ptr)
592{
593#if defined(__i386__) && !defined(_MSC_VER)
594 int val;
595 asm volatile ("movzwl %1, %0\n"
596 "xchgb %b0, %h0\n"
597 : "=q" (val)
598 : "m" (*(uint16_t *)ptr));
599 return val;
600#else
601 uint8_t *b = (uint8_t *) ptr;
602 return ((b[0] << 8) | b[1]);
603#endif
604}
605#endif
606
607#ifndef VBOX
608static inline int ldsw_be_p(void *ptr)
609{
610#if defined(__i386__)
611 int val;
612 asm volatile ("movzwl %1, %0\n"
613 "xchgb %b0, %h0\n"
614 : "=q" (val)
615 : "m" (*(uint16_t *)ptr));
616 return (int16_t)val;
617#else
618 uint8_t *b = (uint8_t *) ptr;
619 return (int16_t)((b[0] << 8) | b[1]);
620#endif
621}
622#else
623DECLINLINE(int) ldsw_be_p(void *ptr)
624{
625#if defined(__i386__) && !defined(_MSC_VER)
626 int val;
627 asm volatile ("movzwl %1, %0\n"
628 "xchgb %b0, %h0\n"
629 : "=q" (val)
630 : "m" (*(uint16_t *)ptr));
631 return (int16_t)val;
632#else
633 uint8_t *b = (uint8_t *) ptr;
634 return (int16_t)((b[0] << 8) | b[1]);
635#endif
636}
637#endif
638
639#ifndef VBOX
640static inline int ldl_be_p(void *ptr)
641{
642#if defined(__i386__) || defined(__x86_64__)
643 int val;
644 asm volatile ("movl %1, %0\n"
645 "bswap %0\n"
646 : "=r" (val)
647 : "m" (*(uint32_t *)ptr));
648 return val;
649#else
650 uint8_t *b = (uint8_t *) ptr;
651 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
652#endif
653}
654#else
655DECLINLINE(int) ldl_be_p(void *ptr)
656{
657#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
658 int val;
659 asm volatile ("movl %1, %0\n"
660 "bswap %0\n"
661 : "=r" (val)
662 : "m" (*(uint32_t *)ptr));
663 return val;
664#else
665 uint8_t *b = (uint8_t *) ptr;
666 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
667#endif
668}
669#endif
670
671#ifndef VBOX
672static inline uint64_t ldq_be_p(void *ptr)
673#else
674DECLINLINE(uint64_t) ldq_be_p(void *ptr)
675#endif
676{
677 uint32_t a,b;
678 a = ldl_be_p(ptr);
679 b = ldl_be_p((uint8_t*)ptr+4);
680 return (((uint64_t)a<<32)|b);
681}
682
683#ifndef VBOX
684static inline void stw_be_p(void *ptr, int v)
685{
686#if defined(__i386__)
687 asm volatile ("xchgb %b0, %h0\n"
688 "movw %w0, %1\n"
689 : "=q" (v)
690 : "m" (*(uint16_t *)ptr), "0" (v));
691#else
692 uint8_t *d = (uint8_t *) ptr;
693 d[0] = v >> 8;
694 d[1] = v;
695#endif
696}
697#else
698DECLINLINE(void) stw_be_p(void *ptr, int v)
699{
700#if defined(__i386__) && !defined(_MSC_VER)
701 asm volatile ("xchgb %b0, %h0\n"
702 "movw %w0, %1\n"
703 : "=q" (v)
704 : "m" (*(uint16_t *)ptr), "0" (v));
705#else
706 uint8_t *d = (uint8_t *) ptr;
707 d[0] = v >> 8;
708 d[1] = v;
709#endif
710}
711
712#endif /* VBOX */
713
714#ifndef VBOX
715static inline void stl_be_p(void *ptr, int v)
716{
717#if defined(__i386__) || defined(__x86_64__)
718 asm volatile ("bswap %0\n"
719 "movl %0, %1\n"
720 : "=r" (v)
721 : "m" (*(uint32_t *)ptr), "0" (v));
722#else
723 uint8_t *d = (uint8_t *) ptr;
724 d[0] = v >> 24;
725 d[1] = v >> 16;
726 d[2] = v >> 8;
727 d[3] = v;
728#endif
729}
730#else
731DECLINLINE(void) stl_be_p(void *ptr, int v)
732{
733#if !defined(_MSC_VER) && (defined(__i386__) || defined(__x86_64__))
734 asm volatile ("bswap %0\n"
735 "movl %0, %1\n"
736 : "=r" (v)
737 : "m" (*(uint32_t *)ptr), "0" (v));
738#else
739 uint8_t *d = (uint8_t *) ptr;
740 d[0] = v >> 24;
741 d[1] = v >> 16;
742 d[2] = v >> 8;
743 d[3] = v;
744#endif
745}
746#endif /* VBOX */
747
748#ifndef VBOX
749static inline void stq_be_p(void *ptr, uint64_t v)
750#else
751DECLINLINE(void) stq_be_p(void *ptr, uint64_t v)
752#endif
753{
754 stl_be_p(ptr, v >> 32);
755 stl_be_p((uint8_t*)ptr + 4, v);
756}
757
758/* float access */
759#ifndef VBOX
760static inline float32 ldfl_be_p(void *ptr)
761#else
762DECLINLINE(float32) ldfl_be_p(void *ptr)
763#endif
764{
765 union {
766 float32 f;
767 uint32_t i;
768 } u;
769 u.i = ldl_be_p(ptr);
770 return u.f;
771}
772
773#ifndef VBOX
774static inline void stfl_be_p(void *ptr, float32 v)
775#else
776DECLINLINE(void) stfl_be_p(void *ptr, float32 v)
777#endif
778{
779 union {
780 float32 f;
781 uint32_t i;
782 } u;
783 u.f = v;
784 stl_be_p(ptr, u.i);
785}
786
787#ifndef VBOX
788static inline float64 ldfq_be_p(void *ptr)
789#else
790DECLINLINE(float64) ldfq_be_p(void *ptr)
791#endif
792{
793 CPU_DoubleU u;
794 u.l.upper = ldl_be_p(ptr);
795 u.l.lower = ldl_be_p((uint8_t*)ptr + 4);
796 return u.d;
797}
798
799#ifndef VBOX
800static inline void stfq_be_p(void *ptr, float64 v)
801#else
802DECLINLINE(void) stfq_be_p(void *ptr, float64 v)
803#endif
804{
805 CPU_DoubleU u;
806 u.d = v;
807 stl_be_p(ptr, u.l.upper);
808 stl_be_p((uint8_t*)ptr + 4, u.l.lower);
809}
810
811#else
812
813static inline int lduw_be_p(void *ptr)
814{
815 return *(uint16_t *)ptr;
816}
817
818static inline int ldsw_be_p(void *ptr)
819{
820 return *(int16_t *)ptr;
821}
822
823static inline int ldl_be_p(void *ptr)
824{
825 return *(uint32_t *)ptr;
826}
827
828static inline uint64_t ldq_be_p(void *ptr)
829{
830 return *(uint64_t *)ptr;
831}
832
833static inline void stw_be_p(void *ptr, int v)
834{
835 *(uint16_t *)ptr = v;
836}
837
838static inline void stl_be_p(void *ptr, int v)
839{
840 *(uint32_t *)ptr = v;
841}
842
843static inline void stq_be_p(void *ptr, uint64_t v)
844{
845 *(uint64_t *)ptr = v;
846}
847
848/* float access */
849
850static inline float32 ldfl_be_p(void *ptr)
851{
852 return *(float32 *)ptr;
853}
854
855static inline float64 ldfq_be_p(void *ptr)
856{
857 return *(float64 *)ptr;
858}
859
860static inline void stfl_be_p(void *ptr, float32 v)
861{
862 *(float32 *)ptr = v;
863}
864
865static inline void stfq_be_p(void *ptr, float64 v)
866{
867 *(float64 *)ptr = v;
868}
869
870#endif
871
872/* target CPU memory access functions */
873#if defined(TARGET_WORDS_BIGENDIAN)
874#define lduw_p(p) lduw_be_p(p)
875#define ldsw_p(p) ldsw_be_p(p)
876#define ldl_p(p) ldl_be_p(p)
877#define ldq_p(p) ldq_be_p(p)
878#define ldfl_p(p) ldfl_be_p(p)
879#define ldfq_p(p) ldfq_be_p(p)
880#define stw_p(p, v) stw_be_p(p, v)
881#define stl_p(p, v) stl_be_p(p, v)
882#define stq_p(p, v) stq_be_p(p, v)
883#define stfl_p(p, v) stfl_be_p(p, v)
884#define stfq_p(p, v) stfq_be_p(p, v)
885#else
886#define lduw_p(p) lduw_le_p(p)
887#define ldsw_p(p) ldsw_le_p(p)
888#define ldl_p(p) ldl_le_p(p)
889#define ldq_p(p) ldq_le_p(p)
890#define ldfl_p(p) ldfl_le_p(p)
891#define ldfq_p(p) ldfq_le_p(p)
892#define stw_p(p, v) stw_le_p(p, v)
893#define stl_p(p, v) stl_le_p(p, v)
894#define stq_p(p, v) stq_le_p(p, v)
895#define stfl_p(p, v) stfl_le_p(p, v)
896#define stfq_p(p, v) stfq_le_p(p, v)
897#endif
898
899/* MMU memory access macros */
900
901#if defined(CONFIG_USER_ONLY)
902/* On some host systems the guest address space is reserved on the host.
903 * This allows the guest address space to be offset to a convenient location.
904 */
905//#define GUEST_BASE 0x20000000
906#define GUEST_BASE 0
907
908/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
909#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
910#define h2g(x) ((target_ulong)(x - GUEST_BASE))
911
912#define saddr(x) g2h(x)
913#define laddr(x) g2h(x)
914
915#else /* !CONFIG_USER_ONLY */
916/* NOTE: we use double casts if pointers and target_ulong have
917 different sizes */
918#define saddr(x) (uint8_t *)(long)(x)
919#define laddr(x) (uint8_t *)(long)(x)
920#endif
921
922#define ldub_raw(p) ldub_p(laddr((p)))
923#define ldsb_raw(p) ldsb_p(laddr((p)))
924#define lduw_raw(p) lduw_p(laddr((p)))
925#define ldsw_raw(p) ldsw_p(laddr((p)))
926#define ldl_raw(p) ldl_p(laddr((p)))
927#define ldq_raw(p) ldq_p(laddr((p)))
928#define ldfl_raw(p) ldfl_p(laddr((p)))
929#define ldfq_raw(p) ldfq_p(laddr((p)))
930#define stb_raw(p, v) stb_p(saddr((p)), v)
931#define stw_raw(p, v) stw_p(saddr((p)), v)
932#define stl_raw(p, v) stl_p(saddr((p)), v)
933#define stq_raw(p, v) stq_p(saddr((p)), v)
934#define stfl_raw(p, v) stfl_p(saddr((p)), v)
935#define stfq_raw(p, v) stfq_p(saddr((p)), v)
936
937
938#if defined(CONFIG_USER_ONLY)
939
940/* if user mode, no other memory access functions */
941#define ldub(p) ldub_raw(p)
942#define ldsb(p) ldsb_raw(p)
943#define lduw(p) lduw_raw(p)
944#define ldsw(p) ldsw_raw(p)
945#define ldl(p) ldl_raw(p)
946#define ldq(p) ldq_raw(p)
947#define ldfl(p) ldfl_raw(p)
948#define ldfq(p) ldfq_raw(p)
949#define stb(p, v) stb_raw(p, v)
950#define stw(p, v) stw_raw(p, v)
951#define stl(p, v) stl_raw(p, v)
952#define stq(p, v) stq_raw(p, v)
953#define stfl(p, v) stfl_raw(p, v)
954#define stfq(p, v) stfq_raw(p, v)
955
956#define ldub_code(p) ldub_raw(p)
957#define ldsb_code(p) ldsb_raw(p)
958#define lduw_code(p) lduw_raw(p)
959#define ldsw_code(p) ldsw_raw(p)
960#define ldl_code(p) ldl_raw(p)
961
962#define ldub_kernel(p) ldub_raw(p)
963#define ldsb_kernel(p) ldsb_raw(p)
964#define lduw_kernel(p) lduw_raw(p)
965#define ldsw_kernel(p) ldsw_raw(p)
966#define ldl_kernel(p) ldl_raw(p)
967#define ldfl_kernel(p) ldfl_raw(p)
968#define ldfq_kernel(p) ldfq_raw(p)
969#define stb_kernel(p, v) stb_raw(p, v)
970#define stw_kernel(p, v) stw_raw(p, v)
971#define stl_kernel(p, v) stl_raw(p, v)
972#define stq_kernel(p, v) stq_raw(p, v)
973#define stfl_kernel(p, v) stfl_raw(p, v)
974#define stfq_kernel(p, vt) stfq_raw(p, v)
975
976#endif /* defined(CONFIG_USER_ONLY) */
977
978/* page related stuff */
979
980#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
981#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
982#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
983
984/* ??? These should be the larger of unsigned long and target_ulong. */
985extern unsigned long qemu_real_host_page_size;
986extern unsigned long qemu_host_page_bits;
987extern unsigned long qemu_host_page_size;
988extern unsigned long qemu_host_page_mask;
989
990#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
991
992/* same as PROT_xxx */
993#define PAGE_READ 0x0001
994#define PAGE_WRITE 0x0002
995#define PAGE_EXEC 0x0004
996#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
997#define PAGE_VALID 0x0008
998/* original state of the write flag (used when tracking self-modifying
999 code */
1000#define PAGE_WRITE_ORG 0x0010
1001#define PAGE_RESERVED 0x0020
1002
1003void page_dump(FILE *f);
1004int page_get_flags(target_ulong address);
1005void page_set_flags(target_ulong start, target_ulong end, int flags);
1006int page_check_range(target_ulong start, target_ulong len, int flags);
1007void page_unprotect_range(target_ulong data, target_ulong data_size);
1008
1009#define SINGLE_CPU_DEFINES
1010#ifdef SINGLE_CPU_DEFINES
1011
1012#if defined(TARGET_I386)
1013
1014#define CPUState CPUX86State
1015#define cpu_init cpu_x86_init
1016#define cpu_exec cpu_x86_exec
1017#define cpu_gen_code cpu_x86_gen_code
1018#define cpu_signal_handler cpu_x86_signal_handler
1019
1020#elif defined(TARGET_ARM)
1021
1022#define CPUState CPUARMState
1023#define cpu_init cpu_arm_init
1024#define cpu_exec cpu_arm_exec
1025#define cpu_gen_code cpu_arm_gen_code
1026#define cpu_signal_handler cpu_arm_signal_handler
1027
1028#elif defined(TARGET_SPARC)
1029
1030#define CPUState CPUSPARCState
1031#define cpu_init cpu_sparc_init
1032#define cpu_exec cpu_sparc_exec
1033#define cpu_gen_code cpu_sparc_gen_code
1034#define cpu_signal_handler cpu_sparc_signal_handler
1035
1036#elif defined(TARGET_PPC)
1037
1038#define CPUState CPUPPCState
1039#define cpu_init cpu_ppc_init
1040#define cpu_exec cpu_ppc_exec
1041#define cpu_gen_code cpu_ppc_gen_code
1042#define cpu_signal_handler cpu_ppc_signal_handler
1043
1044#elif defined(TARGET_M68K)
1045#define CPUState CPUM68KState
1046#define cpu_init cpu_m68k_init
1047#define cpu_exec cpu_m68k_exec
1048#define cpu_gen_code cpu_m68k_gen_code
1049#define cpu_signal_handler cpu_m68k_signal_handler
1050
1051#elif defined(TARGET_MIPS)
1052#define CPUState CPUMIPSState
1053#define cpu_init cpu_mips_init
1054#define cpu_exec cpu_mips_exec
1055#define cpu_gen_code cpu_mips_gen_code
1056#define cpu_signal_handler cpu_mips_signal_handler
1057
1058#elif defined(TARGET_SH4)
1059#define CPUState CPUSH4State
1060#define cpu_init cpu_sh4_init
1061#define cpu_exec cpu_sh4_exec
1062#define cpu_gen_code cpu_sh4_gen_code
1063#define cpu_signal_handler cpu_sh4_signal_handler
1064
1065#else
1066
1067#error unsupported target CPU
1068
1069#endif
1070
1071#endif /* SINGLE_CPU_DEFINES */
1072
1073void cpu_dump_state(CPUState *env, FILE *f,
1074 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1075 int flags);
1076
1077DECLNORETURN(void) cpu_abort(CPUState *env, const char *fmt, ...);
1078extern CPUState *first_cpu;
1079extern CPUState *cpu_single_env;
1080extern int64_t qemu_icount;
1081extern int use_icount;
1082
1083#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
1084#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
1085#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
1086#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
1087#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
1088#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
1089#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
1090#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
1091#define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
1092#define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
1093
1094#ifdef VBOX
1095/** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
1096#define CPU_INTERRUPT_SINGLE_INSTR 0x0400
1097/** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
1098#define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0800
1099/** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
1100#define CPU_INTERRUPT_RC 0x1000
1101/** Exit current TB to process an external interrupt request (also in op.c!!) */
1102#define CPU_INTERRUPT_EXTERNAL_EXIT 0x2000
1103/** Exit current TB to process an external interrupt request (also in op.c!!) */
1104#define CPU_INTERRUPT_EXTERNAL_HARD 0x4000
1105/** Exit current TB to process an external interrupt request (also in op.c!!) */
1106#define CPU_INTERRUPT_EXTERNAL_TIMER 0x8000
1107/** Exit current TB to process an external interrupt request (also in op.c!!) */
1108#define CPU_INTERRUPT_EXTERNAL_DMA 0x10000
1109#endif /* VBOX */
1110void cpu_interrupt(CPUState *s, int mask);
1111void cpu_reset_interrupt(CPUState *env, int mask);
1112
1113int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type);
1114int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
1115void cpu_watchpoint_remove_all(CPUState *env);
1116int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
1117int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
1118void cpu_breakpoint_remove_all(CPUState *env);
1119
1120#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1121#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1122#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1123
1124void cpu_single_step(CPUState *env, int enabled);
1125void cpu_reset(CPUState *s);
1126
1127/* Return the physical page corresponding to a virtual one. Use it
1128 only for debugging because no protection checks are done. Return -1
1129 if no page found. */
1130target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
1131
1132#define CPU_LOG_TB_OUT_ASM (1 << 0)
1133#define CPU_LOG_TB_IN_ASM (1 << 1)
1134#define CPU_LOG_TB_OP (1 << 2)
1135#define CPU_LOG_TB_OP_OPT (1 << 3)
1136#define CPU_LOG_INT (1 << 4)
1137#define CPU_LOG_EXEC (1 << 5)
1138#define CPU_LOG_PCALL (1 << 6)
1139#define CPU_LOG_IOPORT (1 << 7)
1140#define CPU_LOG_TB_CPU (1 << 8)
1141
1142/* define log items */
1143typedef struct CPULogItem {
1144 int mask;
1145 const char *name;
1146 const char *help;
1147} CPULogItem;
1148
1149extern CPULogItem cpu_log_items[];
1150
1151void cpu_set_log(int log_flags);
1152void cpu_set_log_filename(const char *filename);
1153int cpu_str_to_log_mask(const char *str);
1154
1155/* IO ports API */
1156
1157/* NOTE: as these functions may be even used when there is an isa
1158 brige on non x86 targets, we always defined them */
1159#ifndef NO_CPU_IO_DEFS
1160void cpu_outb(CPUState *env, int addr, int val);
1161void cpu_outw(CPUState *env, int addr, int val);
1162void cpu_outl(CPUState *env, int addr, int val);
1163int cpu_inb(CPUState *env, int addr);
1164int cpu_inw(CPUState *env, int addr);
1165int cpu_inl(CPUState *env, int addr);
1166#endif
1167
1168/* address in the RAM (different from a physical address) */
1169#ifdef USE_KQEMU
1170typedef uint32_t ram_addr_t;
1171#else
1172typedef unsigned long ram_addr_t;
1173#endif
1174
1175/* memory API */
1176
1177#ifndef VBOX
1178extern int phys_ram_size;
1179extern int phys_ram_fd;
1180extern int phys_ram_size;
1181#else /* VBOX */
1182extern RTGCPHYS phys_ram_size;
1183/** This is required for bounds checking the phys_ram_dirty accesses. */
1184extern uint32_t phys_ram_dirty_size;
1185#endif /* VBOX */
1186#if !defined(VBOX)
1187extern uint8_t *phys_ram_base;
1188#endif
1189extern uint8_t *phys_ram_dirty;
1190
1191/* physical memory access */
1192
1193/* MMIO pages are identified by a combination of an IO device index and
1194 3 flags. The ROMD code stores the page ram offset in iotlb entry,
1195 so only a limited number of ids are avaiable. */
1196
1197#define IO_MEM_SHIFT 3
1198#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
1199
1200#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
1201#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
1202#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
1203#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
1204#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
1205#define IO_MEM_RAM_MISSING (5 << IO_MEM_SHIFT) /* used internally, never use directly */
1206#endif
1207
1208/* Acts like a ROM when read and like a device when written. */
1209#define IO_MEM_ROMD (1)
1210#define IO_MEM_SUBPAGE (2)
1211#define IO_MEM_SUBWIDTH (4)
1212
1213/* Flags stored in the low bits of the TLB virtual address. These are
1214 defined so that fast path ram access is all zeros. */
1215/* Zero if TLB entry is valid. */
1216#define TLB_INVALID_MASK (1 << 3)
1217/* Set if TLB entry references a clean RAM page. The iotlb entry will
1218 contain the page physical address. */
1219#define TLB_NOTDIRTY (1 << 4)
1220/* Set if TLB entry is an IO callback. */
1221#define TLB_MMIO (1 << 5)
1222
1223typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
1224typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
1225
1226void cpu_register_physical_memory(target_phys_addr_t start_addr,
1227 ram_addr_t size,
1228 ram_addr_t phys_offset);
1229uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
1230ram_addr_t qemu_ram_alloc(ram_addr_t);
1231void qemu_ram_free(ram_addr_t addr);
1232int cpu_register_io_memory(int io_index,
1233 CPUReadMemoryFunc **mem_read,
1234 CPUWriteMemoryFunc **mem_write,
1235 void *opaque);
1236CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
1237CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
1238
1239void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1240 int len, int is_write);
1241#ifndef VBOX
1242static inline void cpu_physical_memory_read(target_phys_addr_t addr,
1243 uint8_t *buf, int len)
1244#else
1245DECLINLINE(void) cpu_physical_memory_read(target_phys_addr_t addr,
1246 uint8_t *buf, int len)
1247#endif
1248{
1249 cpu_physical_memory_rw(addr, buf, len, 0);
1250}
1251#ifndef VBOX
1252static inline void cpu_physical_memory_write(target_phys_addr_t addr,
1253 const uint8_t *buf, int len)
1254#else
1255DECLINLINE(void) cpu_physical_memory_write(target_phys_addr_t addr,
1256 const uint8_t *buf, int len)
1257#endif
1258{
1259 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
1260}
1261uint32_t ldub_phys(target_phys_addr_t addr);
1262uint32_t lduw_phys(target_phys_addr_t addr);
1263uint32_t ldl_phys(target_phys_addr_t addr);
1264uint64_t ldq_phys(target_phys_addr_t addr);
1265void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
1266void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
1267void stb_phys(target_phys_addr_t addr, uint32_t val);
1268void stw_phys(target_phys_addr_t addr, uint32_t val);
1269void stl_phys(target_phys_addr_t addr, uint32_t val);
1270void stq_phys(target_phys_addr_t addr, uint64_t val);
1271
1272void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1273 const uint8_t *buf, int len);
1274int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1275 uint8_t *buf, int len, int is_write);
1276
1277#define VGA_DIRTY_FLAG 0x01
1278#define CODE_DIRTY_FLAG 0x02
1279#define KQEMU_DIRTY_FLAG 0x04
1280#define MIGRATION_DIRTY_FLAG 0x08
1281
1282/* read dirty bit (return 0 or 1) */
1283#ifndef VBOX
1284static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1285{
1286 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1287}
1288#else
1289DECLINLINE(int) cpu_physical_memory_is_dirty(ram_addr_t addr)
1290{
1291 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1292 {
1293 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1294 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1295 return 0;
1296 }
1297 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1298}
1299#endif
1300
1301#ifndef VBOX
1302static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
1303 int dirty_flags)
1304{
1305 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1306}
1307#else
1308DECLINLINE(int) cpu_physical_memory_get_dirty(ram_addr_t addr,
1309 int dirty_flags)
1310{
1311 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1312 {
1313 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1314 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1315 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */
1316 }
1317 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1318}
1319#endif
1320
1321#ifndef VBOX
1322static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1323{
1324 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1325}
1326#else
1327DECLINLINE(void) cpu_physical_memory_set_dirty(ram_addr_t addr)
1328{
1329 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1330 {
1331 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1332 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1333 return;
1334 }
1335 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1336}
1337#endif
1338
1339void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1340 int dirty_flags);
1341void cpu_tlb_update_dirty(CPUState *env);
1342
1343int cpu_physical_memory_set_dirty_tracking(int enable);
1344
1345int cpu_physical_memory_get_dirty_tracking(void);
1346
1347void dump_exec_info(FILE *f,
1348 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1349
1350/*******************************************/
1351/* host CPU ticks (if available) */
1352
1353#ifdef VBOX
1354
1355DECLINLINE(int64_t) cpu_get_real_ticks(void)
1356{
1357 return ASMReadTSC();
1358}
1359
1360#elif defined(__powerpc__)
1361
1362static inline uint32_t get_tbl(void)
1363{
1364 uint32_t tbl;
1365 asm volatile("mftb %0" : "=r" (tbl));
1366 return tbl;
1367}
1368
1369static inline uint32_t get_tbu(void)
1370{
1371 uint32_t tbl;
1372 asm volatile("mftbu %0" : "=r" (tbl));
1373 return tbl;
1374}
1375
1376static inline int64_t cpu_get_real_ticks(void)
1377{
1378 uint32_t l, h, h1;
1379 /* NOTE: we test if wrapping has occurred */
1380 do {
1381 h = get_tbu();
1382 l = get_tbl();
1383 h1 = get_tbu();
1384 } while (h != h1);
1385 return ((int64_t)h << 32) | l;
1386}
1387
1388#elif defined(__i386__)
1389
1390static inline int64_t cpu_get_real_ticks(void)
1391{
1392 int64_t val;
1393 asm volatile ("rdtsc" : "=A" (val));
1394 return val;
1395}
1396
1397#elif defined(__x86_64__)
1398
1399static inline int64_t cpu_get_real_ticks(void)
1400{
1401 uint32_t low,high;
1402 int64_t val;
1403 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1404 val = high;
1405 val <<= 32;
1406 val |= low;
1407 return val;
1408}
1409
1410#elif defined(__ia64)
1411
1412static inline int64_t cpu_get_real_ticks(void)
1413{
1414 int64_t val;
1415 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1416 return val;
1417}
1418
1419#elif defined(__s390__)
1420
1421static inline int64_t cpu_get_real_ticks(void)
1422{
1423 int64_t val;
1424 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1425 return val;
1426}
1427
1428#elif defined(__sparc_v9__)
1429
1430static inline int64_t cpu_get_real_ticks (void)
1431{
1432#if defined(_LP64)
1433 uint64_t rval;
1434 asm volatile("rd %%tick,%0" : "=r"(rval));
1435 return rval;
1436#else
1437 union {
1438 uint64_t i64;
1439 struct {
1440 uint32_t high;
1441 uint32_t low;
1442 } i32;
1443 } rval;
1444 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1445 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1446 return rval.i64;
1447#endif
1448}
1449#else
1450/* The host CPU doesn't have an easily accessible cycle counter.
1451 Just return a monotonically increasing vlue. This will be totally wrong,
1452 but hopefully better than nothing. */
1453static inline int64_t cpu_get_real_ticks (void)
1454{
1455 static int64_t ticks = 0;
1456 return ticks++;
1457}
1458#endif
1459
1460/* profiling */
1461#ifdef CONFIG_PROFILER
1462static inline int64_t profile_getclock(void)
1463{
1464 return cpu_get_real_ticks();
1465}
1466
1467extern int64_t kqemu_time, kqemu_time_start;
1468extern int64_t qemu_time, qemu_time_start;
1469extern int64_t tlb_flush_time;
1470extern int64_t kqemu_exec_count;
1471extern int64_t dev_time;
1472extern int64_t kqemu_ret_int_count;
1473extern int64_t kqemu_ret_excp_count;
1474extern int64_t kqemu_ret_intr_count;
1475
1476#endif
1477
1478#ifdef VBOX
1479void tb_invalidate_virt(CPUState *env, uint32_t eip);
1480#endif /* VBOX */
1481
1482#endif /* CPU_ALL_H */
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