| 1 | ; $Id: bs3-cpu-weird-1-template.mac 102789 2024-01-08 21:48:55Z vboxsync $
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| 2 | ;; @file
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| 3 | ; BS3Kit - bs3-cpu-weird-1 assembly template.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2007-2023 Oracle and/or its affiliates.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox base platform packages, as
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| 10 | ; available from https://www.virtualbox.org.
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| 11 | ;
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| 12 | ; This program is free software; you can redistribute it and/or
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| 13 | ; modify it under the terms of the GNU General Public License
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| 14 | ; as published by the Free Software Foundation, in version 3 of the
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| 15 | ; License.
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| 16 | ;
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| 17 | ; This program is distributed in the hope that it will be useful, but
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| 18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | ; General Public License for more details.
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| 21 | ;
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| 22 | ; You should have received a copy of the GNU General Public License
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| 23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | ;
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| 25 | ; The contents of this file may alternatively be used under the terms
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| 26 | ; of the Common Development and Distribution License Version 1.0
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| 27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | ; in the VirtualBox distribution, in which case the provisions of the
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| 29 | ; CDDL are applicable instead of those of the GPL.
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| 30 | ;
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| 31 | ; You may elect to license modified versions of this file under the
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| 32 | ; terms and conditions of either the GPL or the CDDL or both.
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| 33 | ;
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| 34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | ;
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| 36 |
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| 37 |
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| 38 | ;*********************************************************************************************************************************
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| 39 | ;* Header Files *
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| 40 | ;*********************************************************************************************************************************
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| 41 | %include "bs3kit-template-header.mac" ; setup environment
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| 42 |
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| 43 |
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| 44 | ;*********************************************************************************************************************************
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| 45 | ;* External Symbols *
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| 46 | ;*********************************************************************************************************************************
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| 47 | TMPL_BEGIN_TEXT
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| 48 |
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| 49 |
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| 50 | ;
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| 51 | ; Test code snippets containing code which differs between 16-bit, 32-bit
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| 52 | ; and 64-bit CPUs modes.
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| 53 | ;
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| 54 | %ifdef BS3_INSTANTIATING_CMN
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| 55 |
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| 56 |
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| 57 | ;
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| 58 | ; Inhibited int 80h.
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| 59 | ;
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| 60 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedInt80, BS3_PBC_NEAR
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| 61 | ; Load SS from stack. This instruction causes fusing.
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| 62 | %if TMPL_BITS != 64
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| 63 | pop ss
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| 64 | %else
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| 65 | mov ss, [rsp]
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| 66 | %endif
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| 67 | ; The ring transition instruction.
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| 68 | BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedInt80_int80), , 0
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| 69 | int 80h
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| 70 | ; We shouldn't get here!
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| 71 | .ud2_again:
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| 72 | ud2
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| 73 | jmp .ud2_again
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| 74 | BS3_PROC_END_CMN bs3CpuWeird1_InhibitedInt80
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| 75 |
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| 76 | ;
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| 77 | ; Inhibited int 3.
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| 78 | ;
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| 79 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedInt3, BS3_PBC_NEAR
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| 80 | ; Load SS from stack. This instruction causes fusing.
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| 81 | %if TMPL_BITS != 64
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| 82 | pop ss
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| 83 | %else
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| 84 | mov ss, [rsp]
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| 85 | %endif
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| 86 | ; The ring transition instruction.
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| 87 | BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedInt3_int3), , 0
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| 88 | int 3
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| 89 | ; We shouldn't get here!
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| 90 | .ud2_again:
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| 91 | ud2
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| 92 | jmp .ud2_again
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| 93 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedInt3_int3) == 2)
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| 94 | BS3_PROC_END_CMN bs3CpuWeird1_InhibitedInt3
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| 95 |
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| 96 |
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| 97 | ;
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| 98 | ; Inhibited int3.
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| 99 | ;
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| 100 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedBp, BS3_PBC_NEAR
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| 101 | ; Load SS from stack. This instruction causes fusing.
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| 102 | %if TMPL_BITS != 64
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| 103 | pop ss
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| 104 | %else
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| 105 | mov ss, [rsp]
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| 106 | %endif
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| 107 | ; The ring transition instruction.
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| 108 | BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedBp_int3), , 0
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| 109 | int3
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| 110 | ; We shouldn't get here!
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| 111 | .ud2_again:
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| 112 | ud2
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| 113 | jmp .ud2_again
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| 114 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedBp_int3) == 1)
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| 115 | BS3_PROC_END_CMN bs3CpuWeird1_InhibitedBp
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| 116 |
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| 117 |
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| 118 | ;
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| 119 | ; PC (IP/EIP) wrapper templates.
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| 120 | ; These will potentially trigger VM exits, except for the benign one.
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| 121 | ;
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| 122 | ; Note! Single instructions as the testcase will shift multibyte variations
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| 123 | ; across the wrap-around boundary and that would cause unpredictable
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| 124 | ; results for the 16-bit if there is more than one instruction.
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| 125 | ;
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| 126 |
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| 127 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign1, BS3_PBC_NEAR
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| 128 | nop
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| 129 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign1
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| 130 |
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| 131 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign2, BS3_PBC_NEAR
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| 132 | xor xDX, xAX
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| 133 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign2
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| 134 |
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| 135 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapCpuId, BS3_PBC_NEAR
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| 136 | cpuid
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| 137 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapCpuId
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| 138 |
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| 139 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapIn80, BS3_PBC_NEAR
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| 140 | in al, 80h
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| 141 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapIn80
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| 142 |
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| 143 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapOut80, BS3_PBC_NEAR
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| 144 | out 80h, al
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| 145 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapOut80
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| 146 |
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| 147 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapSmsw, BS3_PBC_NEAR
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| 148 | smsw si
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| 149 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapSmsw
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| 150 |
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| 151 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdCr0, BS3_PBC_NEAR
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| 152 | mov sAX, cr0
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| 153 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdCr0
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| 154 |
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| 155 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdDr0, BS3_PBC_NEAR
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| 156 | mov sAX, dr0
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| 157 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdDr0
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| 158 |
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| 159 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapWrDr0, BS3_PBC_NEAR
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| 160 | mov dr0, sAX
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| 161 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapWrDr0
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| 162 |
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| 163 |
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| 164 | ;
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| 165 | ; PUSH / POP.
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| 166 | ;
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| 167 |
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| 168 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_xSP_Ud2, BS3_PBC_NEAR
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| 169 | push xSP
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| 170 | .ud2_again:
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| 171 | ud2
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| 172 | jmp .ud2_again
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| 173 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_xSP_Ud2) == 1)
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| 174 | BS3_PROC_END_CMN bs3CpuWeird1_Push_xSP_Ud2
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| 175 |
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| 176 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_xSP_Ud2, BS3_PBC_NEAR
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| 177 | pop xSP
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| 178 | .ud2_again:
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| 179 | ud2
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| 180 | jmp .ud2_again
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| 181 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_xSP_Ud2) == 1)
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| 182 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_xSP_Ud2
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| 183 |
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| 184 |
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| 185 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_xSP_Ud2, BS3_PBC_NEAR
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| 186 | db 066h
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| 187 | push xSP
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| 188 | .ud2_again:
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| 189 | ud2
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| 190 | jmp .ud2_again
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| 191 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_xSP_Ud2) == 2)
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| 192 | BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_xSP_Ud2
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| 193 |
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| 194 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_xSP_Ud2, BS3_PBC_NEAR
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| 195 | db 066h
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| 196 | pop xSP
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| 197 | .ud2_again:
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| 198 | ud2
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| 199 | jmp .ud2_again
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| 200 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_xSP_Ud2) == 2)
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| 201 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_xSP_Ud2
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| 202 |
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| 203 |
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| 204 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_xBX_Ud2, BS3_PBC_NEAR
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| 205 | db 066h
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| 206 | push xBX
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| 207 | .ud2_again:
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| 208 | ud2
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| 209 | jmp .ud2_again
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| 210 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_xBX_Ud2) == 2)
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| 211 | BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_xBX_Ud2
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| 212 |
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| 213 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_xBX_Ud2, BS3_PBC_NEAR
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| 214 | db 066h
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| 215 | pop xBX
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| 216 | .ud2_again:
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| 217 | ud2
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| 218 | jmp .ud2_again
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| 219 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_xBX_Ud2) == 2)
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| 220 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_xBX_Ud2
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| 221 |
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| 222 |
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| 223 | ;
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| 224 | ; PUSH / POP SREG.
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| 225 | ;
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| 226 |
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| 227 | %ifndef DEFINED_DO_PUSH_POP_MACROS
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| 228 | %define DEFINED_DO_PUSH_POP_MACROS
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| 229 | %macro DoPushSeg 2
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| 230 |
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| 231 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
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| 232 | push %1
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| 233 | .ud2_again:
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| 234 | ud2
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| 235 | jmp .ud2_again
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| 236 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_ %+ %1 %+ _Ud2) == %2)
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| 237 | BS3_PROC_END_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2
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| 238 |
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| 239 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
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| 240 | db 066h
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| 241 | push %1
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| 242 | .ud2_again:
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| 243 | ud2
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| 244 | jmp .ud2_again
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| 245 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2) == (%2 + 1))
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| 246 | BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2
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| 247 |
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| 248 | %endmacro ; DoPushSeg
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| 249 |
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| 250 | %macro DoPopSeg 2
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| 251 |
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| 252 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
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| 253 | pop %1
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| 254 | .ud2_again:
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| 255 | ud2
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| 256 | jmp .ud2_again
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| 257 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2) == %2)
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| 258 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2
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| 259 |
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| 260 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
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| 261 | db 066h
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| 262 | pop %1
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| 263 | .ud2_again:
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| 264 | ud2
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| 265 | jmp .ud2_again
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| 266 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2) == (%2 + 1))
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| 267 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2
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| 268 |
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| 269 | %endmacro ; DoPopSeg
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| 270 | %endif ; !DEFINED_DO_PUSH_POP_MACROS
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| 271 |
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| 272 | DoPushSeg fs, 2
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| 273 | DoPopSeg fs, 2
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| 274 | DoPushSeg gs, 2
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| 275 | DoPopSeg gs, 2
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| 276 | %if TMPL_BITS == 32 || TMPL_BITS == 16
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| 277 | DoPushSeg es, 1
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| 278 | DoPopSeg es, 1
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| 279 | DoPushSeg ds, 1
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| 280 | DoPopSeg ds, 1
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| 281 | DoPushSeg ss, 1
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| 282 | DoPopSeg ss, 1
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| 283 | DoPushSeg cs, 1
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| 284 | %endif
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| 285 |
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| 286 | %endif ; BS3_INSTANTIATING_CMN
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| 287 |
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| 288 | %include "bs3kit-template-footer.mac" ; reset environment
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| 289 |
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