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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 103374

Last change on this file since 103374 was 103374, checked in by vboxsync, 4 months ago
VMM/PGM,DBGF,GIC: Parfait pointed out some potential NULL pointer use here and there. bugref:3409
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 152.7 KB

Line
1	/* $Id: PGMAll.cpp 103374 2024-02-14 22:10:00Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_PGM
33	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
34	#include <VBox/vmm/pgm.h>
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/selm.h>
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/iom.h>
39	#include <VBox/sup.h>
40	#include <VBox/vmm/mm.h>
41	#include <VBox/vmm/stam.h>
42	#include <VBox/vmm/trpm.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/hm_vmx.h>
46	#include "PGMInternal.h"
47	#include <VBox/vmm/vmcc.h>
48	#include "PGMInline.h"
49	#include <iprt/assert.h>
50	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
51	# include <iprt/asm-amd64-x86.h>
52	#endif
53	#include <iprt/string.h>
54	#include <VBox/log.h>
55	#include <VBox/param.h>
56	#include <VBox/err.h>
57
58
59	/*********************************************************************************************************************************
60	* Internal Functions *
61	*********************************************************************************************************************************/
62	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
63	DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
64	DECLINLINE(int) pgmGstMapCr3(PVMCPUCC pVCpu, RTGCPHYS GCPhysCr3, PRTHCPTR pHCPtrGuestCr3);
65	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
66	static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
67	PPGMPTWALKGST pGstWalk);
68	static int pgmGstSlatTranslateCr3(PVMCPUCC pVCpu, uint64_t uCr3, PRTGCPHYS pGCPhysCr3);
69	static int pgmShwGetNestedEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPhysNested, PEPTPDPT ppPdpt, PEPTPD ppPD,
70	PPGMPTWALKGST pGstWalkAll);
71	#endif
72	static int pgmShwSyncLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
73	static int pgmShwGetEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
74	#ifdef PGM_WITH_PAGE_ZEROING_DETECTION
75	static bool pgmHandlePageZeroingCode(PVMCPUCC pVCpu, PCPUMCTX pCtx);
76	#endif
77
78
79	/*
80	* Second level transation - EPT.
81	*/
82	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
83	# define PGM_SLAT_TYPE PGM_SLAT_TYPE_EPT
84	# include "PGMSlatDefs.h"
85	# include "PGMAllGstSlatEpt.cpp.h"
86	# undef PGM_SLAT_TYPE
87	#endif
88
89
90	/*
91	* Shadow - 32-bit mode
92	*/
93	#define PGM_SHW_TYPE PGM_TYPE_32BIT
94	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
95	#include "PGMAllShw.h"
96
97	/* Guest - real mode */
98	#define PGM_GST_TYPE PGM_TYPE_REAL
99	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
100	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
101	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
102	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
103	#include "PGMGstDefs.h"
104	#include "PGMAllGst.h"
105	#include "PGMAllBth.h"
106	#undef BTH_PGMPOOLKIND_PT_FOR_PT
107	#undef BTH_PGMPOOLKIND_ROOT
108	#undef PGM_BTH_NAME
109	#undef PGM_GST_TYPE
110	#undef PGM_GST_NAME
111
112	/* Guest - protected mode */
113	#define PGM_GST_TYPE PGM_TYPE_PROT
114	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
115	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
116	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
117	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
118	#include "PGMGstDefs.h"
119	#include "PGMAllGst.h"
120	#include "PGMAllBth.h"
121	#undef BTH_PGMPOOLKIND_PT_FOR_PT
122	#undef BTH_PGMPOOLKIND_ROOT
123	#undef PGM_BTH_NAME
124	#undef PGM_GST_TYPE
125	#undef PGM_GST_NAME
126
127	/* Guest - 32-bit mode */
128	#define PGM_GST_TYPE PGM_TYPE_32BIT
129	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
130	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
131	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
132	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
133	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
134	#include "PGMGstDefs.h"
135	#include "PGMAllGst.h"
136	#include "PGMAllBth.h"
137	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
138	#undef BTH_PGMPOOLKIND_PT_FOR_PT
139	#undef BTH_PGMPOOLKIND_ROOT
140	#undef PGM_BTH_NAME
141	#undef PGM_GST_TYPE
142	#undef PGM_GST_NAME
143
144	#undef PGM_SHW_TYPE
145	#undef PGM_SHW_NAME
146
147
148	/*
149	* Shadow - PAE mode
150	*/
151	#define PGM_SHW_TYPE PGM_TYPE_PAE
152	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
153	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
154	#include "PGMAllShw.h"
155
156	/* Guest - real mode */
157	#define PGM_GST_TYPE PGM_TYPE_REAL
158	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162	#include "PGMGstDefs.h"
163	#include "PGMAllBth.h"
164	#undef BTH_PGMPOOLKIND_PT_FOR_PT
165	#undef BTH_PGMPOOLKIND_ROOT
166	#undef PGM_BTH_NAME
167	#undef PGM_GST_TYPE
168	#undef PGM_GST_NAME
169
170	/* Guest - protected mode */
171	#define PGM_GST_TYPE PGM_TYPE_PROT
172	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
173	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
174	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
175	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
176	#include "PGMGstDefs.h"
177	#include "PGMAllBth.h"
178	#undef BTH_PGMPOOLKIND_PT_FOR_PT
179	#undef BTH_PGMPOOLKIND_ROOT
180	#undef PGM_BTH_NAME
181	#undef PGM_GST_TYPE
182	#undef PGM_GST_NAME
183
184	/* Guest - 32-bit mode */
185	#define PGM_GST_TYPE PGM_TYPE_32BIT
186	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
187	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
188	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
189	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
190	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
191	#include "PGMGstDefs.h"
192	#include "PGMAllBth.h"
193	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
194	#undef BTH_PGMPOOLKIND_PT_FOR_PT
195	#undef BTH_PGMPOOLKIND_ROOT
196	#undef PGM_BTH_NAME
197	#undef PGM_GST_TYPE
198	#undef PGM_GST_NAME
199
200
201	/* Guest - PAE mode */
202	#define PGM_GST_TYPE PGM_TYPE_PAE
203	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
204	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
205	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
206	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
207	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
208	#include "PGMGstDefs.h"
209	#include "PGMAllGst.h"
210	#include "PGMAllBth.h"
211	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
212	#undef BTH_PGMPOOLKIND_PT_FOR_PT
213	#undef BTH_PGMPOOLKIND_ROOT
214	#undef PGM_BTH_NAME
215	#undef PGM_GST_TYPE
216	#undef PGM_GST_NAME
217
218	#undef PGM_SHW_TYPE
219	#undef PGM_SHW_NAME
220
221
222	/*
223	* Shadow - AMD64 mode
224	*/
225	#define PGM_SHW_TYPE PGM_TYPE_AMD64
226	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
227	#include "PGMAllShw.h"
228
229	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
230	/** @todo retire this hack. */
231	#define PGM_GST_TYPE PGM_TYPE_PROT
232	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
233	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
234	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
235	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
236	#include "PGMGstDefs.h"
237	#include "PGMAllBth.h"
238	#undef BTH_PGMPOOLKIND_PT_FOR_PT
239	#undef BTH_PGMPOOLKIND_ROOT
240	#undef PGM_BTH_NAME
241	#undef PGM_GST_TYPE
242	#undef PGM_GST_NAME
243
244	#ifdef VBOX_WITH_64_BITS_GUESTS
245	/* Guest - AMD64 mode */
246	# define PGM_GST_TYPE PGM_TYPE_AMD64
247	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
248	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
249	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
250	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
251	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
252	# include "PGMGstDefs.h"
253	# include "PGMAllGst.h"
254	# include "PGMAllBth.h"
255	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
256	# undef BTH_PGMPOOLKIND_PT_FOR_PT
257	# undef BTH_PGMPOOLKIND_ROOT
258	# undef PGM_BTH_NAME
259	# undef PGM_GST_TYPE
260	# undef PGM_GST_NAME
261	#endif /* VBOX_WITH_64_BITS_GUESTS */
262
263	#undef PGM_SHW_TYPE
264	#undef PGM_SHW_NAME
265
266
267	/*
268	* Shadow - 32-bit nested paging mode.
269	*/
270	#define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
271	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
272	#include "PGMAllShw.h"
273
274	/* Guest - real mode */
275	#define PGM_GST_TYPE PGM_TYPE_REAL
276	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
277	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
278	#include "PGMGstDefs.h"
279	#include "PGMAllBth.h"
280	#undef PGM_BTH_NAME
281	#undef PGM_GST_TYPE
282	#undef PGM_GST_NAME
283
284	/* Guest - protected mode */
285	#define PGM_GST_TYPE PGM_TYPE_PROT
286	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
287	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
288	#include "PGMGstDefs.h"
289	#include "PGMAllBth.h"
290	#undef PGM_BTH_NAME
291	#undef PGM_GST_TYPE
292	#undef PGM_GST_NAME
293
294	/* Guest - 32-bit mode */
295	#define PGM_GST_TYPE PGM_TYPE_32BIT
296	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
297	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
298	#include "PGMGstDefs.h"
299	#include "PGMAllBth.h"
300	#undef PGM_BTH_NAME
301	#undef PGM_GST_TYPE
302	#undef PGM_GST_NAME
303
304	/* Guest - PAE mode */
305	#define PGM_GST_TYPE PGM_TYPE_PAE
306	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
307	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
308	#include "PGMGstDefs.h"
309	#include "PGMAllBth.h"
310	#undef PGM_BTH_NAME
311	#undef PGM_GST_TYPE
312	#undef PGM_GST_NAME
313
314	#ifdef VBOX_WITH_64_BITS_GUESTS
315	/* Guest - AMD64 mode */
316	# define PGM_GST_TYPE PGM_TYPE_AMD64
317	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
318	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
319	# include "PGMGstDefs.h"
320	# include "PGMAllBth.h"
321	# undef PGM_BTH_NAME
322	# undef PGM_GST_TYPE
323	# undef PGM_GST_NAME
324	#endif /* VBOX_WITH_64_BITS_GUESTS */
325
326	#undef PGM_SHW_TYPE
327	#undef PGM_SHW_NAME
328
329
330	/*
331	* Shadow - PAE nested paging mode.
332	*/
333	#define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
334	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
335	#include "PGMAllShw.h"
336
337	/* Guest - real mode */
338	#define PGM_GST_TYPE PGM_TYPE_REAL
339	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
340	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
341	#include "PGMGstDefs.h"
342	#include "PGMAllBth.h"
343	#undef PGM_BTH_NAME
344	#undef PGM_GST_TYPE
345	#undef PGM_GST_NAME
346
347	/* Guest - protected mode */
348	#define PGM_GST_TYPE PGM_TYPE_PROT
349	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
350	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
351	#include "PGMGstDefs.h"
352	#include "PGMAllBth.h"
353	#undef PGM_BTH_NAME
354	#undef PGM_GST_TYPE
355	#undef PGM_GST_NAME
356
357	/* Guest - 32-bit mode */
358	#define PGM_GST_TYPE PGM_TYPE_32BIT
359	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
360	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
361	#include "PGMGstDefs.h"
362	#include "PGMAllBth.h"
363	#undef PGM_BTH_NAME
364	#undef PGM_GST_TYPE
365	#undef PGM_GST_NAME
366
367	/* Guest - PAE mode */
368	#define PGM_GST_TYPE PGM_TYPE_PAE
369	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
370	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
371	#include "PGMGstDefs.h"
372	#include "PGMAllBth.h"
373	#undef PGM_BTH_NAME
374	#undef PGM_GST_TYPE
375	#undef PGM_GST_NAME
376
377	#ifdef VBOX_WITH_64_BITS_GUESTS
378	/* Guest - AMD64 mode */
379	# define PGM_GST_TYPE PGM_TYPE_AMD64
380	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
381	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
382	# include "PGMGstDefs.h"
383	# include "PGMAllBth.h"
384	# undef PGM_BTH_NAME
385	# undef PGM_GST_TYPE
386	# undef PGM_GST_NAME
387	#endif /* VBOX_WITH_64_BITS_GUESTS */
388
389	#undef PGM_SHW_TYPE
390	#undef PGM_SHW_NAME
391
392
393	/*
394	* Shadow - AMD64 nested paging mode.
395	*/
396	#define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
397	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
398	#include "PGMAllShw.h"
399
400	/* Guest - real mode */
401	#define PGM_GST_TYPE PGM_TYPE_REAL
402	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
403	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
404	#include "PGMGstDefs.h"
405	#include "PGMAllBth.h"
406	#undef PGM_BTH_NAME
407	#undef PGM_GST_TYPE
408	#undef PGM_GST_NAME
409
410	/* Guest - protected mode */
411	#define PGM_GST_TYPE PGM_TYPE_PROT
412	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
413	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
414	#include "PGMGstDefs.h"
415	#include "PGMAllBth.h"
416	#undef PGM_BTH_NAME
417	#undef PGM_GST_TYPE
418	#undef PGM_GST_NAME
419
420	/* Guest - 32-bit mode */
421	#define PGM_GST_TYPE PGM_TYPE_32BIT
422	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
423	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
424	#include "PGMGstDefs.h"
425	#include "PGMAllBth.h"
426	#undef PGM_BTH_NAME
427	#undef PGM_GST_TYPE
428	#undef PGM_GST_NAME
429
430	/* Guest - PAE mode */
431	#define PGM_GST_TYPE PGM_TYPE_PAE
432	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
433	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
434	#include "PGMGstDefs.h"
435	#include "PGMAllBth.h"
436	#undef PGM_BTH_NAME
437	#undef PGM_GST_TYPE
438	#undef PGM_GST_NAME
439
440	#ifdef VBOX_WITH_64_BITS_GUESTS
441	/* Guest - AMD64 mode */
442	# define PGM_GST_TYPE PGM_TYPE_AMD64
443	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
444	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
445	# include "PGMGstDefs.h"
446	# include "PGMAllBth.h"
447	# undef PGM_BTH_NAME
448	# undef PGM_GST_TYPE
449	# undef PGM_GST_NAME
450	#endif /* VBOX_WITH_64_BITS_GUESTS */
451
452	#undef PGM_SHW_TYPE
453	#undef PGM_SHW_NAME
454
455
456	/*
457	* Shadow - EPT.
458	*/
459	#define PGM_SHW_TYPE PGM_TYPE_EPT
460	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
461	#include "PGMAllShw.h"
462
463	/* Guest - real mode */
464	#define PGM_GST_TYPE PGM_TYPE_REAL
465	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
466	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
467	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
468	#include "PGMGstDefs.h"
469	#include "PGMAllBth.h"
470	#undef BTH_PGMPOOLKIND_PT_FOR_PT
471	#undef PGM_BTH_NAME
472	#undef PGM_GST_TYPE
473	#undef PGM_GST_NAME
474
475	/* Guest - protected mode */
476	#define PGM_GST_TYPE PGM_TYPE_PROT
477	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
478	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
479	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
480	#include "PGMGstDefs.h"
481	#include "PGMAllBth.h"
482	#undef BTH_PGMPOOLKIND_PT_FOR_PT
483	#undef PGM_BTH_NAME
484	#undef PGM_GST_TYPE
485	#undef PGM_GST_NAME
486
487	/* Guest - 32-bit mode */
488	#define PGM_GST_TYPE PGM_TYPE_32BIT
489	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
490	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
491	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
492	#include "PGMGstDefs.h"
493	#include "PGMAllBth.h"
494	#undef BTH_PGMPOOLKIND_PT_FOR_PT
495	#undef PGM_BTH_NAME
496	#undef PGM_GST_TYPE
497	#undef PGM_GST_NAME
498
499	/* Guest - PAE mode */
500	#define PGM_GST_TYPE PGM_TYPE_PAE
501	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
502	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
503	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
504	#include "PGMGstDefs.h"
505	#include "PGMAllBth.h"
506	#undef BTH_PGMPOOLKIND_PT_FOR_PT
507	#undef PGM_BTH_NAME
508	#undef PGM_GST_TYPE
509	#undef PGM_GST_NAME
510
511	#ifdef VBOX_WITH_64_BITS_GUESTS
512	/* Guest - AMD64 mode */
513	# define PGM_GST_TYPE PGM_TYPE_AMD64
514	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
515	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
516	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
517	# include "PGMGstDefs.h"
518	# include "PGMAllBth.h"
519	# undef BTH_PGMPOOLKIND_PT_FOR_PT
520	# undef PGM_BTH_NAME
521	# undef PGM_GST_TYPE
522	# undef PGM_GST_NAME
523	#endif /* VBOX_WITH_64_BITS_GUESTS */
524
525	#undef PGM_SHW_TYPE
526	#undef PGM_SHW_NAME
527
528
529	/*
530	* Shadow - NEM / None.
531	*/
532	#define PGM_SHW_TYPE PGM_TYPE_NONE
533	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NONE(name)
534	#include "PGMAllShw.h"
535
536	/* Guest - real mode */
537	#define PGM_GST_TYPE PGM_TYPE_REAL
538	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
539	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_REAL(name)
540	#include "PGMGstDefs.h"
541	#include "PGMAllBth.h"
542	#undef PGM_BTH_NAME
543	#undef PGM_GST_TYPE
544	#undef PGM_GST_NAME
545
546	/* Guest - protected mode */
547	#define PGM_GST_TYPE PGM_TYPE_PROT
548	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
549	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PROT(name)
550	#include "PGMGstDefs.h"
551	#include "PGMAllBth.h"
552	#undef PGM_BTH_NAME
553	#undef PGM_GST_TYPE
554	#undef PGM_GST_NAME
555
556	/* Guest - 32-bit mode */
557	#define PGM_GST_TYPE PGM_TYPE_32BIT
558	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
559	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_32BIT(name)
560	#include "PGMGstDefs.h"
561	#include "PGMAllBth.h"
562	#undef PGM_BTH_NAME
563	#undef PGM_GST_TYPE
564	#undef PGM_GST_NAME
565
566	/* Guest - PAE mode */
567	#define PGM_GST_TYPE PGM_TYPE_PAE
568	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
569	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PAE(name)
570	#include "PGMGstDefs.h"
571	#include "PGMAllBth.h"
572	#undef PGM_BTH_NAME
573	#undef PGM_GST_TYPE
574	#undef PGM_GST_NAME
575
576	#ifdef VBOX_WITH_64_BITS_GUESTS
577	/* Guest - AMD64 mode */
578	# define PGM_GST_TYPE PGM_TYPE_AMD64
579	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
580	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_AMD64(name)
581	# include "PGMGstDefs.h"
582	# include "PGMAllBth.h"
583	# undef PGM_BTH_NAME
584	# undef PGM_GST_TYPE
585	# undef PGM_GST_NAME
586	#endif /* VBOX_WITH_64_BITS_GUESTS */
587
588	#undef PGM_SHW_TYPE
589	#undef PGM_SHW_NAME
590
591
592
593	/**
594	* Guest mode data array.
595	*/
596	PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE] =
597	{
598	{ UINT32_MAX, NULL, NULL, NULL, NULL }, /* 0 */
599	{
600	PGM_TYPE_REAL,
601	PGM_GST_NAME_REAL(GetPage),
602	PGM_GST_NAME_REAL(ModifyPage),
603	PGM_GST_NAME_REAL(Enter),
604	PGM_GST_NAME_REAL(Exit),
605	#ifdef IN_RING3
606	PGM_GST_NAME_REAL(Relocate),
607	#endif
608	},
609	{
610	PGM_TYPE_PROT,
611	PGM_GST_NAME_PROT(GetPage),
612	PGM_GST_NAME_PROT(ModifyPage),
613	PGM_GST_NAME_PROT(Enter),
614	PGM_GST_NAME_PROT(Exit),
615	#ifdef IN_RING3
616	PGM_GST_NAME_PROT(Relocate),
617	#endif
618	},
619	{
620	PGM_TYPE_32BIT,
621	PGM_GST_NAME_32BIT(GetPage),
622	PGM_GST_NAME_32BIT(ModifyPage),
623	PGM_GST_NAME_32BIT(Enter),
624	PGM_GST_NAME_32BIT(Exit),
625	#ifdef IN_RING3
626	PGM_GST_NAME_32BIT(Relocate),
627	#endif
628	},
629	{
630	PGM_TYPE_PAE,
631	PGM_GST_NAME_PAE(GetPage),
632	PGM_GST_NAME_PAE(ModifyPage),
633	PGM_GST_NAME_PAE(Enter),
634	PGM_GST_NAME_PAE(Exit),
635	#ifdef IN_RING3
636	PGM_GST_NAME_PAE(Relocate),
637	#endif
638	},
639	#ifdef VBOX_WITH_64_BITS_GUESTS
640	{
641	PGM_TYPE_AMD64,
642	PGM_GST_NAME_AMD64(GetPage),
643	PGM_GST_NAME_AMD64(ModifyPage),
644	PGM_GST_NAME_AMD64(Enter),
645	PGM_GST_NAME_AMD64(Exit),
646	# ifdef IN_RING3
647	PGM_GST_NAME_AMD64(Relocate),
648	# endif
649	},
650	#endif
651	};
652
653
654	/**
655	* The shadow mode data array.
656	*/
657	PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE] =
658	{
659	{ UINT8_MAX, NULL, NULL, NULL, NULL }, /* 0 */
660	{ UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_REAL */
661	{ UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_PROT */
662	{
663	PGM_TYPE_32BIT,
664	PGM_SHW_NAME_32BIT(GetPage),
665	PGM_SHW_NAME_32BIT(ModifyPage),
666	PGM_SHW_NAME_32BIT(Enter),
667	PGM_SHW_NAME_32BIT(Exit),
668	#ifdef IN_RING3
669	PGM_SHW_NAME_32BIT(Relocate),
670	#endif
671	},
672	{
673	PGM_TYPE_PAE,
674	PGM_SHW_NAME_PAE(GetPage),
675	PGM_SHW_NAME_PAE(ModifyPage),
676	PGM_SHW_NAME_PAE(Enter),
677	PGM_SHW_NAME_PAE(Exit),
678	#ifdef IN_RING3
679	PGM_SHW_NAME_PAE(Relocate),
680	#endif
681	},
682	{
683	PGM_TYPE_AMD64,
684	PGM_SHW_NAME_AMD64(GetPage),
685	PGM_SHW_NAME_AMD64(ModifyPage),
686	PGM_SHW_NAME_AMD64(Enter),
687	PGM_SHW_NAME_AMD64(Exit),
688	#ifdef IN_RING3
689	PGM_SHW_NAME_AMD64(Relocate),
690	#endif
691	},
692	{
693	PGM_TYPE_NESTED_32BIT,
694	PGM_SHW_NAME_NESTED_32BIT(GetPage),
695	PGM_SHW_NAME_NESTED_32BIT(ModifyPage),
696	PGM_SHW_NAME_NESTED_32BIT(Enter),
697	PGM_SHW_NAME_NESTED_32BIT(Exit),
698	#ifdef IN_RING3
699	PGM_SHW_NAME_NESTED_32BIT(Relocate),
700	#endif
701	},
702	{
703	PGM_TYPE_NESTED_PAE,
704	PGM_SHW_NAME_NESTED_PAE(GetPage),
705	PGM_SHW_NAME_NESTED_PAE(ModifyPage),
706	PGM_SHW_NAME_NESTED_PAE(Enter),
707	PGM_SHW_NAME_NESTED_PAE(Exit),
708	#ifdef IN_RING3
709	PGM_SHW_NAME_NESTED_PAE(Relocate),
710	#endif
711	},
712	{
713	PGM_TYPE_NESTED_AMD64,
714	PGM_SHW_NAME_NESTED_AMD64(GetPage),
715	PGM_SHW_NAME_NESTED_AMD64(ModifyPage),
716	PGM_SHW_NAME_NESTED_AMD64(Enter),
717	PGM_SHW_NAME_NESTED_AMD64(Exit),
718	#ifdef IN_RING3
719	PGM_SHW_NAME_NESTED_AMD64(Relocate),
720	#endif
721	},
722	{
723	PGM_TYPE_EPT,
724	PGM_SHW_NAME_EPT(GetPage),
725	PGM_SHW_NAME_EPT(ModifyPage),
726	PGM_SHW_NAME_EPT(Enter),
727	PGM_SHW_NAME_EPT(Exit),
728	#ifdef IN_RING3
729	PGM_SHW_NAME_EPT(Relocate),
730	#endif
731	},
732	{
733	PGM_TYPE_NONE,
734	PGM_SHW_NAME_NONE(GetPage),
735	PGM_SHW_NAME_NONE(ModifyPage),
736	PGM_SHW_NAME_NONE(Enter),
737	PGM_SHW_NAME_NONE(Exit),
738	#ifdef IN_RING3
739	PGM_SHW_NAME_NONE(Relocate),
740	#endif
741	},
742	};
743
744
745	/**
746	* The guest+shadow mode data array.
747	*/
748	PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE] =
749	{
750	#if !defined(IN_RING3) && !defined(VBOX_STRICT)
751	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
752	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
753	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(NestedTrap0eHandler) }
754
755	#elif !defined(IN_RING3) && defined(VBOX_STRICT)
756	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
757	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
758	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(NestedTrap0eHandler), Nm(AssertCR3) }
759
760	#elif defined(IN_RING3) && !defined(VBOX_STRICT)
761	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL }
762	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
763	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), }
764
765	#elif defined(IN_RING3) && defined(VBOX_STRICT)
766	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
767	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
768	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(AssertCR3) }
769
770	#else
771	# error "Misconfig."
772	#endif
773
774	/* 32-bit shadow paging mode: */
775	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
776	PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_32BIT_REAL),
777	PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_32BIT_PROT),
778	PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_32BIT_32BIT),
779	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_PAE - illegal */
780	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_AMD64 - illegal */
781	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
782	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_PAE - illegal */
783	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
784	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_EPT - illegal */
785	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NONE - illegal */
786
787	/* PAE shadow paging mode: */
788	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
789	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_PAE_REAL),
790	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_PAE_PROT),
791	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_PAE_32BIT),
792	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_PAE_PAE),
793	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_AMD64 - illegal */
794	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_32BIT - illegal */
795	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_PAE - illegal */
796	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
797	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_EPT - illegal */
798	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NONE - illegal */
799
800	/* AMD64 shadow paging mode: */
801	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
802	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_AMD64_REAL),
803	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_AMD64_PROT),
804	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_AMD64_32BIT),
805	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_AMD64_PAE),
806	#ifdef VBOX_WITH_64_BITS_GUESTS
807	PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_AMD64_AMD64),
808	#else
809	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_AMD64 - illegal */
810	#endif
811	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
812	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_PAE - illegal */
813	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
814	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_EPT - illegal */
815	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NONE - illegal */
816
817	/* 32-bit nested paging mode: */
818	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
819	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_32BIT_REAL),
820	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_32BIT_PROT),
821	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_32BIT_32BIT),
822	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_32BIT_PAE),
823	#ifdef VBOX_WITH_64_BITS_GUESTS
824	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_32BIT_AMD64),
825	#else
826	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64 - illegal */
827	#endif
828	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
829	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_PAE - illegal */
830	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
831	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_EPT - illegal */
832	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NONE - illegal */
833
834	/* PAE nested paging mode: */
835	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
836	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_PAE_REAL),
837	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_PAE_PROT),
838	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_PAE_32BIT),
839	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_PAE_PAE),
840	#ifdef VBOX_WITH_64_BITS_GUESTS
841	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_PAE_AMD64),
842	#else
843	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64 - illegal */
844	#endif
845	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_32BIT - illegal */
846	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_PAE - illegal */
847	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
848	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_EPT - illegal */
849	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NONE - illegal */
850
851	/* AMD64 nested paging mode: */
852	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
853	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_AMD64_REAL),
854	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_AMD64_PROT),
855	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_AMD64_32BIT),
856	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_AMD64_PAE),
857	#ifdef VBOX_WITH_64_BITS_GUESTS
858	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_AMD64_AMD64),
859	#else
860	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64 - illegal */
861	#endif
862	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
863	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_PAE - illegal */
864	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
865	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_EPT - illegal */
866	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NONE - illegal */
867
868	/* EPT nested paging mode: */
869	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
870	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
871	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
872	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
873	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
874	#ifdef VBOX_WITH_64_BITS_GUESTS
875	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
876	#else
877	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_AMD64 - illegal */
878	#endif
879	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_32BIT - illegal */
880	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_PAE - illegal */
881	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_AMD64 - illegal */
882	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_EPT - illegal */
883	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NONE - illegal */
884
885	/* NONE / NEM: */
886	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
887	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
888	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
889	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
890	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
891	#ifdef VBOX_WITH_64_BITS_GUESTS
892	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
893	#else
894	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_AMD64 - illegal */
895	#endif
896	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_32BIT - illegal */
897	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_PAE - illegal */
898	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_AMD64 - illegal */
899	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_EPT - illegal */
900	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NONE - illegal */
901
902
903	#undef PGMMODEDATABTH_ENTRY
904	#undef PGMMODEDATABTH_NULL_ENTRY
905	};
906
907
908	/** Mask array used by pgmGetCr3MaskForMode.
909	* X86_CR3_AMD64_PAGE_MASK is used for modes that doesn't have a CR3 or EPTP. */
910	static uint64_t const g_auCr3MaskForMode[PGMMODE_MAX] =
911	{
912	/* [PGMMODE_INVALID] = */ X86_CR3_AMD64_PAGE_MASK,
913	/* [PGMMODE_REAL] = */ X86_CR3_AMD64_PAGE_MASK,
914	/* [PGMMODE_PROTECTED] = */ X86_CR3_AMD64_PAGE_MASK,
915	/* [PGMMODE_32_BIT] = */ X86_CR3_PAGE_MASK,
916	/* [PGMMODE_PAE] = */ X86_CR3_PAE_PAGE_MASK,
917	/* [PGMMODE_PAE_NX] = */ X86_CR3_PAE_PAGE_MASK,
918	/* [PGMMODE_AMD64] = */ X86_CR3_AMD64_PAGE_MASK,
919	/* [PGMMODE_AMD64_NX] = */ X86_CR3_AMD64_PAGE_MASK,
920	/* [PGMMODE_NESTED_32BIT = */ X86_CR3_PAGE_MASK,
921	/* [PGMMODE_NESTED_PAE] = */ X86_CR3_PAE_PAGE_MASK,
922	/* [PGMMODE_NESTED_AMD64] = */ X86_CR3_AMD64_PAGE_MASK,
923	/* [PGMMODE_EPT] = */ X86_CR3_EPT_PAGE_MASK,
924	/* [PGMMODE_NONE] = */ X86_CR3_AMD64_PAGE_MASK,
925	};
926
927
928	/**
929	* Gets the physical address mask for CR3 in the given paging mode.
930	*
931	* The mask is for eliminating flags and other stuff in CR3/EPTP when
932	* extracting the physical address. It is not for validating whether there are
933	* reserved bits set. PGM ASSUMES that whoever loaded the CR3 value and passed
934	* it to PGM checked for reserved bits, including reserved physical address
935	* bits.
936	*
937	* @returns The CR3 mask.
938	* @param enmMode The paging mode.
939	* @param enmSlatMode The second-level address translation mode.
940	*/
941	DECLINLINE(uint64_t) pgmGetCr3MaskForMode(PGMMODE enmMode, PGMSLAT enmSlatMode)
942	{
943	if (enmSlatMode == PGMSLAT_DIRECT)
944	{
945	Assert(enmMode != PGMMODE_EPT);
946	return g_auCr3MaskForMode[(unsigned)enmMode < (unsigned)PGMMODE_MAX ? enmMode : 0];
947	}
948	Assert(enmSlatMode == PGMSLAT_EPT);
949	return X86_CR3_EPT_PAGE_MASK;
950	}
951
952
953	/**
954	* Gets the masked CR3 value according to the current guest paging mode.
955	*
956	* See disclaimer in pgmGetCr3MaskForMode.
957	*
958	* @returns The masked PGM CR3 value.
959	* @param pVCpu The cross context virtual CPU structure.
960	* @param uCr3 The raw guest CR3 value.
961	*/
962	DECLINLINE(RTGCPHYS) pgmGetGuestMaskedCr3(PVMCPUCC pVCpu, uint64_t uCr3)
963	{
964	uint64_t const fCr3Mask = pgmGetCr3MaskForMode(pVCpu->pgm.s.enmGuestMode, pVCpu->pgm.s.enmGuestSlatMode);
965	RTGCPHYS GCPhysCR3 = (RTGCPHYS)(uCr3 & fCr3Mask);
966	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
967	return GCPhysCR3;
968	}
969
970
971	#ifdef IN_RING0
972	/**
973	* #PF Handler.
974	*
975	* @returns VBox status code (appropriate for trap handling and GC return).
976	* @param pVCpu The cross context virtual CPU structure.
977	* @param uErr The trap error code.
978	* @param pCtx Pointer to the register context for the CPU.
979	* @param pvFault The fault address.
980	*/
981	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault)
982	{
983	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
984
985	Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
986	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.StatRZTrap0e, a);
987	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = NULL; } );
988
989
990	# ifdef VBOX_WITH_STATISTICS
991	/*
992	* Error code stats.
993	*/
994	if (uErr & X86_TRAP_PF_US)
995	{
996	if (!(uErr & X86_TRAP_PF_P))
997	{
998	if (uErr & X86_TRAP_PF_RW)
999	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNotPresentWrite);
1000	else
1001	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNotPresentRead);
1002	}
1003	else if (uErr & X86_TRAP_PF_RW)
1004	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSWrite);
1005	else if (uErr & X86_TRAP_PF_RSVD)
1006	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSReserved);
1007	else if (uErr & X86_TRAP_PF_ID)
1008	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNXE);
1009	else
1010	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSRead);
1011	}
1012	else
1013	{ /* Supervisor */
1014	if (!(uErr & X86_TRAP_PF_P))
1015	{
1016	if (uErr & X86_TRAP_PF_RW)
1017	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVNotPresentWrite);
1018	else
1019	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVNotPresentRead);
1020	}
1021	else if (uErr & X86_TRAP_PF_RW)
1022	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVWrite);
1023	else if (uErr & X86_TRAP_PF_ID)
1024	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSNXE);
1025	else if (uErr & X86_TRAP_PF_RSVD)
1026	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVReserved);
1027	}
1028	# endif /* VBOX_WITH_STATISTICS */
1029
1030	/*
1031	* Call the worker.
1032	*/
1033	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1034	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1035	AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE);
1036	bool fLockTaken = false;
1037	int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pCtx, pvFault, &fLockTaken);
1038	if (fLockTaken)
1039	{
1040	PGM_LOCK_ASSERT_OWNER(pVM);
1041	PGM_UNLOCK(pVM);
1042	}
1043	LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
1044
1045	/*
1046	* Return code tweaks.
1047	*/
1048	if (rc != VINF_SUCCESS)
1049	{
1050	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
1051	rc = VINF_SUCCESS;
1052
1053	/* Note: hack alert for difficult to reproduce problem. */
1054	if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
1055	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
1056	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
1057	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
1058	{
1059	Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pCtx->rip));
1060	/* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
1061	rc = VINF_SUCCESS;
1062	}
1063	}
1064
1065	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eGuestPF); });
1066	STAM_STATS({ if (!pVCpu->pgmr0.s.pStatTrap0eAttributionR0)
1067	pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Misc; });
1068	STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.Stats.StatRZTrap0e, pVCpu->pgmr0.s.pStatTrap0eAttributionR0, a);
1069	return rc;
1070	}
1071	#endif /* IN_RING0 */
1072
1073
1074	/**
1075	* Prefetch a page
1076	*
1077	* Typically used to sync commonly used pages before entering raw mode
1078	* after a CR3 reload.
1079	*
1080	* @returns VBox status code suitable for scheduling.
1081	* @retval VINF_SUCCESS on success.
1082	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
1083	* @param pVCpu The cross context virtual CPU structure.
1084	* @param GCPtrPage Page to invalidate.
1085	*/
1086	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1087	{
1088	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,Prefetch), a);
1089
1090	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1091	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1092	AssertReturn(g_aPgmBothModeData[idxBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
1093	int rc = g_aPgmBothModeData[idxBth].pfnPrefetchPage(pVCpu, GCPtrPage);
1094
1095	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,Prefetch), a);
1096	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1097	return rc;
1098	}
1099
1100
1101	/**
1102	* Emulation of the invlpg instruction (HC only actually).
1103	*
1104	* @returns Strict VBox status code, special care required.
1105	* @retval VINF_PGM_SYNC_CR3 - handled.
1106	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
1107	*
1108	* @param pVCpu The cross context virtual CPU structure.
1109	* @param GCPtrPage Page to invalidate.
1110	*
1111	* @remark ASSUMES the page table entry or page directory is valid. Fairly
1112	* safe, but there could be edge cases!
1113	*
1114	* @todo Flush page or page directory only if necessary!
1115	* @todo VBOXSTRICTRC
1116	*/
1117	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1118	{
1119	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1120	int rc;
1121	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
1122
1123	IEMTlbInvalidatePage(pVCpu, GCPtrPage);
1124
1125	/*
1126	* Call paging mode specific worker.
1127	*/
1128	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage), a);
1129	PGM_LOCK_VOID(pVM);
1130
1131	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1132	AssertReturnStmt(idxBth < RT_ELEMENTS(g_aPgmBothModeData), PGM_UNLOCK(pVM), VERR_PGM_MODE_IPE);
1133	AssertReturnStmt(g_aPgmBothModeData[idxBth].pfnInvalidatePage, PGM_UNLOCK(pVM), VERR_PGM_MODE_IPE);
1134	rc = g_aPgmBothModeData[idxBth].pfnInvalidatePage(pVCpu, GCPtrPage);
1135
1136	PGM_UNLOCK(pVM);
1137	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage), a);
1138
1139	/* Ignore all irrelevant error codes. */
1140	if ( rc == VERR_PAGE_NOT_PRESENT
1141	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1142	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
1143	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
1144	rc = VINF_SUCCESS;
1145
1146	return rc;
1147	}
1148
1149
1150	/**
1151	* Executes an instruction using the interpreter.
1152	*
1153	* @returns VBox status code (appropriate for trap handling and GC return).
1154	* @param pVCpu The cross context virtual CPU structure.
1155	* @param pvFault Fault address.
1156	*/
1157	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault)
1158	{
1159	RT_NOREF(pvFault);
1160	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu);
1161	if (rc == VERR_EM_INTERPRETER)
1162	rc = VINF_EM_RAW_EMULATE_INSTR;
1163	if (rc != VINF_SUCCESS)
1164	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
1165	return rc;
1166	}
1167
1168
1169	/**
1170	* Gets effective page information (from the VMM page directory).
1171	*
1172	* @returns VBox status code.
1173	* @param pVCpu The cross context virtual CPU structure.
1174	* @param GCPtr Guest Context virtual address of the page.
1175	* @param pfFlags Where to store the flags. These are X86_PTE_*.
1176	* @param pHCPhys Where to store the HC physical address of the page.
1177	* This is page aligned.
1178	* @remark You should use PGMMapGetPage() for pages in a mapping.
1179	*/
1180	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
1181	{
1182	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1183	PGM_LOCK_VOID(pVM);
1184
1185	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1186	AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1187	AssertReturn(g_aPgmShadowModeData[idxShw].pfnGetPage, VERR_PGM_MODE_IPE);
1188	int rc = g_aPgmShadowModeData[idxShw].pfnGetPage(pVCpu, GCPtr, pfFlags, pHCPhys);
1189
1190	PGM_UNLOCK(pVM);
1191	return rc;
1192	}
1193
1194
1195	/**
1196	* Modify page flags for a range of pages in the shadow context.
1197	*
1198	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1199	*
1200	* @returns VBox status code.
1201	* @param pVCpu The cross context virtual CPU structure.
1202	* @param GCPtr Virtual address of the first page in the range.
1203	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1204	* @param fMask The AND mask - page flags X86_PTE_*.
1205	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1206	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1207	* @remark You must use PGMMapModifyPage() for pages in a mapping.
1208	*/
1209	DECLINLINE(int) pdmShwModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
1210	{
1211	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1212	Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 \| PGM_MK_PG_IS_WRITE_FAULT)));
1213
1214	GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK; /** @todo this ain't necessary, right... */
1215
1216	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1217	PGM_LOCK_VOID(pVM);
1218
1219	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1220	AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1221	AssertReturn(g_aPgmShadowModeData[idxShw].pfnModifyPage, VERR_PGM_MODE_IPE);
1222	int rc = g_aPgmShadowModeData[idxShw].pfnModifyPage(pVCpu, GCPtr, GUEST_PAGE_SIZE, fFlags, fMask, fOpFlags);
1223
1224	PGM_UNLOCK(pVM);
1225	return rc;
1226	}
1227
1228
1229	/**
1230	* Changing the page flags for a single page in the shadow page tables so as to
1231	* make it read-only.
1232	*
1233	* @returns VBox status code.
1234	* @param pVCpu The cross context virtual CPU structure.
1235	* @param GCPtr Virtual address of the first page in the range.
1236	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1237	*/
1238	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1239	{
1240	return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
1241	}
1242
1243
1244	/**
1245	* Changing the page flags for a single page in the shadow page tables so as to
1246	* make it writable.
1247	*
1248	* The call must know with 101% certainty that the guest page tables maps this
1249	* as writable too. This function will deal shared, zero and write monitored
1250	* pages.
1251	*
1252	* @returns VBox status code.
1253	* @param pVCpu The cross context virtual CPU structure.
1254	* @param GCPtr Virtual address of the first page in the range.
1255	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1256	*/
1257	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1258	{
1259	if (pVCpu->pgm.s.enmShadowMode != PGMMODE_NONE) /* avoid assertions */
1260	return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
1261	return VINF_SUCCESS;
1262	}
1263
1264
1265	/**
1266	* Changing the page flags for a single page in the shadow page tables so as to
1267	* make it not present.
1268	*
1269	* @returns VBox status code.
1270	* @param pVCpu The cross context virtual CPU structure.
1271	* @param GCPtr Virtual address of the first page in the range.
1272	* @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1273	*/
1274	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1275	{
1276	return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
1277	}
1278
1279
1280	/**
1281	* Changing the page flags for a single page in the shadow page tables so as to
1282	* make it supervisor and writable.
1283	*
1284	* This if for dealing with CR0.WP=0 and readonly user pages.
1285	*
1286	* @returns VBox status code.
1287	* @param pVCpu The cross context virtual CPU structure.
1288	* @param GCPtr Virtual address of the first page in the range.
1289	* @param fBigPage Whether or not this is a big page. If it is, we have to
1290	* change the shadow PDE as well. If it isn't, the caller
1291	* has checked that the shadow PDE doesn't need changing.
1292	* We ASSUME 4KB pages backing the big page here!
1293	* @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1294	*/
1295	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
1296	{
1297	int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
1298	if (rc == VINF_SUCCESS && fBigPage)
1299	{
1300	/* this is a bit ugly... */
1301	switch (pVCpu->pgm.s.enmShadowMode)
1302	{
1303	case PGMMODE_32_BIT:
1304	{
1305	PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
1306	AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1307	Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1308	pPde->u \|= X86_PDE_RW;
1309	Log(("-> PDE=%#llx (32)\n", pPde->u));
1310	break;
1311	}
1312	case PGMMODE_PAE:
1313	case PGMMODE_PAE_NX:
1314	{
1315	PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
1316	AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1317	Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1318	pPde->u \|= X86_PDE_RW;
1319	Log(("-> PDE=%#llx (PAE)\n", pPde->u));
1320	break;
1321	}
1322	default:
1323	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
1324	}
1325	}
1326	return rc;
1327	}
1328
1329
1330	/**
1331	* Gets the shadow page directory for the specified address, PAE.
1332	*
1333	* @returns Pointer to the shadow PD.
1334	* @param pVCpu The cross context virtual CPU structure.
1335	* @param GCPtr The address.
1336	* @param uGstPdpe Guest PDPT entry. Valid.
1337	* @param ppPD Receives address of page directory
1338	*/
1339	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1340	{
1341	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1342	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1343	PPGMPOOLPAGE pShwPage;
1344	int rc;
1345	PGM_LOCK_ASSERT_OWNER(pVM);
1346
1347
1348	/* Allocate page directory if not present. */
1349	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1350	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1351	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1352	X86PGPAEUINT const uPdpe = pPdpe->u;
1353	if (uPdpe & (X86_PDPE_P \| X86_PDPE_PG_MASK))
1354	{
1355	pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1356	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1357	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1358
1359	pgmPoolCacheUsed(pPool, pShwPage);
1360
1361	/* Update the entry if necessary. */
1362	X86PGPAEUINT const uPdpeNew = pShwPage->Core.Key \| (uGstPdpe & (X86_PDPE_P \| X86_PDPE_A)) \| (uPdpe & PGM_PDPT_FLAGS);
1363	if (uPdpeNew == uPdpe)
1364	{ /* likely */ }
1365	else
1366	ASMAtomicWriteU64(&pPdpe->u, uPdpeNew);
1367	}
1368	else
1369	{
1370	RTGCPTR64 GCPdPt;
1371	PGMPOOLKIND enmKind;
1372	if (pVM->pgm.s.fNestedPaging \|\| !CPUMIsGuestPagingEnabled(pVCpu))
1373	{
1374	/* AMD-V nested paging or real/protected mode without paging. */
1375	GCPdPt = GCPtr & ~(RT_BIT_64(X86_PDPT_SHIFT) - 1);
1376	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1377	}
1378	else if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1379	{
1380	if (uGstPdpe & X86_PDPE_P)
1381	{
1382	GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1383	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
1384	}
1385	else
1386	{
1387	/* PD not present; guest must reload CR3 to change it.
1388	* No need to monitor anything in this case. */
1389	/** @todo r=bird: WTF is hit?!? */
1390	/Assert(VM_IS_RAW_MODE_ENABLED(pVM)); - ??? /
1391	GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1392	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1393	Assert(uGstPdpe & X86_PDPE_P); /* caller should do this already */
1394	}
1395	}
1396	else
1397	{
1398	GCPdPt = CPUMGetGuestCR3(pVCpu);
1399	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
1400	}
1401
1402	/* Create a reference back to the PDPT by using the index in its shadow page. */
1403	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1404	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /fLockPage/,
1405	&pShwPage);
1406	AssertRCReturn(rc, rc);
1407
1408	/* Hook it up. */
1409	ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key \| (uGstPdpe & (X86_PDPE_P \| X86_PDPE_A)) \| (uPdpe & PGM_PDPT_FLAGS));
1410	}
1411	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1412
1413	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1414	return VINF_SUCCESS;
1415	}
1416
1417
1418	/**
1419	* Gets the pointer to the shadow page directory entry for an address, PAE.
1420	*
1421	* @returns Pointer to the PDE.
1422	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1423	* @param GCPtr The address.
1424	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1425	*/
1426	DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1427	{
1428	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1429	PGM_LOCK_ASSERT_OWNER(pVM);
1430
1431	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1432	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1433	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1434	X86PGPAEUINT const uPdpe = pPdpt->a[iPdPt].u;
1435	if (!(uPdpe & X86_PDPE_P))
1436	{
1437	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, uPdpe));
1438	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1439	}
1440	AssertMsg(uPdpe & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1441
1442	/* Fetch the pgm pool shadow descriptor. */
1443	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), uPdpe & X86_PDPE_PG_MASK);
1444	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1445
1446	*ppShwPde = pShwPde;
1447	return VINF_SUCCESS;
1448	}
1449
1450
1451	/**
1452	* Syncs the SHADOW page directory pointer for the specified address.
1453	*
1454	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1455	*
1456	* The caller is responsible for making sure the guest has a valid PD before
1457	* calling this function.
1458	*
1459	* @returns VBox status code.
1460	* @param pVCpu The cross context virtual CPU structure.
1461	* @param GCPtr The address.
1462	* @param uGstPml4e Guest PML4 entry (valid).
1463	* @param uGstPdpe Guest PDPT entry (valid).
1464	* @param ppPD Receives address of page directory
1465	*/
1466	static int pgmShwSyncLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1467	{
1468	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1469	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1470	bool const fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging \|\| !CPUMIsGuestPagingEnabled(pVCpu);
1471	int rc;
1472
1473	PGM_LOCK_ASSERT_OWNER(pVM);
1474
1475	/*
1476	* PML4.
1477	*/
1478	PPGMPOOLPAGE pShwPage;
1479	{
1480	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1481	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1482	AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1483	X86PGPAEUINT const uPml4e = pPml4e->u;
1484
1485	/* Allocate page directory pointer table if not present. */
1486	if (uPml4e & (X86_PML4E_P \| X86_PML4E_PG_MASK))
1487	{
1488	pShwPage = pgmPoolGetPage(pPool, uPml4e & X86_PML4E_PG_MASK);
1489	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1490
1491	pgmPoolCacheUsed(pPool, pShwPage);
1492
1493	/* Update the entry if needed. */
1494	X86PGPAEUINT const uPml4eNew = pShwPage->Core.Key \| (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask)
1495	\| (uPml4e & PGM_PML4_FLAGS);
1496	if (uPml4e == uPml4eNew)
1497	{ /* likely */ }
1498	else
1499	ASMAtomicWriteU64(&pPml4e->u, uPml4eNew);
1500	}
1501	else
1502	{
1503	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1504
1505	RTGCPTR64 GCPml4;
1506	PGMPOOLKIND enmKind;
1507	if (fNestedPagingOrNoGstPaging)
1508	{
1509	/* AMD-V nested paging or real/protected mode without paging */
1510	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT; /** @todo bogus calculation for PML5 */
1511	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1512	}
1513	else
1514	{
1515	GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1516	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1517	}
1518
1519	/* Create a reference back to the PDPT by using the index in its shadow page. */
1520	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1521	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /fLockPage/,
1522	&pShwPage);
1523	AssertRCReturn(rc, rc);
1524
1525	/* Hook it up. */
1526	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask)
1527	\| (uPml4e & PGM_PML4_FLAGS));
1528	}
1529	}
1530
1531	/*
1532	* PDPT.
1533	*/
1534	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1535	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1536	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1537	X86PGPAEUINT const uPdpe = pPdpe->u;
1538
1539	/* Allocate page directory if not present. */
1540	if (uPdpe & (X86_PDPE_P \| X86_PDPE_PG_MASK))
1541	{
1542	pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1543	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1544
1545	pgmPoolCacheUsed(pPool, pShwPage);
1546
1547	/* Update the entry if needed. */
1548	X86PGPAEUINT const uPdpeNew = pShwPage->Core.Key \| (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask)
1549	\| (uPdpe & PGM_PDPT_FLAGS);
1550	if (uPdpe == uPdpeNew)
1551	{ /* likely */ }
1552	else
1553	ASMAtomicWriteU64(&pPdpe->u, uPdpeNew);
1554	}
1555	else
1556	{
1557	RTGCPTR64 GCPdPt;
1558	PGMPOOLKIND enmKind;
1559	if (fNestedPagingOrNoGstPaging)
1560	{
1561	/* AMD-V nested paging or real/protected mode without paging */
1562	GCPdPt = GCPtr & ~(RT_BIT_64(iPdPt << X86_PDPT_SHIFT) - 1);
1563	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1564	}
1565	else
1566	{
1567	GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1568	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1569	}
1570
1571	/* Create a reference back to the PDPT by using the index in its shadow page. */
1572	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1573	pShwPage->idx, iPdPt, false /fLockPage/,
1574	&pShwPage);
1575	AssertRCReturn(rc, rc);
1576
1577	/* Hook it up. */
1578	ASMAtomicWriteU64(&pPdpe->u,
1579	pShwPage->Core.Key \| (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask) \| (uPdpe & PGM_PDPT_FLAGS));
1580	}
1581
1582	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1583	return VINF_SUCCESS;
1584	}
1585
1586
1587	/**
1588	* Gets the SHADOW page directory pointer for the specified address (long mode).
1589	*
1590	* @returns VBox status code.
1591	* @param pVCpu The cross context virtual CPU structure.
1592	* @param GCPtr The address.
1593	* @param ppPml4e Receives the address of the page map level 4 entry.
1594	* @param ppPdpt Receives the address of the page directory pointer table.
1595	* @param ppPD Receives the address of the page directory.
1596	*/
1597	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1598	{
1599	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1600	PGM_LOCK_ASSERT_OWNER(pVM);
1601
1602	/*
1603	* PML4
1604	*/
1605	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1606	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1607	AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1608	if (ppPml4e)
1609	*ppPml4e = (PX86PML4E)pPml4e;
1610	X86PGPAEUINT const uPml4e = pPml4e->u;
1611	Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, uPml4e));
1612	if (!(uPml4e & X86_PML4E_P)) /** @todo other code is check for NULL page frame number! */
1613	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1614
1615	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1616	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, uPml4e & X86_PML4E_PG_MASK);
1617	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1618
1619	/*
1620	* PDPT
1621	*/
1622	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1623	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1624	X86PGPAEUINT const uPdpe = pPdpt->a[iPdPt].u;
1625	if (!(uPdpe & X86_PDPE_P)) /** @todo other code is check for NULL page frame number! */
1626	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1627
1628	pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1629	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1630
1631	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1632	Log4(("pgmShwGetLongModePDPtr %RGv -> ppPD=%p PDE=%p/%RX64\n", GCPtr, ppPD, &(ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1633	return VINF_SUCCESS;
1634	}
1635
1636
1637	/**
1638	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1639	* backing pages in case the PDPT or PML4 entry is missing.
1640	*
1641	* @returns VBox status code.
1642	* @param pVCpu The cross context virtual CPU structure.
1643	* @param GCPtr The address.
1644	* @param ppPdpt Receives address of pdpt
1645	* @param ppPD Receives address of page directory
1646	*/
1647	static int pgmShwGetEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1648	{
1649	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1650	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1651	int rc;
1652
1653	Assert(pVM->pgm.s.fNestedPaging);
1654	PGM_LOCK_ASSERT_OWNER(pVM);
1655
1656	/*
1657	* PML4 level.
1658	*/
1659	PEPTPML4 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1660	Assert(pPml4);
1661
1662	/* Allocate page directory pointer table if not present. */
1663	PPGMPOOLPAGE pShwPage;
1664	{
1665	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1666	PEPTPML4E pPml4e = &pPml4->a[iPml4];
1667	EPTPML4E Pml4e;
1668	Pml4e.u = pPml4e->u;
1669	if (!(Pml4e.u & (EPT_E_PG_MASK \| EPT_E_READ)))
1670	{
1671	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1672	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1673	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /fLockPage/,
1674	&pShwPage);
1675	AssertRCReturn(rc, rc);
1676
1677	/* Hook up the new PDPT now. */
1678	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1679	}
1680	else
1681	{
1682	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1683	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1684
1685	pgmPoolCacheUsed(pPool, pShwPage);
1686
1687	/* Hook up the cached PDPT if needed (probably not given 512512 PTs to sync). /
1688	if (Pml4e.u == (pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE))
1689	{ }
1690	else
1691	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1692	}
1693	}
1694
1695	/*
1696	* PDPT level.
1697	*/
1698	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1699	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1700	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1701
1702	if (ppPdpt)
1703	*ppPdpt = pPdpt;
1704
1705	/* Allocate page directory if not present. */
1706	EPTPDPTE Pdpe;
1707	Pdpe.u = pPdpe->u;
1708	if (!(Pdpe.u & (EPT_E_PG_MASK \| EPT_E_READ)))
1709	{
1710	RTGCPTR64 const GCPdPt = GCPtr & ~(RT_BIT_64(EPT_PDPT_SHIFT) - 1);
1711	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1712	pShwPage->idx, iPdPt, false /fLockPage/,
1713	&pShwPage);
1714	AssertRCReturn(rc, rc);
1715
1716	/* Hook up the new PD now. */
1717	ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1718	}
1719	else
1720	{
1721	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1722	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1723
1724	pgmPoolCacheUsed(pPool, pShwPage);
1725
1726	/* Hook up the cached PD if needed (probably not given there are 512 PTs we may need sync). */
1727	if (Pdpe.u == (pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE))
1728	{ }
1729	else
1730	ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1731	}
1732
1733	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1734	return VINF_SUCCESS;
1735	}
1736
1737
1738	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1739	/**
1740	* Syncs the SHADOW nested-guest page directory pointer for the specified address.
1741	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1742	*
1743	* @returns VBox status code.
1744	* @param pVCpu The cross context virtual CPU structure.
1745	* @param GCPhysNested The nested-guest physical address.
1746	* @param ppPdpt Where to store the PDPT. Optional, can be NULL.
1747	* @param ppPD Where to store the PD. Optional, can be NULL.
1748	* @param pGstWalkAll The guest walk info.
1749	*/
1750	static int pgmShwGetNestedEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPhysNested, PEPTPDPT ppPdpt, PEPTPD ppPD,
1751	PPGMPTWALKGST pGstWalkAll)
1752	{
1753	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1754	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1755	int rc;
1756
1757	PPGMPOOLPAGE pShwPage;
1758	Assert(pVM->pgm.s.fNestedPaging);
1759	Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
1760	PGM_LOCK_ASSERT_OWNER(pVM);
1761
1762	/*
1763	* PML4 level.
1764	*/
1765	{
1766	PEPTPML4 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1767	Assert(pPml4);
1768
1769	/* Allocate page directory pointer table if not present. */
1770	{
1771	uint64_t const fShwFlags = pGstWalkAll->u.Ept.Pml4e.u & pVCpu->pgm.s.fGstEptShadowedPml4eMask;
1772	const unsigned iPml4e = (GCPhysNested >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1773	PEPTPML4E pPml4e = &pPml4->a[iPml4e];
1774
1775	if (!(pPml4e->u & (EPT_E_PG_MASK \| EPT_PRESENT_MASK)))
1776	{
1777	RTGCPHYS const GCPhysPdpt = pGstWalkAll->u.Ept.Pml4e.u & EPT_PML4E_PG_MASK;
1778	rc = pgmPoolAlloc(pVM, GCPhysPdpt, PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT, PGMPOOLACCESS_DONTCARE,
1779	PGM_A20_IS_ENABLED(pVCpu), pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4e, false /fLockPage/,
1780	&pShwPage);
1781	AssertRCReturn(rc, rc);
1782
1783	/* Hook up the new PDPT now. */
1784	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| fShwFlags);
1785	}
1786	else
1787	{
1788	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1789	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1790
1791	pgmPoolCacheUsed(pPool, pShwPage);
1792
1793	/* Hook up the cached PDPT if needed (probably not given 512512 PTs to sync). /
1794	if (pPml4e->u != (pShwPage->Core.Key \| fShwFlags))
1795	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| fShwFlags);
1796	}
1797	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
1798	Log7Func(("GstPml4e=%RX64 ShwPml4e=%RX64 iPml4e=%u\n", pGstWalkAll->u.Ept.Pml4e.u, pPml4e->u, iPml4e));
1799	}
1800	}
1801
1802	/*
1803	* PDPT level.
1804	*/
1805	{
1806	AssertReturn(!(pGstWalkAll->u.Ept.Pdpte.u & EPT_E_LEAF), VERR_NOT_SUPPORTED); /* shadowing 1GB pages not supported yet. */
1807
1808	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1809	if (ppPdpt)
1810	*ppPdpt = pPdpt;
1811
1812	uint64_t const fShwFlags = pGstWalkAll->u.Ept.Pdpte.u & pVCpu->pgm.s.fGstEptShadowedPdpteMask;
1813	const unsigned iPdPte = (GCPhysNested >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1814	PEPTPDPTE pPdpte = &pPdpt->a[iPdPte];
1815
1816	if (!(pPdpte->u & (EPT_E_PG_MASK \| EPT_PRESENT_MASK)))
1817	{
1818	RTGCPHYS const GCPhysPd = pGstWalkAll->u.Ept.Pdpte.u & EPT_PDPTE_PG_MASK;
1819	rc = pgmPoolAlloc(pVM, GCPhysPd, PGMPOOLKIND_EPT_PD_FOR_EPT_PD, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1820	pShwPage->idx, iPdPte, false /fLockPage/, &pShwPage);
1821	AssertRCReturn(rc, rc);
1822
1823	/* Hook up the new PD now. */
1824	ASMAtomicWriteU64(&pPdpte->u, pShwPage->Core.Key \| fShwFlags);
1825	}
1826	else
1827	{
1828	pShwPage = pgmPoolGetPage(pPool, pPdpte->u & EPT_PDPTE_PG_MASK);
1829	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1830
1831	pgmPoolCacheUsed(pPool, pShwPage);
1832
1833	/* Hook up the cached PD if needed (probably not given there are 512 PTs we may need sync). */
1834	if (pPdpte->u != (pShwPage->Core.Key \| fShwFlags))
1835	ASMAtomicWriteU64(&pPdpte->u, pShwPage->Core.Key \| fShwFlags);
1836	}
1837	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
1838	Log7Func(("GstPdpte=%RX64 ShwPdpte=%RX64 iPdPte=%u \n", pGstWalkAll->u.Ept.Pdpte.u, pPdpte->u, iPdPte));
1839
1840	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1841	}
1842
1843	return VINF_SUCCESS;
1844	}
1845	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1846
1847
1848	#ifdef IN_RING0
1849	/**
1850	* Synchronizes a range of nested page table entries.
1851	*
1852	* The caller must own the PGM lock.
1853	*
1854	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1855	* @param GCPhys Where to start.
1856	* @param cPages How many pages which entries should be synced.
1857	* @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1858	* host paging mode for AMD-V).
1859	*/
1860	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint32_t cPages, PGMMODE enmShwPagingMode)
1861	{
1862	PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1863
1864	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
1865	int rc;
1866	switch (enmShwPagingMode)
1867	{
1868	case PGMMODE_32_BIT:
1869	{
1870	X86PDE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1871	rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1872	break;
1873	}
1874
1875	case PGMMODE_PAE:
1876	case PGMMODE_PAE_NX:
1877	{
1878	X86PDEPAE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1879	rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1880	break;
1881	}
1882
1883	case PGMMODE_AMD64:
1884	case PGMMODE_AMD64_NX:
1885	{
1886	X86PDEPAE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1887	rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1888	break;
1889	}
1890
1891	case PGMMODE_EPT:
1892	{
1893	X86PDEPAE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1894	rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1895	break;
1896	}
1897
1898	default:
1899	AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1900	}
1901	return rc;
1902	}
1903	#endif /* IN_RING0 */
1904
1905
1906	/**
1907	* Gets effective Guest OS page information.
1908	*
1909	* When GCPtr is in a big page, the function will return as if it was a normal
1910	* 4KB page. If the need for distinguishing between big and normal page becomes
1911	* necessary at a later point, a PGMGstGetPage() will be created for that
1912	* purpose.
1913	*
1914	* @returns VBox status code.
1915	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1916	* @param GCPtr Guest Context virtual address of the page.
1917	* @param pWalk Where to store the page walk information.
1918	*/
1919	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
1920	{
1921	VMCPU_ASSERT_EMT(pVCpu);
1922	Assert(pWalk);
1923	uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
1924	AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
1925	AssertReturn(g_aPgmGuestModeData[idx].pfnGetPage, VERR_PGM_MODE_IPE);
1926	return g_aPgmGuestModeData[idx].pfnGetPage(pVCpu, GCPtr, pWalk);
1927	}
1928
1929
1930	/**
1931	* Maps the guest CR3.
1932	*
1933	* @returns VBox status code.
1934	* @param pVCpu The cross context virtual CPU structure.
1935	* @param GCPhysCr3 The guest CR3 value.
1936	* @param pHCPtrGuestCr3 Where to store the mapped memory.
1937	*/
1938	DECLINLINE(int) pgmGstMapCr3(PVMCPUCC pVCpu, RTGCPHYS GCPhysCr3, PRTHCPTR pHCPtrGuestCr3)
1939	{
1940	/** @todo this needs some reworking wrt. locking? */
1941	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1942	PGM_LOCK_VOID(pVM);
1943	PPGMPAGE pPageCr3 = pgmPhysGetPage(pVM, GCPhysCr3);
1944	AssertReturnStmt(pPageCr3, PGM_UNLOCK(pVM), VERR_PGM_INVALID_CR3_ADDR);
1945
1946	RTHCPTR HCPtrGuestCr3;
1947	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCr3, GCPhysCr3, (void **)&HCPtrGuestCr3);
1948	PGM_UNLOCK(pVM);
1949
1950	*pHCPtrGuestCr3 = HCPtrGuestCr3;
1951	return rc;
1952	}
1953
1954
1955	/**
1956	* Unmaps the guest CR3.
1957	*
1958	* @returns VBox status code.
1959	* @param pVCpu The cross context virtual CPU structure.
1960	*/
1961	DECLINLINE(int) pgmGstUnmapCr3(PVMCPUCC pVCpu)
1962	{
1963	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1964	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1965	AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
1966	return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
1967	}
1968
1969
1970	/**
1971	* Performs a guest page table walk.
1972	*
1973	* The guest should be in paged protect mode or long mode when making a call to
1974	* this function.
1975	*
1976	* @returns VBox status code.
1977	* @retval VINF_SUCCESS on success.
1978	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1979	* @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1980	* not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1981	*
1982	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1983	* @param GCPtr The guest virtual address to walk by.
1984	* @param pWalk Where to return the walk result. This is valid for some
1985	* error codes as well.
1986	* @param pGstWalk The guest mode specific page walk information.
1987	*/
1988	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
1989	{
1990	VMCPU_ASSERT_EMT(pVCpu);
1991	switch (pVCpu->pgm.s.enmGuestMode)
1992	{
1993	case PGMMODE_32_BIT:
1994	pGstWalk->enmType = PGMPTWALKGSTTYPE_32BIT;
1995	return PGM_GST_NAME_32BIT(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Legacy);
1996
1997	case PGMMODE_PAE:
1998	case PGMMODE_PAE_NX:
1999	pGstWalk->enmType = PGMPTWALKGSTTYPE_PAE;
2000	return PGM_GST_NAME_PAE(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Pae);
2001
2002	case PGMMODE_AMD64:
2003	case PGMMODE_AMD64_NX:
2004	pGstWalk->enmType = PGMPTWALKGSTTYPE_AMD64;
2005	return PGM_GST_NAME_AMD64(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Amd64);
2006
2007	case PGMMODE_REAL:
2008	case PGMMODE_PROTECTED:
2009	pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2010	return VERR_PGM_NOT_USED_IN_MODE;
2011
2012	case PGMMODE_EPT:
2013	case PGMMODE_NESTED_32BIT:
2014	case PGMMODE_NESTED_PAE:
2015	case PGMMODE_NESTED_AMD64:
2016	default:
2017	AssertFailed();
2018	pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2019	return VERR_PGM_NOT_USED_IN_MODE;
2020	}
2021	}
2022
2023
2024	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2025	/**
2026	* Performs a guest second-level address translation (SLAT).
2027	*
2028	* @returns VBox status code.
2029	* @retval VINF_SUCCESS on success.
2030	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
2031	* @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
2032	* not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
2033	*
2034	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2035	* @param GCPhysNested The nested-guest physical address being translated.
2036	* @param fIsLinearAddrValid Whether the linear address in @a GCPtrNested is the
2037	* cause for this translation.
2038	* @param GCPtrNested The nested-guest virtual address that initiated the
2039	* SLAT. If none, pass 0 (and not NIL_RTGCPTR).
2040	* @param pWalk Where to return the walk result. This is updated for
2041	* all error codes other than
2042	* VERR_PGM_NOT_USED_IN_MODE.
2043	* @param pGstWalk Where to store the second-level paging-mode specific
2044	* walk info.
2045	*/
2046	static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
2047	PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
2048	{
2049	/* SLAT mode must be valid at this point as this should only be used -after- we have determined SLAT mode. */
2050	Assert( pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_DIRECT
2051	&& pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_INVALID);
2052	AssertPtr(pWalk);
2053	AssertPtr(pGstWalk);
2054	switch (pVCpu->pgm.s.enmGuestSlatMode)
2055	{
2056	case PGMSLAT_EPT:
2057	pGstWalk->enmType = PGMPTWALKGSTTYPE_EPT;
2058	return PGM_GST_SLAT_NAME_EPT(Walk)(pVCpu, GCPhysNested, fIsLinearAddrValid, GCPtrNested, pWalk, &pGstWalk->u.Ept);
2059
2060	default:
2061	AssertFailed();
2062	pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2063	return VERR_PGM_NOT_USED_IN_MODE;
2064	}
2065	}
2066	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
2067
2068
2069	/**
2070	* Tries to continue the previous walk.
2071	*
2072	* @note Requires the caller to hold the PGM lock from the first
2073	* pgmGstPtWalk() call to the last pgmGstPtWalkNext() call. Otherwise
2074	* we cannot use the pointers.
2075	*
2076	* @returns VBox status code.
2077	* @retval VINF_SUCCESS on success.
2078	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
2079	* @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
2080	* not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
2081	*
2082	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2083	* @param GCPtr The guest virtual address to walk by.
2084	* @param pWalk Pointer to the previous walk result and where to return
2085	* the result of this walk. This is valid for some error
2086	* codes as well.
2087	* @param pGstWalk The guest-mode specific walk information.
2088	*/
2089	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
2090	{
2091	/*
2092	* We can only handle successfully walks.
2093	* We also limit ourselves to the next page.
2094	*/
2095	if ( pWalk->fSucceeded
2096	&& GCPtr - pWalk->GCPtr == GUEST_PAGE_SIZE)
2097	{
2098	Assert(pWalk->uLevel == 0);
2099	if (pGstWalk->enmType == PGMPTWALKGSTTYPE_AMD64)
2100	{
2101	/*
2102	* AMD64
2103	*/
2104	if (!pWalk->fGigantPage && !pWalk->fBigPage)
2105	{
2106	/*
2107	* We fall back to full walk if the PDE table changes, if any
2108	* reserved bits are set, or if the effective page access changes.
2109	*/
2110	const uint64_t fPteSame = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT
2111	\| X86_PTE_PCD \| X86_PTE_A \| X86_PTE_PAE_NX;
2112	const uint64_t fPdeSame = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT
2113	\| X86_PDE_PCD \| X86_PDE_A \| X86_PDE_PAE_NX \| X86_PDE_PS;
2114
2115	if ((GCPtr >> X86_PD_PAE_SHIFT) == (pWalk->GCPtr >> X86_PD_PAE_SHIFT))
2116	{
2117	if (pGstWalk->u.Amd64.pPte)
2118	{
2119	X86PTEPAE Pte;
2120	Pte.u = pGstWalk->u.Amd64.pPte[1].u;
2121	if ( (Pte.u & fPteSame) == (pGstWalk->u.Amd64.Pte.u & fPteSame)
2122	&& !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2123	{
2124	pWalk->GCPtr = GCPtr;
2125	pWalk->GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2126	pGstWalk->u.Amd64.Pte.u = Pte.u;
2127	pGstWalk->u.Amd64.pPte++;
2128	return VINF_SUCCESS;
2129	}
2130	}
2131	}
2132	else if ((GCPtr >> X86_PDPT_SHIFT) == (pWalk->GCPtr >> X86_PDPT_SHIFT))
2133	{
2134	Assert(!((GCPtr >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK)); /* Must be first PT entry. */
2135	if (pGstWalk->u.Amd64.pPde)
2136	{
2137	X86PDEPAE Pde;
2138	Pde.u = pGstWalk->u.Amd64.pPde[1].u;
2139	if ( (Pde.u & fPdeSame) == (pGstWalk->u.Amd64.Pde.u & fPdeSame)
2140	&& !(Pde.u & (pVCpu)->pgm.s.fGstAmd64MbzPdeMask))
2141	{
2142	/* Get the new PTE and check out the first entry. */
2143	int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, PGM_A20_APPLY(pVCpu, (Pde.u & X86_PDE_PAE_PG_MASK)),
2144	&pGstWalk->u.Amd64.pPt);
2145	if (RT_SUCCESS(rc))
2146	{
2147	pGstWalk->u.Amd64.pPte = &pGstWalk->u.Amd64.pPt->a[0];
2148	X86PTEPAE Pte;
2149	Pte.u = pGstWalk->u.Amd64.pPte->u;
2150	if ( (Pte.u & fPteSame) == (pGstWalk->u.Amd64.Pte.u & fPteSame)
2151	&& !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2152	{
2153	pWalk->GCPtr = GCPtr;
2154	pWalk->GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2155	pGstWalk->u.Amd64.Pte.u = Pte.u;
2156	pGstWalk->u.Amd64.Pde.u = Pde.u;
2157	pGstWalk->u.Amd64.pPde++;
2158	return VINF_SUCCESS;
2159	}
2160	}
2161	}
2162	}
2163	}
2164	}
2165	else if (!pWalk->fGigantPage)
2166	{
2167	if ((GCPtr & X86_PAGE_2M_BASE_MASK) == (pWalk->GCPtr & X86_PAGE_2M_BASE_MASK))
2168	{
2169	pWalk->GCPtr = GCPtr;
2170	pWalk->GCPhys += GUEST_PAGE_SIZE;
2171	return VINF_SUCCESS;
2172	}
2173	}
2174	else
2175	{
2176	if ((GCPtr & X86_PAGE_1G_BASE_MASK) == (pWalk->GCPtr & X86_PAGE_1G_BASE_MASK))
2177	{
2178	pWalk->GCPtr = GCPtr;
2179	pWalk->GCPhys += GUEST_PAGE_SIZE;
2180	return VINF_SUCCESS;
2181	}
2182	}
2183	}
2184	}
2185	/* Case we don't handle. Do full walk. */
2186	return pgmGstPtWalk(pVCpu, GCPtr, pWalk, pGstWalk);
2187	}
2188
2189
2190	/**
2191	* Modify page flags for a range of pages in the guest's tables
2192	*
2193	* The existing flags are ANDed with the fMask and ORed with the fFlags.
2194	*
2195	* @returns VBox status code.
2196	* @param pVCpu The cross context virtual CPU structure.
2197	* @param GCPtr Virtual address of the first page in the range.
2198	* @param cb Size (in bytes) of the range to apply the modification to.
2199	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
2200	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
2201	* Be very CAREFUL when ~'ing constants which could be 32-bit!
2202	*/
2203	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
2204	{
2205	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,GstModifyPage), a);
2206	VMCPU_ASSERT_EMT(pVCpu);
2207
2208	/*
2209	* Validate input.
2210	*/
2211	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
2212	Assert(cb);
2213
2214	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
2215
2216	/*
2217	* Adjust input.
2218	*/
2219	cb += GCPtr & GUEST_PAGE_OFFSET_MASK;
2220	cb = RT_ALIGN_Z(cb, GUEST_PAGE_SIZE);
2221	GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
2222
2223	/*
2224	* Call worker.
2225	*/
2226	uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
2227	AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
2228	AssertReturn(g_aPgmGuestModeData[idx].pfnModifyPage, VERR_PGM_MODE_IPE);
2229	int rc = g_aPgmGuestModeData[idx].pfnModifyPage(pVCpu, GCPtr, cb, fFlags, fMask);
2230
2231	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,GstModifyPage), a);
2232	return rc;
2233	}
2234
2235
2236	/**
2237	* Checks whether the given PAE PDPEs are potentially valid for the guest.
2238	*
2239	* @returns @c true if the PDPE is valid, @c false otherwise.
2240	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2241	* @param paPaePdpes The PAE PDPEs to validate.
2242	*
2243	* @remarks This function -only- checks the reserved bits in the PDPE entries.
2244	*/
2245	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes)
2246	{
2247	Assert(paPaePdpes);
2248	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
2249	{
2250	X86PDPE const PaePdpe = paPaePdpes[i];
2251	if ( !(PaePdpe.u & X86_PDPE_P)
2252	\|\| !(PaePdpe.u & pVCpu->pgm.s.fGstPaeMbzPdpeMask))
2253	{ /* likely */ }
2254	else
2255	return false;
2256	}
2257	return true;
2258	}
2259
2260
2261	/**
2262	* Performs the lazy mapping of the 32-bit guest PD.
2263	*
2264	* @returns VBox status code.
2265	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2266	* @param ppPd Where to return the pointer to the mapping. This is
2267	* always set.
2268	*/
2269	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd)
2270	{
2271	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2272	PGM_LOCK_VOID(pVM);
2273
2274	Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
2275
2276	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2277	PPGMPAGE pPage;
2278	int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2279	if (RT_SUCCESS(rc))
2280	{
2281	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPd);
2282	if (RT_SUCCESS(rc))
2283	{
2284	# ifdef IN_RING3
2285	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
2286	pVCpu->pgm.s.pGst32BitPdR3 = *ppPd;
2287	# else
2288	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR0PTR;
2289	pVCpu->pgm.s.pGst32BitPdR0 = *ppPd;
2290	# endif
2291	PGM_UNLOCK(pVM);
2292	return VINF_SUCCESS;
2293	}
2294	AssertRC(rc);
2295	}
2296	PGM_UNLOCK(pVM);
2297
2298	*ppPd = NULL;
2299	return rc;
2300	}
2301
2302
2303	/**
2304	* Performs the lazy mapping of the PAE guest PDPT.
2305	*
2306	* @returns VBox status code.
2307	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2308	* @param ppPdpt Where to return the pointer to the mapping. This is
2309	* always set.
2310	*/
2311	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt)
2312	{
2313	Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
2314	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2315	PGM_LOCK_VOID(pVM);
2316
2317	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2318	PPGMPAGE pPage;
2319	int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2320	if (RT_SUCCESS(rc))
2321	{
2322	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPdpt);
2323	if (RT_SUCCESS(rc))
2324	{
2325	# ifdef IN_RING3
2326	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
2327	pVCpu->pgm.s.pGstPaePdptR3 = *ppPdpt;
2328	# else
2329	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
2330	pVCpu->pgm.s.pGstPaePdptR0 = *ppPdpt;
2331	# endif
2332	PGM_UNLOCK(pVM);
2333	return VINF_SUCCESS;
2334	}
2335	AssertRC(rc);
2336	}
2337
2338	PGM_UNLOCK(pVM);
2339	*ppPdpt = NULL;
2340	return rc;
2341	}
2342
2343
2344	/**
2345	* Performs the lazy mapping / updating of a PAE guest PD.
2346	*
2347	* @returns Pointer to the mapping.
2348	* @returns VBox status code.
2349	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2350	* @param iPdpt Which PD entry to map (0..3).
2351	* @param ppPd Where to return the pointer to the mapping. This is
2352	* always set.
2353	*/
2354	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
2355	{
2356	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2357	PGM_LOCK_VOID(pVM);
2358
2359	PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
2360	Assert(pGuestPDPT);
2361	Assert(pGuestPDPT->a[iPdpt].u & X86_PDPE_P);
2362	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
2363	bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
2364
2365	PPGMPAGE pPage;
2366	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2367	if (RT_SUCCESS(rc))
2368	{
2369	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)ppPd);
2370	AssertRC(rc);
2371	if (RT_SUCCESS(rc))
2372	{
2373	# ifdef IN_RING3
2374	pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = NIL_RTR0PTR;
2375	pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = *ppPd;
2376	# else
2377	pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = NIL_RTR3PTR;
2378	pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = *ppPd;
2379	# endif
2380	if (fChanged)
2381	pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
2382	PGM_UNLOCK(pVM);
2383	return VINF_SUCCESS;
2384	}
2385	}
2386
2387	/* Invalid page or some failure, invalidate the entry. */
2388	pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
2389	pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = NIL_RTR3PTR;
2390	pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = NIL_RTR0PTR;
2391
2392	PGM_UNLOCK(pVM);
2393	return rc;
2394	}
2395
2396
2397	/**
2398	* Performs the lazy mapping of the 32-bit guest PD.
2399	*
2400	* @returns VBox status code.
2401	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2402	* @param ppPml4 Where to return the pointer to the mapping. This will
2403	* always be set.
2404	*/
2405	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4)
2406	{
2407	Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
2408	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2409	PGM_LOCK_VOID(pVM);
2410
2411	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2412	PPGMPAGE pPage;
2413	int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2414	if (RT_SUCCESS(rc))
2415	{
2416	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPml4);
2417	if (RT_SUCCESS(rc))
2418	{
2419	# ifdef IN_RING3
2420	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
2421	pVCpu->pgm.s.pGstAmd64Pml4R3 = *ppPml4;
2422	# else
2423	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
2424	pVCpu->pgm.s.pGstAmd64Pml4R0 = *ppPml4;
2425	# endif
2426	PGM_UNLOCK(pVM);
2427	return VINF_SUCCESS;
2428	}
2429	}
2430
2431	PGM_UNLOCK(pVM);
2432	*ppPml4 = NULL;
2433	return rc;
2434	}
2435
2436
2437	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2438	/**
2439	* Performs the lazy mapping of the guest PML4 table when using EPT paging.
2440	*
2441	* @returns VBox status code.
2442	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2443	* @param ppEptPml4 Where to return the pointer to the mapping. This will
2444	* always be set.
2445	*/
2446	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppEptPml4)
2447	{
2448	Assert(!pVCpu->pgm.s.CTX_SUFF(pGstEptPml4));
2449	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2450	PGM_LOCK_VOID(pVM);
2451
2452	RTGCPHYS const GCPhysEpt = pVCpu->pgm.s.uEptPtr & EPT_EPTP_PG_MASK;
2453	PPGMPAGE pPage;
2454	int rc = pgmPhysGetPageEx(pVM, GCPhysEpt, &pPage);
2455	if (RT_SUCCESS(rc))
2456	{
2457	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysEpt, (void **)ppEptPml4);
2458	if (RT_SUCCESS(rc))
2459	{
2460	# ifdef IN_RING3
2461	pVCpu->pgm.s.pGstEptPml4R0 = NIL_RTR0PTR;
2462	pVCpu->pgm.s.pGstEptPml4R3 = *ppEptPml4;
2463	# else
2464	pVCpu->pgm.s.pGstEptPml4R3 = NIL_RTR3PTR;
2465	pVCpu->pgm.s.pGstEptPml4R0 = *ppEptPml4;
2466	# endif
2467	PGM_UNLOCK(pVM);
2468	return VINF_SUCCESS;
2469	}
2470	}
2471
2472	PGM_UNLOCK(pVM);
2473	*ppEptPml4 = NULL;
2474	return rc;
2475	}
2476	#endif
2477
2478
2479	/**
2480	* Gets the current CR3 register value for the shadow memory context.
2481	* @returns CR3 value.
2482	* @param pVCpu The cross context virtual CPU structure.
2483	*/
2484	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
2485	{
2486	PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2487	AssertPtrReturn(pPoolPage, NIL_RTHCPHYS);
2488	return pPoolPage->Core.Key;
2489	}
2490
2491
2492	/**
2493	* Forces lazy remapping of the guest's PAE page-directory structures.
2494	*
2495	* @param pVCpu The cross context virtual CPU structure.
2496	*/
2497	static void pgmGstFlushPaePdpes(PVMCPU pVCpu)
2498	{
2499	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGCPhysGstPaePDs); i++)
2500	{
2501	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2502	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2503	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2504	}
2505	}
2506
2507
2508	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2509	/**
2510	* Performs second-level address translation for the given CR3 and updates the
2511	* nested-guest CR3 when successful.
2512	*
2513	* @returns VBox status code.
2514	* @param pVCpu The cross context virtual CPU structure.
2515	* @param uCr3 The masked nested-guest CR3 value.
2516	* @param pGCPhysCR3 Where to store the translated CR3.
2517	*
2518	* @warning This updates PGMCPU::GCPhysNstGstCR3 when the translation succeeds. Be
2519	* mindful of this in code that's hyper sensitive to the order of
2520	* operations.
2521	*/
2522	static int pgmGstSlatTranslateCr3(PVMCPUCC pVCpu, uint64_t uCr3, PRTGCPHYS pGCPhysCr3)
2523	{
2524	if (uCr3 != pVCpu->pgm.s.GCPhysNstGstCR3)
2525	{
2526	PGMPTWALK Walk;
2527	PGMPTWALKGST GstWalk;
2528	int const rc = pgmGstSlatWalk(pVCpu, uCr3, false /* fIsLinearAddrValid /, 0 / GCPtrNested */, &Walk, &GstWalk);
2529	if (RT_SUCCESS(rc))
2530	{
2531	/* Update nested-guest CR3. */
2532	pVCpu->pgm.s.GCPhysNstGstCR3 = uCr3;
2533
2534	/* Pass back the translated result. */
2535	*pGCPhysCr3 = Walk.GCPhys;
2536	return VINF_SUCCESS;
2537	}
2538
2539	/* Translation failed. */
2540	*pGCPhysCr3 = NIL_RTGCPHYS;
2541	return rc;
2542	}
2543
2544	/*
2545	* If the nested-guest CR3 has not changed, then the previously
2546	* translated CR3 result (i.e. GCPhysCR3) is passed back.
2547	*/
2548	*pGCPhysCr3 = pVCpu->pgm.s.GCPhysCR3;
2549	return VINF_SUCCESS;
2550	}
2551	#endif
2552
2553
2554	/**
2555	* Performs and schedules necessary updates following a CR3 load or reload.
2556	*
2557	* This will normally involve mapping the guest PD or nPDPT
2558	*
2559	* @returns VBox status code.
2560	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
2561	* safely be ignored and overridden since the FF will be set too then.
2562	* @param pVCpu The cross context virtual CPU structure.
2563	* @param cr3 The new cr3.
2564	* @param fGlobal Indicates whether this is a global flush or not.
2565	*/
2566	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal)
2567	{
2568	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLB), a);
2569	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2570
2571	VMCPU_ASSERT_EMT(pVCpu);
2572
2573	/*
2574	* Always flag the necessary updates; necessary for hardware acceleration
2575	*/
2576	/** @todo optimize this, it shouldn't always be necessary. */
2577	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2578	if (fGlobal)
2579	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2580
2581	/*
2582	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2583	*/
2584	RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2585	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2586	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2587	if ( pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT
2588	&& PGMMODE_WITH_PAGING(pVCpu->pgm.s.enmGuestMode))
2589	{
2590	RTGCPHYS GCPhysOut;
2591	int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2592	if (RT_SUCCESS(rc))
2593	GCPhysCR3 = GCPhysOut;
2594	else
2595	{
2596	/* CR3 SLAT translation failed but we try to pretend it
2597	succeeded for the reasons mentioned in PGMHCChangeMode(). */
2598	AssertMsgFailed(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", cr3, rc));
2599	int const rc2 = pgmGstUnmapCr3(pVCpu);
2600	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2601	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2602	return rc2;
2603	}
2604	}
2605	#endif
2606
2607	LogFlowFunc(("cr3=%RX64 old=%RX64 fGlobal=%d\n", cr3, GCPhysOldCR3, fGlobal));
2608	int rc = VINF_SUCCESS;
2609	if (GCPhysOldCR3 != GCPhysCR3)
2610	{
2611	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2612	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2613	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2614
2615	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2616	rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2617	if (RT_LIKELY(rc == VINF_SUCCESS))
2618	{ }
2619	else
2620	{
2621	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
2622	Assert(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_PGM_SYNC_CR3));
2623	pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped) = false;
2624	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
2625	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2626	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
2627	}
2628
2629	if (fGlobal)
2630	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
2631	else
2632	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBNewCR3));
2633	}
2634	else
2635	{
2636	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2637	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2638	if (pPool->cDirtyPages)
2639	{
2640	PGM_LOCK_VOID(pVM);
2641	pgmPoolResetDirtyPages(pVM);
2642	PGM_UNLOCK(pVM);
2643	}
2644	#endif
2645	if (fGlobal)
2646	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
2647	else
2648	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBSameCR3));
2649
2650	/*
2651	* Flush PAE PDPTEs.
2652	*/
2653	if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
2654	pgmGstFlushPaePdpes(pVCpu);
2655	}
2656
2657	IEMTlbInvalidateAll(pVCpu);
2658	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLB), a);
2659	return rc;
2660	}
2661
2662
2663	/**
2664	* Performs and schedules necessary updates following a CR3 load or reload when
2665	* using nested or extended paging.
2666	*
2667	* This API is an alternative to PGMFlushTLB that avoids actually flushing the
2668	* TLB and triggering a SyncCR3.
2669	*
2670	* This will normally involve mapping the guest PD or nPDPT
2671	*
2672	* @returns VBox status code.
2673	* @retval VINF_SUCCESS.
2674	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync (not for nested
2675	* paging modes). This can safely be ignored and overridden since the
2676	* FF will be set too then.
2677	* @param pVCpu The cross context virtual CPU structure.
2678	* @param cr3 The new CR3.
2679	*/
2680	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3)
2681	{
2682	VMCPU_ASSERT_EMT(pVCpu);
2683
2684	/* We assume we're only called in nested paging mode. */
2685	Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2686
2687	/*
2688	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2689	*/
2690	RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2691	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2692	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2693	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2694	{
2695	RTGCPHYS GCPhysOut;
2696	int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2697	if (RT_SUCCESS(rc))
2698	GCPhysCR3 = GCPhysOut;
2699	else
2700	{
2701	/* CR3 SLAT translation failed but we try to pretend it
2702	succeeded for the reasons mentioned in PGMHCChangeMode(). */
2703	Log(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", cr3, rc));
2704	int const rc2 = pgmGstUnmapCr3(pVCpu);
2705	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2706	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2707	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2708	return rc2;
2709	}
2710	}
2711	#endif
2712
2713	LogFlowFunc(("cr3=%RX64 old=%RX64\n", cr3, GCPhysOldCR3));
2714	int rc = VINF_SUCCESS;
2715	if (GCPhysOldCR3 != GCPhysCR3)
2716	{
2717	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2718	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2719	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2720
2721	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2722	rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2723
2724	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
2725	}
2726	/*
2727	* Flush PAE PDPTEs.
2728	*/
2729	else if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
2730	pgmGstFlushPaePdpes(pVCpu);
2731
2732	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2733	return rc;
2734	}
2735
2736
2737	/**
2738	* Synchronize the paging structures.
2739	*
2740	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2741	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2742	* in several places, most importantly whenever the CR3 is loaded.
2743	*
2744	* @returns VBox status code. May return VINF_PGM_SYNC_CR3 in RC/R0.
2745	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
2746	* the VMM into guest context.
2747	* @param pVCpu The cross context virtual CPU structure.
2748	* @param cr0 Guest context CR0 register
2749	* @param cr3 Guest context CR3 register
2750	* @param cr4 Guest context CR4 register
2751	* @param fGlobal Including global page directories or not
2752	*/
2753	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2754	{
2755	int rc;
2756
2757	VMCPU_ASSERT_EMT(pVCpu);
2758
2759	/*
2760	* The pool may have pending stuff and even require a return to ring-3 to
2761	* clear the whole thing.
2762	*/
2763	rc = pgmPoolSyncCR3(pVCpu);
2764	if (rc != VINF_SUCCESS)
2765	return rc;
2766
2767	/*
2768	* We might be called when we shouldn't.
2769	*
2770	* The mode switching will ensure that the PD is resynced after every mode
2771	* switch. So, if we find ourselves here when in protected or real mode
2772	* we can safely clear the FF and return immediately.
2773	*/
2774	if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2775	{
2776	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
2777	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2778	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2779	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2780	return VINF_SUCCESS;
2781	}
2782
2783	/* If global pages are not supported, then all flushes are global. */
2784	if (!(cr4 & X86_CR4_PGE))
2785	fGlobal = true;
2786	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2787	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2788
2789	/*
2790	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2791	* This should be done before SyncCR3.
2792	*/
2793	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2794	{
2795	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2796
2797	RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2798	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2799	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2800	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2801	{
2802	RTGCPHYS GCPhysOut;
2803	int rc2 = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2804	if (RT_SUCCESS(rc2))
2805	GCPhysCR3 = GCPhysOut;
2806	else
2807	{
2808	/* CR3 SLAT translation failed but we try to pretend it
2809	succeeded for the reasons mentioned in PGMHCChangeMode(). */
2810	AssertMsgFailed(("Failed to translate CR3 %#RX64. rc=%Rrc\n", cr3, rc2));
2811	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2812	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2813	return rc2;
2814	}
2815	}
2816	#endif
2817	Assert(!pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped));
2818	if (GCPhysOldCR3 != GCPhysCR3)
2819	{
2820	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2821	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2822	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2823	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2824	rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2825	}
2826
2827	/* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2828	if ( rc == VINF_PGM_SYNC_CR3
2829	\|\| (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2830	{
2831	Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2832	#ifdef IN_RING3
2833	rc = pgmPoolSyncCR3(pVCpu);
2834	#else
2835	if (rc == VINF_PGM_SYNC_CR3)
2836	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2837	return VINF_PGM_SYNC_CR3;
2838	#endif
2839	}
2840	AssertRCReturn(rc, rc);
2841	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2842	}
2843
2844	/*
2845	* Let the 'Bth' function do the work and we'll just keep track of the flags.
2846	*/
2847	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
2848
2849	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2850	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2851	AssertReturn(g_aPgmBothModeData[idxBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
2852	rc = g_aPgmBothModeData[idxBth].pfnSyncCR3(pVCpu, cr0, cr3, cr4, fGlobal);
2853
2854	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
2855	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2856	if (rc == VINF_SUCCESS)
2857	{
2858	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2859	{
2860	/* Go back to ring 3 if a pgm pool sync is again pending. */
2861	return VINF_PGM_SYNC_CR3;
2862	}
2863
2864	if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2865	{
2866	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2867	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2868	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2869	}
2870	}
2871
2872	/*
2873	* Now flush the CR3 (guest context).
2874	*/
2875	if (rc == VINF_SUCCESS)
2876	PGM_INVL_VCPU_TLBS(pVCpu);
2877	return rc;
2878	}
2879
2880
2881	/**
2882	* Maps all the PAE PDPE entries.
2883	*
2884	* @returns VBox status code.
2885	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2886	* @param paPaePdpes The new PAE PDPE values.
2887	*
2888	* @remarks This function may be invoked during the process of changing the guest
2889	* paging mode to PAE, hence the guest state (CR0, CR4 etc.) may not
2890	* reflect PAE paging just yet.
2891	*/
2892	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes)
2893	{
2894	Assert(paPaePdpes);
2895	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
2896	{
2897	X86PDPE const PaePdpe = paPaePdpes[i];
2898
2899	/*
2900	* In some cases (e.g. in SVM with nested paging) the validation of the PAE PDPEs
2901	* are deferred.[1] Also, different situations require different handling of invalid
2902	* PDPE entries. Here we assume the caller has already validated or doesn't require
2903	* validation of the PDPEs.
2904	*
2905	* In the case of nested EPT (i.e. for nested-guests), the PAE PDPEs have been
2906	* validated by the VMX transition.
2907	*
2908	* [1] -- See AMD spec. 15.25.10 "Legacy PAE Mode".
2909	*/
2910	if ((PaePdpe.u & (pVCpu->pgm.s.fGstPaeMbzPdpeMask \| X86_PDPE_P)) == X86_PDPE_P)
2911	{
2912	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2913	RTHCPTR HCPtr;
2914
2915	RTGCPHYS GCPhys;
2916	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2917	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2918	{
2919	PGMPTWALK Walk;
2920	PGMPTWALKGST GstWalk;
2921	RTGCPHYS const GCPhysNested = PaePdpe.u & X86_PDPE_PG_MASK;
2922	int const rc = pgmGstSlatWalk(pVCpu, GCPhysNested, false /* fIsLinearAddrValid /, 0 / GCPtrNested */,
2923	&Walk, &GstWalk);
2924	if (RT_SUCCESS(rc))
2925	GCPhys = Walk.GCPhys;
2926	else
2927	{
2928	/*
2929	* Second-level address translation of the PAE PDPE has failed but we must -NOT-
2930	* abort and return a failure now. This is because we're called from a Mov CRx
2931	* instruction (or similar operation). Let's just pretend success but flag that
2932	* we need to map this PDPE lazily later.
2933	*
2934	* See Intel spec. 25.3 "Changes to instruction behavior in VMX non-root operation".
2935	* See Intel spec. 28.3.1 "EPT Overview".
2936	*/
2937	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2938	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2939	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2940	continue;
2941	}
2942	}
2943	else
2944	#endif
2945	{
2946	GCPhys = PGM_A20_APPLY(pVCpu, PaePdpe.u & X86_PDPE_PG_MASK);
2947	}
2948
2949	PGM_LOCK_VOID(pVM);
2950	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
2951	AssertReturnStmt(pPage, PGM_UNLOCK(pVM), VERR_PGM_INVALID_PDPE_ADDR);
2952	int const rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
2953	PGM_UNLOCK(pVM);
2954	if (RT_SUCCESS(rc))
2955	{
2956	#ifdef IN_RING3
2957	pVCpu->pgm.s.apGstPaePDsR3[i] = (PX86PDPAE)HCPtr;
2958	pVCpu->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
2959	#else
2960	pVCpu->pgm.s.apGstPaePDsR3[i] = NIL_RTR3PTR;
2961	pVCpu->pgm.s.apGstPaePDsR0[i] = (PX86PDPAE)HCPtr;
2962	#endif
2963	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
2964	continue;
2965	}
2966	AssertMsgFailed(("PGMPhysMapPaePdpes: rc2=%d GCPhys=%RGp i=%d\n", rc, GCPhys, i));
2967	}
2968	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2969	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2970	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2971	}
2972	return VINF_SUCCESS;
2973	}
2974
2975
2976	/**
2977	* Validates and maps the PDPT and PAE PDPEs referenced by the given CR3.
2978	*
2979	* @returns VBox status code.
2980	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2981	* @param cr3 The guest CR3 value.
2982	*
2983	* @remarks This function may be invoked during the process of changing the guest
2984	* paging mode to PAE but the guest state (CR0, CR4 etc.) may not reflect
2985	* PAE paging just yet.
2986	*/
2987	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3)
2988	{
2989	/*
2990	* Read the page-directory-pointer table (PDPT) at CR3.
2991	*/
2992	RTGCPHYS GCPhysCR3 = (cr3 & X86_CR3_PAE_PAGE_MASK);
2993	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2994
2995	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2996	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2997	{
2998	RTGCPHYS GCPhysOut;
2999	int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
3000	if (RT_SUCCESS(rc))
3001	GCPhysCR3 = GCPhysOut;
3002	else
3003	{
3004	Log(("Failed to load CR3 at %#RX64. rc=%Rrc\n", GCPhysCR3, rc));
3005	return rc;
3006	}
3007	}
3008	#endif
3009
3010	RTHCPTR HCPtrGuestCr3;
3011	int rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCr3);
3012	if (RT_SUCCESS(rc))
3013	{
3014	/*
3015	* Validate the page-directory-pointer table entries (PDPE).
3016	*/
3017	X86PDPE aPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
3018	memcpy(&aPaePdpes[0], HCPtrGuestCr3, sizeof(aPaePdpes));
3019	if (PGMGstArePaePdpesValid(pVCpu, &aPaePdpes[0]))
3020	{
3021	/*
3022	* Map the PDPT.
3023	* We deliberately don't update PGM's GCPhysCR3 here as it's expected
3024	* that PGMFlushTLB will be called soon and only a change to CR3 then
3025	* will cause the shadow page tables to be updated.
3026	*/
3027	#ifdef IN_RING3
3028	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCr3;
3029	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
3030	#else
3031	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
3032	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCr3;
3033	#endif
3034
3035	/*
3036	* Update CPUM and map the 4 PAE PDPEs.
3037	*/
3038	CPUMSetGuestPaePdpes(pVCpu, &aPaePdpes[0]);
3039	rc = PGMGstMapPaePdpes(pVCpu, &aPaePdpes[0]);
3040	if (RT_SUCCESS(rc))
3041	{
3042	#ifdef IN_RING3
3043	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
3044	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
3045	#else
3046	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
3047	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
3048	#endif
3049	pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
3050	}
3051	}
3052	else
3053	rc = VERR_PGM_PAE_PDPE_RSVD;
3054	}
3055	return rc;
3056	}
3057
3058
3059	/**
3060	* Called whenever CR0 or CR4 in a way which may affect the paging mode.
3061	*
3062	* @returns VBox status code, with the following informational code for
3063	* VM scheduling.
3064	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
3065	* @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
3066	*
3067	* @param pVCpu The cross context virtual CPU structure.
3068	* @param cr0 The new cr0.
3069	* @param cr4 The new cr4.
3070	* @param efer The new extended feature enable register.
3071	* @param fForce Whether to force a mode change.
3072	*/
3073	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce)
3074	{
3075	VMCPU_ASSERT_EMT(pVCpu);
3076
3077	/*
3078	* Calc the new guest mode.
3079	*
3080	* Note! We check PG before PE and without requiring PE because of the
3081	* special AMD-V paged real mode (APM vol 2, rev 3.28, 15.9).
3082	*/
3083	PGMMODE enmGuestMode;
3084	if (cr0 & X86_CR0_PG)
3085	{
3086	if (!(cr4 & X86_CR4_PAE))
3087	{
3088	bool const fPse = !!(cr4 & X86_CR4_PSE);
3089	if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
3090	Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
3091	pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
3092	enmGuestMode = PGMMODE_32_BIT;
3093	}
3094	else if (!(efer & MSR_K6_EFER_LME))
3095	{
3096	if (!(efer & MSR_K6_EFER_NXE))
3097	enmGuestMode = PGMMODE_PAE;
3098	else
3099	enmGuestMode = PGMMODE_PAE_NX;
3100	}
3101	else
3102	{
3103	if (!(efer & MSR_K6_EFER_NXE))
3104	enmGuestMode = PGMMODE_AMD64;
3105	else
3106	enmGuestMode = PGMMODE_AMD64_NX;
3107	}
3108	}
3109	else if (!(cr0 & X86_CR0_PE))
3110	enmGuestMode = PGMMODE_REAL;
3111	else
3112	enmGuestMode = PGMMODE_PROTECTED;
3113
3114	/*
3115	* Did it change?
3116	*/
3117	if ( !fForce
3118	&& pVCpu->pgm.s.enmGuestMode == enmGuestMode)
3119	return VINF_SUCCESS;
3120
3121	/* Flush the TLB */
3122	PGM_INVL_VCPU_TLBS(pVCpu);
3123	return PGMHCChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode, fForce);
3124	}
3125
3126
3127	/**
3128	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3129	*
3130	* @returns PGM_TYPE_*.
3131	* @param pgmMode The mode value to convert.
3132	*/
3133	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3134	{
3135	switch (pgmMode)
3136	{
3137	case PGMMODE_REAL: return PGM_TYPE_REAL;
3138	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3139	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3140	case PGMMODE_PAE:
3141	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3142	case PGMMODE_AMD64:
3143	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3144	case PGMMODE_NESTED_32BIT: return PGM_TYPE_NESTED_32BIT;
3145	case PGMMODE_NESTED_PAE: return PGM_TYPE_NESTED_PAE;
3146	case PGMMODE_NESTED_AMD64: return PGM_TYPE_NESTED_AMD64;
3147	case PGMMODE_EPT: return PGM_TYPE_EPT;
3148	case PGMMODE_NONE: return PGM_TYPE_NONE;
3149	default:
3150	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3151	}
3152	}
3153
3154
3155	/**
3156	* Calculates the shadow paging mode.
3157	*
3158	* @returns The shadow paging mode.
3159	* @param pVM The cross context VM structure.
3160	* @param enmGuestMode The guest mode.
3161	* @param enmHostMode The host mode.
3162	* @param enmShadowMode The current shadow mode.
3163	*/
3164	static PGMMODE pgmCalcShadowMode(PVMCC pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode)
3165	{
3166	switch (enmGuestMode)
3167	{
3168	case PGMMODE_REAL:
3169	case PGMMODE_PROTECTED:
3170	switch (enmHostMode)
3171	{
3172	case SUPPAGINGMODE_32_BIT:
3173	case SUPPAGINGMODE_32_BIT_GLOBAL:
3174	enmShadowMode = PGMMODE_32_BIT;
3175	break;
3176
3177	case SUPPAGINGMODE_PAE:
3178	case SUPPAGINGMODE_PAE_NX:
3179	case SUPPAGINGMODE_PAE_GLOBAL:
3180	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3181	enmShadowMode = PGMMODE_PAE;
3182	break;
3183
3184	case SUPPAGINGMODE_AMD64:
3185	case SUPPAGINGMODE_AMD64_GLOBAL:
3186	case SUPPAGINGMODE_AMD64_NX:
3187	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3188	enmShadowMode = PGMMODE_PAE;
3189	break;
3190
3191	default:
3192	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3193	}
3194	break;
3195
3196	case PGMMODE_32_BIT:
3197	switch (enmHostMode)
3198	{
3199	case SUPPAGINGMODE_32_BIT:
3200	case SUPPAGINGMODE_32_BIT_GLOBAL:
3201	enmShadowMode = PGMMODE_32_BIT;
3202	break;
3203
3204	case SUPPAGINGMODE_PAE:
3205	case SUPPAGINGMODE_PAE_NX:
3206	case SUPPAGINGMODE_PAE_GLOBAL:
3207	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3208	enmShadowMode = PGMMODE_PAE;
3209	break;
3210
3211	case SUPPAGINGMODE_AMD64:
3212	case SUPPAGINGMODE_AMD64_GLOBAL:
3213	case SUPPAGINGMODE_AMD64_NX:
3214	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3215	enmShadowMode = PGMMODE_PAE;
3216	break;
3217
3218	default:
3219	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3220	}
3221	break;
3222
3223	case PGMMODE_PAE:
3224	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3225	switch (enmHostMode)
3226	{
3227	case SUPPAGINGMODE_32_BIT:
3228	case SUPPAGINGMODE_32_BIT_GLOBAL:
3229	enmShadowMode = PGMMODE_PAE;
3230	break;
3231
3232	case SUPPAGINGMODE_PAE:
3233	case SUPPAGINGMODE_PAE_NX:
3234	case SUPPAGINGMODE_PAE_GLOBAL:
3235	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3236	enmShadowMode = PGMMODE_PAE;
3237	break;
3238
3239	case SUPPAGINGMODE_AMD64:
3240	case SUPPAGINGMODE_AMD64_GLOBAL:
3241	case SUPPAGINGMODE_AMD64_NX:
3242	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3243	enmShadowMode = PGMMODE_PAE;
3244	break;
3245
3246	default:
3247	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3248	}
3249	break;
3250
3251	case PGMMODE_AMD64:
3252	case PGMMODE_AMD64_NX:
3253	switch (enmHostMode)
3254	{
3255	case SUPPAGINGMODE_32_BIT:
3256	case SUPPAGINGMODE_32_BIT_GLOBAL:
3257	enmShadowMode = PGMMODE_AMD64;
3258	break;
3259
3260	case SUPPAGINGMODE_PAE:
3261	case SUPPAGINGMODE_PAE_NX:
3262	case SUPPAGINGMODE_PAE_GLOBAL:
3263	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3264	enmShadowMode = PGMMODE_AMD64;
3265	break;
3266
3267	case SUPPAGINGMODE_AMD64:
3268	case SUPPAGINGMODE_AMD64_GLOBAL:
3269	case SUPPAGINGMODE_AMD64_NX:
3270	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3271	enmShadowMode = PGMMODE_AMD64;
3272	break;
3273
3274	default:
3275	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3276	}
3277	break;
3278
3279	default:
3280	AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), PGMMODE_INVALID);
3281	}
3282
3283	/*
3284	* Override the shadow mode when NEM, IEM or nested paging is active.
3285	*/
3286	if (!VM_IS_HM_ENABLED(pVM))
3287	{
3288	Assert(VM_IS_NEM_ENABLED(pVM) \|\| VM_IS_EXEC_ENGINE_IEM(pVM));
3289	pVM->pgm.s.fNestedPaging = true;
3290	enmShadowMode = PGMMODE_NONE;
3291	}
3292	else
3293	{
3294	bool fNestedPaging = HMIsNestedPagingActive(pVM);
3295	pVM->pgm.s.fNestedPaging = fNestedPaging;
3296	if (fNestedPaging)
3297	{
3298	if (HMIsVmxActive(pVM))
3299	enmShadowMode = PGMMODE_EPT;
3300	else
3301	{
3302	/* The nested SVM paging depends on the host one. */
3303	Assert(HMIsSvmActive(pVM));
3304	if ( enmGuestMode == PGMMODE_AMD64
3305	\|\| enmGuestMode == PGMMODE_AMD64_NX)
3306	enmShadowMode = PGMMODE_NESTED_AMD64;
3307	else
3308	switch (pVM->pgm.s.enmHostMode)
3309	{
3310	case SUPPAGINGMODE_32_BIT:
3311	case SUPPAGINGMODE_32_BIT_GLOBAL:
3312	enmShadowMode = PGMMODE_NESTED_32BIT;
3313	break;
3314
3315	case SUPPAGINGMODE_PAE:
3316	case SUPPAGINGMODE_PAE_GLOBAL:
3317	case SUPPAGINGMODE_PAE_NX:
3318	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3319	enmShadowMode = PGMMODE_NESTED_PAE;
3320	break;
3321
3322	case SUPPAGINGMODE_AMD64:
3323	case SUPPAGINGMODE_AMD64_GLOBAL:
3324	case SUPPAGINGMODE_AMD64_NX:
3325	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3326	enmShadowMode = PGMMODE_NESTED_AMD64;
3327	break;
3328
3329	default:
3330	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode), PGMMODE_INVALID);
3331	}
3332	}
3333	}
3334	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3335	else
3336	{
3337	/* Nested paging is a requirement for nested VT-x. */
3338	AssertLogRelMsgReturn(enmGuestMode != PGMMODE_EPT, ("enmHostMode=%d\n", pVM->pgm.s.enmHostMode), PGMMODE_INVALID);
3339	}
3340	#endif
3341	}
3342
3343	return enmShadowMode;
3344	}
3345
3346
3347	/**
3348	* Performs the actual mode change.
3349	* This is called by PGMChangeMode and pgmR3InitPaging().
3350	*
3351	* @returns VBox status code. May suspend or power off the VM on error, but this
3352	* will trigger using FFs and not informational status codes.
3353	*
3354	* @param pVM The cross context VM structure.
3355	* @param pVCpu The cross context virtual CPU structure.
3356	* @param enmGuestMode The new guest mode. This is assumed to be different from
3357	* the current mode.
3358	* @param fForce Whether to force a shadow paging mode change.
3359	*/
3360	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode, bool fForce)
3361	{
3362	Log(("PGMHCChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3363	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3364
3365	/*
3366	* Calc the shadow mode and switcher.
3367	*/
3368	PGMMODE const enmShadowMode = pgmCalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode);
3369	bool const fShadowModeChanged = enmShadowMode != pVCpu->pgm.s.enmShadowMode \|\| fForce;
3370
3371	/*
3372	* Exit old mode(s).
3373	*/
3374	/* shadow */
3375	if (fShadowModeChanged)
3376	{
3377	LogFlow(("PGMHCChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3378	uintptr_t idxOldShw = pVCpu->pgm.s.idxShadowModeData;
3379	if ( idxOldShw < RT_ELEMENTS(g_aPgmShadowModeData)
3380	&& g_aPgmShadowModeData[idxOldShw].pfnExit)
3381	{
3382	int rc = g_aPgmShadowModeData[idxOldShw].pfnExit(pVCpu);
3383	AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3384	}
3385	}
3386	else
3387	LogFlow(("PGMHCChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3388
3389	/* guest */
3390	uintptr_t const idxOldGst = pVCpu->pgm.s.idxGuestModeData;
3391	if ( idxOldGst < RT_ELEMENTS(g_aPgmGuestModeData)
3392	&& g_aPgmGuestModeData[idxOldGst].pfnExit)
3393	{
3394	int rc = g_aPgmGuestModeData[idxOldGst].pfnExit(pVCpu);
3395	AssertMsgReturn(RT_SUCCESS(rc), ("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc), rc);
3396	}
3397	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
3398	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
3399	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
3400	Assert(!pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped));
3401
3402	/*
3403	* Change the paging mode data indexes.
3404	*/
3405	uintptr_t idxNewGst = pVCpu->pgm.s.idxGuestModeData = pgmModeToType(enmGuestMode);
3406	AssertReturn(idxNewGst < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
3407	AssertReturn(g_aPgmGuestModeData[idxNewGst].uType == idxNewGst, VERR_PGM_MODE_IPE);
3408	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnGetPage, VERR_PGM_MODE_IPE);
3409	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnModifyPage, VERR_PGM_MODE_IPE);
3410	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnExit, VERR_PGM_MODE_IPE);
3411	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnEnter, VERR_PGM_MODE_IPE);
3412	#ifdef IN_RING3
3413	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnRelocate, VERR_PGM_MODE_IPE);
3414	#endif
3415
3416	uintptr_t const idxNewShw = pVCpu->pgm.s.idxShadowModeData = pgmModeToType(enmShadowMode);
3417	AssertReturn(idxNewShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
3418	AssertReturn(g_aPgmShadowModeData[idxNewShw].uType == idxNewShw, VERR_PGM_MODE_IPE);
3419	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnGetPage, VERR_PGM_MODE_IPE);
3420	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnModifyPage, VERR_PGM_MODE_IPE);
3421	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnExit, VERR_PGM_MODE_IPE);
3422	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnEnter, VERR_PGM_MODE_IPE);
3423	#ifdef IN_RING3
3424	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnRelocate, VERR_PGM_MODE_IPE);
3425	#endif
3426
3427	uintptr_t const idxNewBth = pVCpu->pgm.s.idxBothModeData = (idxNewShw - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END + idxNewGst;
3428	AssertReturn(g_aPgmBothModeData[idxNewBth].uShwType == idxNewShw, VERR_PGM_MODE_IPE);
3429	AssertReturn(g_aPgmBothModeData[idxNewBth].uGstType == idxNewGst, VERR_PGM_MODE_IPE);
3430	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnInvalidatePage, VERR_PGM_MODE_IPE);
3431	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
3432	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
3433	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
3434	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnMapCR3, VERR_PGM_MODE_IPE);
3435	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
3436	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnEnter, VERR_PGM_MODE_IPE);
3437	#ifdef VBOX_STRICT
3438	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnAssertCR3, VERR_PGM_MODE_IPE);
3439	#endif
3440
3441	/*
3442	* Determine SLAT mode -before- entering the new shadow mode!
3443	*/
3444	pVCpu->pgm.s.enmGuestSlatMode = !CPUMIsGuestVmxEptPagingEnabled(pVCpu) ? PGMSLAT_DIRECT : PGMSLAT_EPT;
3445
3446	/*
3447	* Enter new shadow mode (if changed).
3448	*/
3449	if (fShadowModeChanged)
3450	{
3451	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3452	int rc = g_aPgmShadowModeData[idxNewShw].pfnEnter(pVCpu);
3453	AssertLogRelMsgRCReturnStmt(rc, ("Entering enmShadowMode=%s failed: %Rrc\n", PGMGetModeName(enmShadowMode), rc),
3454	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID, rc);
3455	}
3456
3457	/*
3458	* Always flag the necessary updates
3459	*/
3460	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3461
3462	/*
3463	* Enter the new guest and shadow+guest modes.
3464	*/
3465	/* Calc the new CR3 value. */
3466	RTGCPHYS GCPhysCR3;
3467	switch (enmGuestMode)
3468	{
3469	case PGMMODE_REAL:
3470	case PGMMODE_PROTECTED:
3471	GCPhysCR3 = NIL_RTGCPHYS;
3472	break;
3473
3474	case PGMMODE_32_BIT:
3475	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3476	break;
3477
3478	case PGMMODE_PAE_NX:
3479	case PGMMODE_PAE:
3480	if (!pVM->cpum.ro.GuestFeatures.fPae)
3481	#ifdef IN_RING3 /** @todo r=bird: wrong place, probably hasn't really worked for a while. */
3482	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3483	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3484	#else
3485	AssertLogRelMsgFailedReturn(("enmGuestMode=%s - Try enable PAE for the guest!\n", PGMGetModeName(enmGuestMode)), VERR_PGM_MODE_IPE);
3486
3487	#endif
3488	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3489	break;
3490
3491	#ifdef VBOX_WITH_64_BITS_GUESTS
3492	case PGMMODE_AMD64_NX:
3493	case PGMMODE_AMD64:
3494	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_AMD64_PAGE_MASK;
3495	break;
3496	#endif
3497	default:
3498	AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), VERR_PGM_MODE_IPE);
3499	}
3500
3501	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3502	/*
3503	* If a nested-guest is using EPT paging:
3504	* - Update the second-level address translation (SLAT) mode.
3505	* - Indicate that the CR3 is nested-guest physical address.
3506	*/
3507	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
3508	{
3509	if (PGMMODE_WITH_PAGING(enmGuestMode))
3510	{
3511	/*
3512	* Translate CR3 to its guest-physical address.
3513	* We don't use pgmGstSlatTranslateCr3() here as we want to update GCPhysNstGstCR3 -after-
3514	* switching modes to keep it consistent with how GCPhysCR3 is updated.
3515	*/
3516	PGMPTWALK Walk;
3517	PGMPTWALKGST GstWalk;
3518	int const rc = pgmGstSlatWalk(pVCpu, GCPhysCR3, false /* fIsLinearAddrValid /, 0 / GCPtrNested */, &Walk,
3519	&GstWalk);
3520	if (RT_SUCCESS(rc))
3521	{ /* likely */ }
3522	else
3523	{
3524	/*
3525	* SLAT failed but we avoid reporting this to the caller because the caller
3526	* is not supposed to fail. The only time the caller needs to indicate a
3527	* failure to software is when PAE paging is used by the nested-guest, but
3528	* we handle the PAE case separately (e.g., see VMX transition in IEM).
3529	* In all other cases, the failure will be indicated when CR3 tries to be
3530	* translated on the next linear-address memory access.
3531	* See Intel spec. 27.2.1 "EPT Overview".
3532	*/
3533	Log(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", GCPhysCR3, rc));
3534
3535	/* Trying to coax PGM to succeed for the time being... */
3536	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3537	pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3;
3538	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3539	HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3540	return VINF_SUCCESS;
3541	}
3542	pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3;
3543	GCPhysCR3 = Walk.GCPhys & X86_CR3_EPT_PAGE_MASK;
3544	}
3545	}
3546	else
3547	Assert(pVCpu->pgm.s.GCPhysNstGstCR3 == NIL_RTGCPHYS);
3548	#endif
3549
3550	/*
3551	* Enter the new guest mode.
3552	*/
3553	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3554	int rc = g_aPgmGuestModeData[idxNewGst].pfnEnter(pVCpu, GCPhysCR3);
3555	int rc2 = g_aPgmBothModeData[idxNewBth].pfnEnter(pVCpu, GCPhysCR3);
3556
3557	/* Set the new guest CR3 (and nested-guest CR3). */
3558	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3559
3560	/* status codes. */
3561	AssertRC(rc);
3562	AssertRC(rc2);
3563	if (RT_SUCCESS(rc))
3564	{
3565	rc = rc2;
3566	if (RT_SUCCESS(rc)) /* no informational status codes. */
3567	rc = VINF_SUCCESS;
3568	}
3569
3570	/*
3571	* Notify HM.
3572	*/
3573	HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3574	return rc;
3575	}
3576
3577
3578	/**
3579	* Called by CPUM or REM when CR0.WP changes to 1.
3580	*
3581	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3582	* @thread EMT
3583	*/
3584	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu)
3585	{
3586	/*
3587	* Netware WP0+RO+US hack cleanup when WP0 -> WP1.
3588	*
3589	* Use the counter to judge whether there might be pool pages with active
3590	* hacks in them. If there are, we will be running the risk of messing up
3591	* the guest by allowing it to write to read-only pages. Thus, we have to
3592	* clear the page pool ASAP if there is the slightest chance.
3593	*/
3594	if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
3595	{
3596	Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
3597
3598	Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
3599	pVCpu->pgm.s.cNetwareWp0Hacks = 0;
3600	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3601	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3602	}
3603	}
3604
3605
3606	/**
3607	* Gets the current guest paging mode.
3608	*
3609	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
3610	*
3611	* @returns The current paging mode.
3612	* @param pVCpu The cross context virtual CPU structure.
3613	*/
3614	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
3615	{
3616	return pVCpu->pgm.s.enmGuestMode;
3617	}
3618
3619
3620	/**
3621	* Gets the current shadow paging mode.
3622	*
3623	* @returns The current paging mode.
3624	* @param pVCpu The cross context virtual CPU structure.
3625	*/
3626	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
3627	{
3628	return pVCpu->pgm.s.enmShadowMode;
3629	}
3630
3631
3632	/**
3633	* Gets the current host paging mode.
3634	*
3635	* @returns The current paging mode.
3636	* @param pVM The cross context VM structure.
3637	*/
3638	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
3639	{
3640	switch (pVM->pgm.s.enmHostMode)
3641	{
3642	case SUPPAGINGMODE_32_BIT:
3643	case SUPPAGINGMODE_32_BIT_GLOBAL:
3644	return PGMMODE_32_BIT;
3645
3646	case SUPPAGINGMODE_PAE:
3647	case SUPPAGINGMODE_PAE_GLOBAL:
3648	return PGMMODE_PAE;
3649
3650	case SUPPAGINGMODE_PAE_NX:
3651	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3652	return PGMMODE_PAE_NX;
3653
3654	case SUPPAGINGMODE_AMD64:
3655	case SUPPAGINGMODE_AMD64_GLOBAL:
3656	return PGMMODE_AMD64;
3657
3658	case SUPPAGINGMODE_AMD64_NX:
3659	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3660	return PGMMODE_AMD64_NX;
3661
3662	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
3663	}
3664
3665	return PGMMODE_INVALID;
3666	}
3667
3668
3669	/**
3670	* Get mode name.
3671	*
3672	* @returns read-only name string.
3673	* @param enmMode The mode which name is desired.
3674	*/
3675	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
3676	{
3677	switch (enmMode)
3678	{
3679	case PGMMODE_REAL: return "Real";
3680	case PGMMODE_PROTECTED: return "Protected";
3681	case PGMMODE_32_BIT: return "32-bit";
3682	case PGMMODE_PAE: return "PAE";
3683	case PGMMODE_PAE_NX: return "PAE+NX";
3684	case PGMMODE_AMD64: return "AMD64";
3685	case PGMMODE_AMD64_NX: return "AMD64+NX";
3686	case PGMMODE_NESTED_32BIT: return "Nested-32";
3687	case PGMMODE_NESTED_PAE: return "Nested-PAE";
3688	case PGMMODE_NESTED_AMD64: return "Nested-AMD64";
3689	case PGMMODE_EPT: return "EPT";
3690	case PGMMODE_NONE: return "None";
3691	default: return "unknown mode value";
3692	}
3693	}
3694
3695
3696	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3697	/**
3698	* Gets the SLAT mode name.
3699	*
3700	* @returns The read-only SLAT mode descriptive string.
3701	* @param enmSlatMode The SLAT mode value.
3702	*/
3703	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode)
3704	{
3705	switch (enmSlatMode)
3706	{
3707	case PGMSLAT_DIRECT: return "Direct";
3708	case PGMSLAT_EPT: return "EPT";
3709	case PGMSLAT_32BIT: return "32-bit";
3710	case PGMSLAT_PAE: return "PAE";
3711	case PGMSLAT_AMD64: return "AMD64";
3712	default: return "Unknown";
3713	}
3714	}
3715	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
3716
3717
3718	/**
3719	* Gets the physical address represented in the guest CR3 as PGM sees it.
3720	*
3721	* This is mainly for logging and debugging.
3722	*
3723	* @returns PGM's guest CR3 value.
3724	* @param pVCpu The cross context virtual CPU structure.
3725	*/
3726	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu)
3727	{
3728	return pVCpu->pgm.s.GCPhysCR3;
3729	}
3730
3731
3732
3733	/**
3734	* Notification from CPUM that the EFER.NXE bit has changed.
3735	*
3736	* @param pVCpu The cross context virtual CPU structure of the CPU for
3737	* which EFER changed.
3738	* @param fNxe The new NXE state.
3739	*/
3740	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
3741	{
3742	/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
3743	Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
3744
3745	pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
3746	if (fNxe)
3747	{
3748	/pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A /
3749	pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
3750	pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
3751	pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3752	/pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A /
3753	pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
3754	pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
3755	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3756	pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
3757	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
3758	pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
3759
3760	pVCpu->pgm.s.fGst64ShadowedPteMask \|= X86_PTE_PAE_NX;
3761	pVCpu->pgm.s.fGst64ShadowedPdeMask \|= X86_PDE_PAE_NX;
3762	pVCpu->pgm.s.fGst64ShadowedBigPdeMask \|= X86_PDE2M_PAE_NX;
3763	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask \|= X86_PDE2M_PAE_NX;
3764	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask \|= X86_PDPE_LM_NX;
3765	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask \|= X86_PML4E_NX;
3766	}
3767	else
3768	{
3769	/pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A /
3770	pVCpu->pgm.s.fGstPaeMbzPteMask \|= X86_PTE_PAE_NX;
3771	pVCpu->pgm.s.fGstPaeMbzPdeMask \|= X86_PDE_PAE_NX;
3772	pVCpu->pgm.s.fGstPaeMbzBigPdeMask \|= X86_PDE2M_PAE_NX;
3773	/pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A /
3774	pVCpu->pgm.s.fGstAmd64MbzPteMask \|= X86_PTE_PAE_NX;
3775	pVCpu->pgm.s.fGstAmd64MbzPdeMask \|= X86_PDE_PAE_NX;
3776	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask \|= X86_PDE2M_PAE_NX;
3777	pVCpu->pgm.s.fGstAmd64MbzPdpeMask \|= X86_PDPE_LM_NX;
3778	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask \|= X86_PDPE_LM_NX;
3779	pVCpu->pgm.s.fGstAmd64MbzPml4eMask \|= X86_PML4E_NX;
3780
3781	pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
3782	pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
3783	pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
3784	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
3785	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
3786	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
3787	}
3788	}
3789
3790
3791	/**
3792	* Check if any pgm pool pages are marked dirty (not monitored)
3793	*
3794	* @returns bool locked/not locked
3795	* @param pVM The cross context VM structure.
3796	*/
3797	VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
3798	{
3799	return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
3800	}
3801
3802
3803	/**
3804	* Check if this VCPU currently owns the PGM lock.
3805	*
3806	* @returns bool owner/not owner
3807	* @param pVM The cross context VM structure.
3808	*/
3809	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM)
3810	{
3811	return PDMCritSectIsOwner(pVM, &pVM->pgm.s.CritSectX);
3812	}
3813
3814
3815	/**
3816	* Enable or disable large page usage
3817	*
3818	* @returns VBox status code.
3819	* @param pVM The cross context VM structure.
3820	* @param fUseLargePages Use/not use large pages
3821	*/
3822	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages)
3823	{
3824	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3825
3826	pVM->pgm.s.fUseLargePages = fUseLargePages;
3827	return VINF_SUCCESS;
3828	}
3829
3830
3831	/**
3832	* Acquire the PGM lock.
3833	*
3834	* @returns VBox status code
3835	* @param pVM The cross context VM structure.
3836	* @param fVoid Set if the caller cannot handle failure returns.
3837	* @param SRC_POS The source position of the caller (RT_SRC_POS).
3838	*/
3839	#if defined(VBOX_STRICT) \|\| defined(DOXYGEN_RUNNING)
3840	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL)
3841	#else
3842	int pgmLock(PVMCC pVM, bool fVoid)
3843	#endif
3844	{
3845	#if defined(VBOX_STRICT)
3846	int rc = PDMCritSectEnterDebug(pVM, &pVM->pgm.s.CritSectX, VINF_SUCCESS, (uintptr_t)ASMReturnAddress(), RT_SRC_POS_ARGS);
3847	#else
3848	int rc = PDMCritSectEnter(pVM, &pVM->pgm.s.CritSectX, VINF_SUCCESS);
3849	#endif
3850	if (RT_SUCCESS(rc))
3851	return rc;
3852	if (fVoid)
3853	PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pgm.s.CritSectX, rc);
3854	else
3855	AssertRC(rc);
3856	return rc;
3857	}
3858
3859
3860	/**
3861	* Release the PGM lock.
3862	*
3863	* @param pVM The cross context VM structure.
3864	*/
3865	void pgmUnlock(PVMCC pVM)
3866	{
3867	uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
3868	pVM->pgm.s.cDeprecatedPageLocks = 0;
3869	int rc = PDMCritSectLeave(pVM, &pVM->pgm.s.CritSectX);
3870	if (rc == VINF_SEM_NESTED)
3871	pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
3872	}
3873
3874
3875	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
3876
3877	/** Format handler for PGMPAGE.
3878	* @copydoc FNRTSTRFORMATTYPE */
3879	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3880	const char pszType, void const pvValue,
3881	int cchWidth, int cchPrecision, unsigned fFlags,
3882	void *pvUser)
3883	{
3884	size_t cch;
3885	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
3886	if (RT_VALID_PTR(pPage))
3887	{
3888	char szTmp[64+80];
3889
3890	cch = 0;
3891
3892	/* The single char state stuff. */
3893	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
3894	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
3895
3896	# define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
3897	if (IS_PART_INCLUDED(5))
3898	{
3899	static const char s_achHandlerStates[4*2] = { '-', 't', 'w', 'a' , '_', 'T', 'W', 'A' };
3900	szTmp[cch++] = s_achHandlerStates[ PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)
3901	\| ((uint8_t)PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage) << 2)];
3902	}
3903
3904	/* The type. */
3905	if (IS_PART_INCLUDED(4))
3906	{
3907	szTmp[cch++] = ':';
3908	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
3909	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
3910	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
3911	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
3912	}
3913
3914	/* The numbers. */
3915	if (IS_PART_INCLUDED(3))
3916	{
3917	szTmp[cch++] = ':';
3918	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
3919	}
3920
3921	if (IS_PART_INCLUDED(2))
3922	{
3923	szTmp[cch++] = ':';
3924	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
3925	}
3926
3927	if (IS_PART_INCLUDED(6))
3928	{
3929	szTmp[cch++] = ':';
3930	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
3931	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
3932	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
3933	}
3934	# undef IS_PART_INCLUDED
3935
3936	cch = pfnOutput(pvArgOutput, szTmp, cch);
3937	#if 0
3938	size_t cch2 = 0;
3939	szTmp[cch2++] = '(';
3940	cch2 += RTStrFormatNumber(&szTmp[cch2], (uintptr_t)pPage, 16, 18, 0, RTSTR_F_SPECIAL \| RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
3941	szTmp[cch2++] = ')';
3942	szTmp[cch2] = '\0';
3943	cch += pfnOutput(pvArgOutput, szTmp, cch2);
3944	#endif
3945	}
3946	else
3947	cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmpage-ptr>"));
3948	NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
3949	return cch;
3950	}
3951
3952
3953	/** Format handler for PGMRAMRANGE.
3954	* @copydoc FNRTSTRFORMATTYPE */
3955	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3956	const char pszType, void const pvValue,
3957	int cchWidth, int cchPrecision, unsigned fFlags,
3958	void *pvUser)
3959	{
3960	size_t cch;
3961	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
3962	if (RT_VALID_PTR(pRam))
3963	{
3964	char szTmp[80];
3965	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
3966	cch = pfnOutput(pvArgOutput, szTmp, cch);
3967	}
3968	else
3969	cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmramrange-ptr>"));
3970	NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
3971	return cch;
3972	}
3973
3974	/** Format type andlers to be registered/deregistered. */
3975	static const struct
3976	{
3977	char szType[24];
3978	PFNRTSTRFORMATTYPE pfnHandler;
3979	} g_aPgmFormatTypes[] =
3980	{
3981	{ "pgmpage", pgmFormatTypeHandlerPage },
3982	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
3983	};
3984
3985	#endif /* !IN_R0 \|\| LOG_ENABLED */
3986
3987	/**
3988	* Registers the global string format types.
3989	*
3990	* This should be called at module load time or in some other manner that ensure
3991	* that it's called exactly one time.
3992	*
3993	* @returns IPRT status code on RTStrFormatTypeRegister failure.
3994	*/
3995	VMMDECL(int) PGMRegisterStringFormatTypes(void)
3996	{
3997	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
3998	int rc = VINF_SUCCESS;
3999	unsigned i;
4000	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
4001	{
4002	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
4003	# ifdef IN_RING0
4004	if (rc == VERR_ALREADY_EXISTS)
4005	{
4006	/* in case of cleanup failure in ring-0 */
4007	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4008	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
4009	}
4010	# endif
4011	}
4012	if (RT_FAILURE(rc))
4013	while (i-- > 0)
4014	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4015
4016	return rc;
4017	#else
4018	return VINF_SUCCESS;
4019	#endif
4020	}
4021
4022
4023	/**
4024	* Deregisters the global string format types.
4025	*
4026	* This should be called at module unload time or in some other manner that
4027	* ensure that it's called exactly one time.
4028	*/
4029	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
4030	{
4031	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
4032	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
4033	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4034	#endif
4035	}
4036
4037
4038	#ifdef VBOX_STRICT
4039	/**
4040	* Asserts that everything related to the guest CR3 is correctly shadowed.
4041	*
4042	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
4043	* and assert the correctness of the guest CR3 mapping before asserting that the
4044	* shadow page tables is in sync with the guest page tables.
4045	*
4046	* @returns Number of conflicts.
4047	* @param pVM The cross context VM structure.
4048	* @param pVCpu The cross context virtual CPU structure.
4049	* @param cr3 The current guest CR3 register value.
4050	* @param cr4 The current guest CR4 register value.
4051	*/
4052	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4)
4053	{
4054	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
4055
4056	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
4057	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), -VERR_PGM_MODE_IPE);
4058	AssertReturn(g_aPgmBothModeData[idxBth].pfnAssertCR3, -VERR_PGM_MODE_IPE);
4059
4060	PGM_LOCK_VOID(pVM);
4061	unsigned cErrors = g_aPgmBothModeData[idxBth].pfnAssertCR3(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
4062	PGM_UNLOCK(pVM);
4063
4064	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
4065	return cErrors;
4066	}
4067	#endif /* VBOX_STRICT */
4068
4069
4070	/**
4071	* Updates PGM's copy of the guest's EPT pointer.
4072	*
4073	* @param pVCpu The cross context virtual CPU structure.
4074	* @param uEptPtr The EPT pointer.
4075	*
4076	* @remarks This can be called as part of VM-entry so we might be in the midst of
4077	* switching to VMX non-root mode.
4078	*/
4079	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr)
4080	{
4081	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4082	PGM_LOCK_VOID(pVM);
4083	pVCpu->pgm.s.uEptPtr = uEptPtr;
4084	pVCpu->pgm.s.pGstEptPml4R3 = 0;
4085	pVCpu->pgm.s.pGstEptPml4R0 = 0;
4086	PGM_UNLOCK(pVM);
4087	}
4088
4089	#ifdef PGM_WITH_PAGE_ZEROING_DETECTION
4090
4091	/**
4092	* Helper for checking whether XMM0 is zero, possibly retriving external state.
4093	*/
4094	static bool pgmHandlePageZeroingIsXmm0Zero(PVMCPUCC pVCpu, PCPUMCTX pCtx)
4095	{
4096	if (pCtx->fExtrn & CPUMCTX_EXTRN_SSE_AVX)
4097	{
4098	int rc = CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_SSE_AVX);
4099	AssertRCReturn(rc, false);
4100	}
4101	return pCtx->XState.x87.aXMM[0].au64[0] == 0
4102	&& pCtx->XState.x87.aXMM[0].au64[1] == 0
4103	&& pCtx->XState.x87.aXMM[0].au64[2] == 0
4104	&& pCtx->XState.x87.aXMM[0].au64[3] == 0;
4105	}
4106
4107
4108	/**
4109	* Helper for comparing opcode bytes.
4110	*/
4111	static bool pgmHandlePageZeroingMatchOpcodes(PVMCPUCC pVCpu, PCPUMCTX pCtx, uint8_t const *pbOpcodes, uint32_t cbOpcodes)
4112	{
4113	uint8_t abTmp[64];
4114	AssertMsgReturn(cbOpcodes <= sizeof(abTmp), ("cbOpcodes=%#x\n", cbOpcodes), false);
4115	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abTmp, pCtx->rip + pCtx->cs.u64Base, cbOpcodes);
4116	if (RT_SUCCESS(rc))
4117	return memcmp(abTmp, pbOpcodes, cbOpcodes) == 0;
4118	return false;
4119	}
4120
4121
4122	/**
4123	* Called on faults on ZERO pages to check if the guest is trying to zero it.
4124	*
4125	* Since it's a waste of time to zero a ZERO page and it will cause an
4126	* unnecessary page allocation, we'd like to detect and avoid this.
4127	* If any known page zeroing code is detected, this function will update the CPU
4128	* state to pretend the page was zeroed by the code.
4129	*
4130	* @returns true if page zeroing code was detected and CPU state updated to skip
4131	* the code.
4132	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
4133	* @param pCtx The guest register context.
4134	*/
4135	static bool pgmHandlePageZeroingCode(PVMCPUCC pVCpu, PCPUMCTX pCtx)
4136	{
4137	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
4138
4139	/*
4140	* Sort by mode first.
4141	*/
4142	if (CPUMIsGuestInLongModeEx(pCtx))
4143	{
4144	if (CPUMIsGuestIn64BitCodeEx(pCtx))
4145	{
4146	/*
4147	* 64-bit code.
4148	*/
4149	Log9(("pgmHandlePageZeroingCode: not page zeroing - 64-bit\n"));
4150	}
4151	else if (pCtx->cs.Attr.n.u1DefBig)
4152	Log9(("pgmHandlePageZeroingCode: not page zeroing - 32-bit lm\n"));
4153	else
4154	Log9(("pgmHandlePageZeroingCode: not page zeroing - 16-bit lm\n"));
4155	}
4156	else if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
4157	{
4158	if (pCtx->cs.Attr.n.u1DefBig)
4159	{
4160	/*
4161	* 32-bit paged protected mode code.
4162	*/
4163	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX \| CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RBX
4164	\| CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP \| CPUMCTX_EXTRN_RSI \| CPUMCTX_EXTRN_RDI
4165	\| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
4166
4167	/* 1. Generic 'rep stosd' detection. */
4168	static uint8_t const s_abRepStosD[] = { 0xf3, 0xab };
4169	if ( pCtx->eax == 0
4170	&& pCtx->ecx == X86_PAGE_SIZE / 4
4171	&& !(pCtx->edi & X86_PAGE_OFFSET_MASK)
4172	&& pgmHandlePageZeroingMatchOpcodes(pVCpu, pCtx, s_abRepStosD, sizeof(s_abRepStosD)))
4173	{
4174	pCtx->ecx = 0;
4175	pCtx->edi += X86_PAGE_SIZE;
4176	Log9(("pgmHandlePageZeroingCode: REP STOSD: eip=%RX32 -> %RX32\n", pCtx->eip, pCtx->eip + sizeof(s_abRepStosD)));
4177	pCtx->eip += sizeof(s_abRepStosD);
4178	return true;
4179	}
4180
4181	/* 2. Windows 2000 sp4 KiXMMIZeroPageNoSave loop code: */
4182	static uint8_t const s_abW2kSp4XmmZero[] =
4183	{
4184	0x0f, 0x2b, 0x01,
4185	0x0f, 0x2b, 0x41, 0x10,
4186	0x0f, 0x2b, 0x41, 0x20,
4187	0x0f, 0x2b, 0x41, 0x30,
4188	0x83, 0xc1, 0x40,
4189	0x48,
4190	0x75, 0xeb,
4191	};
4192	if ( pCtx->eax == 64
4193	&& !(pCtx->ecx & X86_PAGE_OFFSET_MASK)
4194	&& pgmHandlePageZeroingMatchOpcodes(pVCpu, pCtx, s_abW2kSp4XmmZero, sizeof(s_abW2kSp4XmmZero))
4195	&& pgmHandlePageZeroingIsXmm0Zero(pVCpu, pCtx))
4196	{
4197	pCtx->eax = 1;
4198	pCtx->ecx += X86_PAGE_SIZE;
4199	Log9(("pgmHandlePageZeroingCode: w2k sp4 xmm: eip=%RX32 -> %RX32\n",
4200	pCtx->eip, pCtx->eip + sizeof(s_abW2kSp4XmmZero) - 3));
4201	pCtx->eip += sizeof(s_abW2kSp4XmmZero) - 3;
4202	return true;
4203	}
4204	Log9(("pgmHandlePageZeroingCode: not page zeroing - 32-bit\n"));
4205	}
4206	else if (!pCtx->eflags.Bits.u1VM)
4207	Log9(("pgmHandlePageZeroingCode: not page zeroing - 16-bit\n"));
4208	else
4209	Log9(("pgmHandlePageZeroingCode: not page zeroing - v86\n"));
4210	}
4211	return false;
4212	}
4213
4214	#endif /* PGM_WITH_PAGE_ZEROING_DETECTION */

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