| 1 | /* $Id: PDMAll.cpp 100108 2023-06-07 20:05:13Z vboxsync $ */
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| 2 | /** @file
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| 3 | * PDM Critical Sections
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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| 32 | #define LOG_GROUP LOG_GROUP_PDM
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| 33 | #include "PDMInternal.h"
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| 34 | #include <VBox/vmm/pdm.h>
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| 35 | #include <VBox/vmm/mm.h>
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| 36 | #include <VBox/vmm/vmcc.h>
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| 37 | #include <VBox/err.h>
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| 38 | #ifdef VBOX_VMM_TARGET_ARMV8
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| 39 | # include <VBox/vmm/gic.h>
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| 40 | #else
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| 41 | # include <VBox/vmm/apic.h>
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| 42 | #endif
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| 43 |
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| 44 | #include <VBox/log.h>
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| 45 | #include <iprt/asm.h>
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| 46 | #include <iprt/assert.h>
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| 47 |
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| 48 | #include "PDMInline.h"
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| 49 | #include "dtrace/VBoxVMM.h"
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| 50 |
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| 51 |
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| 52 | #if !defined(VBOX_VMM_TARGET_ARMV8)
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| 53 | /**
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| 54 | * Gets the pending interrupt.
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| 55 | *
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| 56 | * @returns VBox status code.
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| 57 | * @retval VINF_SUCCESS on success.
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| 58 | * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
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| 59 | * can't be delivered due to TPR priority.
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| 60 | * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
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| 61 | * has been software-disabled since it flagged something was pending,
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| 62 | * or other reasons).
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| 63 | *
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| 64 | * @param pVCpu The cross context virtual CPU structure.
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| 65 | * @param pu8Interrupt Where to store the interrupt.
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| 66 | */
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| 67 | VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
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| 68 | {
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| 69 | /*
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| 70 | * The local APIC has a higher priority than the PIC.
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| 71 | */
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| 72 | int rc = VERR_NO_DATA;
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| 73 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
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| 74 | {
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| 75 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
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| 76 |
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| 77 | uint32_t uTagSrc;
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| 78 | rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
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| 79 | if (RT_SUCCESS(rc))
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| 80 | {
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| 81 | VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
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| 82 | Log8(("PDMGetInterrupt: irq=%#x tag=%#x (apic)\n", *pu8Interrupt, uTagSrc));
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| 83 | return VINF_SUCCESS;
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| 84 | }
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| 85 | /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
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| 86 | interrupts shouldn't prevent ExtINT from being delivered. */
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| 87 | }
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| 88 |
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| 89 | PVMCC pVM = pVCpu->CTX_SUFF(pVM);
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| 90 | pdmLock(pVM);
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| 91 |
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| 92 | /*
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| 93 | * Check the PIC.
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| 94 | */
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| 95 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
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| 96 | {
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| 97 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
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| 98 | Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
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| 99 | Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
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| 100 | uint32_t uTagSrc;
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| 101 | int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
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| 102 | AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
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| 103 | if (i >= 0)
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| 104 | {
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| 105 | pdmUnlock(pVM);
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| 106 | *pu8Interrupt = (uint8_t)i;
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| 107 | VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
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| 108 | Log8(("PDMGetInterrupt: irq=%#x tag=%#x (pic)\n", i, uTagSrc));
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| 109 | return VINF_SUCCESS;
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| 110 | }
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| 111 | }
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| 112 |
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| 113 | /*
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| 114 | * One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
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| 115 | * got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
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| 116 | * force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
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| 117 | * without returning a valid interrupt still needs to be handled for the TPR masked case,
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| 118 | * so we shall just handle it here regardless if we choose to update the APIC code in the future.
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| 119 | */
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| 120 |
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| 121 | pdmUnlock(pVM);
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| 122 | return rc;
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| 123 | }
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| 124 | #endif
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| 125 |
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| 126 |
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| 127 | /**
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| 128 | * Sets the pending interrupt coming from ISA source or HPET.
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| 129 | *
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| 130 | * @returns VBox status code.
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| 131 | * @param pVM The cross context VM structure.
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| 132 | * @param u8Irq The IRQ line.
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| 133 | * @param u8Level The new level.
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| 134 | * @param uTagSrc The IRQ tag and source tracer ID.
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| 135 | */
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| 136 | VMMDECL(int) PDMIsaSetIrq(PVMCC pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
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| 137 | {
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| 138 | pdmLock(pVM);
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| 139 |
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| 140 | /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
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| 141 | if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
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| 142 | {
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| 143 | if (u8Level == PDM_IRQ_LEVEL_HIGH)
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| 144 | VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
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| 145 | else
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| 146 | VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
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| 147 | }
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| 148 | Log9(("PDMIsaSetIrq: irq=%#x lvl=%u tag=%#x\n", u8Irq, u8Level, uTagSrc));
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| 149 |
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| 150 | #ifdef VBOX_VMM_TARGET_ARMV8
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| 151 | int rc = VINF_SUCCESS;
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| 152 | GICSpiSet(pVM, u8Irq, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
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| 153 | #else
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| 154 | int rc = VERR_PDM_NO_PIC_INSTANCE;
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| 155 | /** @todo r=bird: This code is incorrect, as it ASSUMES the PIC and I/O APIC
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| 156 | * are always ring-0 enabled! */
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| 157 | if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
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| 158 | {
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| 159 | Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
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| 160 | pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
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| 161 | rc = VINF_SUCCESS;
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| 162 | }
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| 163 |
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| 164 | if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
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| 165 | {
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| 166 | Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
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| 167 |
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| 168 | /*
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| 169 | * Apply Interrupt Source Override rules.
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| 170 | * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
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| 171 | * interrupt source override.
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| 172 | * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
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| 173 | * notably recent OS X rely upon this configuration.
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| 174 | * If changing, also update override rules in MADT and MPS.
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| 175 | */
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| 176 | /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
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| 177 | if (u8Irq == 0)
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| 178 | u8Irq = 2;
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| 179 |
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| 180 | pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), NIL_PCIBDF, u8Irq, u8Level, uTagSrc);
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| 181 | rc = VINF_SUCCESS;
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| 182 | }
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| 183 | #endif
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| 184 |
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| 185 | if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
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| 186 | VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
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| 187 | pdmUnlock(pVM);
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| 188 | return rc;
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| 189 | }
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| 190 |
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| 191 |
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| 192 | /**
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| 193 | * Sets the pending I/O APIC interrupt.
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| 194 | *
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| 195 | * @returns VBox status code.
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| 196 | * @param pVM The cross context VM structure.
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| 197 | * @param u8Irq The IRQ line.
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| 198 | * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
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| 199 | * Pass NIL_PCIBDF when it's not a PCI device or interrupt.
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| 200 | * @param u8Level The new level.
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| 201 | * @param uTagSrc The IRQ tag and source tracer ID.
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| 202 | */
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| 203 | VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
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| 204 | {
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| 205 | Log9(("PDMIoApicSetIrq: irq=%#x lvl=%u tag=%#x src=%#x\n", u8Irq, u8Level, uTagSrc, uBusDevFn));
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| 206 |
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| 207 | #ifdef VBOX_VMM_TARGET_ARMV8
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| 208 | RT_NOREF(uBusDevFn, uTagSrc);
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| 209 | GICSpiSet(pVM, u8Irq, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
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| 210 | return VINF_SUCCESS;
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| 211 | #else
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| 212 | if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
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| 213 | {
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| 214 | Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
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| 215 | pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, u8Irq, u8Level, uTagSrc);
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| 216 | return VINF_SUCCESS;
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| 217 | }
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| 218 | return VERR_PDM_NO_PIC_INSTANCE;
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| 219 | #endif
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| 220 | }
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| 221 |
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| 222 |
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| 223 | /**
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| 224 | * Broadcasts an EOI to the I/O APIC(s).
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| 225 | *
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| 226 | * @param pVM The cross context VM structure.
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| 227 | * @param uVector The interrupt vector corresponding to the EOI.
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| 228 | */
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| 229 | VMM_INT_DECL(void) PDMIoApicBroadcastEoi(PVMCC pVM, uint8_t uVector)
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| 230 | {
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| 231 | /*
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| 232 | * At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
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| 233 | * multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs.
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| 234 | */
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| 235 | PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
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| 236 | #ifdef IN_RING0
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| 237 | if (pIoApic->pDevInsR0)
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| 238 | {
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| 239 | Assert(pIoApic->pfnSetEoiR0);
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| 240 | pIoApic->pfnSetEoiR0(pIoApic->pDevInsR0, uVector);
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| 241 | }
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| 242 | else if (pIoApic->pDevInsR3)
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| 243 | {
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| 244 | /* Queue for ring-3 execution. */
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| 245 | PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
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| 246 | if (pTask)
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| 247 | {
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| 248 | pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_EOI;
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| 249 | pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
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| 250 | pTask->u.IoApicSetEoi.uVector = uVector;
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| 251 | PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
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| 252 | }
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| 253 | else
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| 254 | AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
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| 255 | }
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| 256 | #else
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| 257 | if (pIoApic->pDevInsR3)
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| 258 | {
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| 259 | Assert(pIoApic->pfnSetEoiR3);
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| 260 | pIoApic->pfnSetEoiR3(pIoApic->pDevInsR3, uVector);
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| 261 | }
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| 262 | #endif
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| 263 | }
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| 264 |
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| 265 |
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| 266 | /**
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| 267 | * Send a MSI to an I/O APIC.
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| 268 | *
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| 269 | * @param pVM The cross context VM structure.
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| 270 | * @param uBusDevFn The bus:device:function of the device initiating the MSI.
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| 271 | * @param pMsi The MSI to send.
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| 272 | * @param uTagSrc The IRQ tag and source tracer ID.
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| 273 | */
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| 274 | VMM_INT_DECL(void) PDMIoApicSendMsi(PVMCC pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
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| 275 | {
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| 276 | Log9(("PDMIoApicSendMsi: addr=%#RX64 data=%#RX32 tag=%#x src=%#x\n", pMsi->Addr.u64, pMsi->Data.u32, uTagSrc, uBusDevFn));
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| 277 | PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
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| 278 | #ifdef IN_RING0
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| 279 | if (pIoApic->pDevInsR0)
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| 280 | pIoApic->pfnSendMsiR0(pIoApic->pDevInsR0, uBusDevFn, pMsi, uTagSrc);
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| 281 | else if (pIoApic->pDevInsR3)
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| 282 | {
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| 283 | /* Queue for ring-3 execution. */
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| 284 | PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
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| 285 | if (pTask)
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| 286 | {
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| 287 | pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SEND_MSI;
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| 288 | pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
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| 289 | pTask->u.IoApicSendMsi.uBusDevFn = uBusDevFn;
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| 290 | pTask->u.IoApicSendMsi.Msi = *pMsi;
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| 291 | pTask->u.IoApicSendMsi.uTagSrc = uTagSrc;
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| 292 | PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
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| 293 | }
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| 294 | else
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| 295 | AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
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| 296 | }
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| 297 | #else
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| 298 | if (pIoApic->pDevInsR3)
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| 299 | {
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| 300 | Assert(pIoApic->pfnSendMsiR3);
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| 301 | pIoApic->pfnSendMsiR3(pIoApic->pDevInsR3, uBusDevFn, pMsi, uTagSrc);
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| 302 | }
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| 303 | #endif
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| 304 | }
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| 305 |
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| 306 |
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| 307 |
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| 308 | /**
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| 309 | * Returns the presence of an IO-APIC.
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| 310 | *
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| 311 | * @returns true if an IO-APIC is present.
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| 312 | * @param pVM The cross context VM structure.
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| 313 | */
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| 314 | VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
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| 315 | {
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| 316 | return pVM->pdm.s.IoApic.pDevInsR3 != NULL;
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| 317 | }
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| 318 |
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| 319 |
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| 320 | /**
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| 321 | * Returns the presence of an APIC.
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| 322 | *
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| 323 | * @returns true if an APIC is present.
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| 324 | * @param pVM The cross context VM structure.
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| 325 | */
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| 326 | VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
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| 327 | {
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| 328 | return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
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| 329 | }
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| 330 |
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| 331 |
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| 332 | /**
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| 333 | * Translates a ring-0 device instance index to a pointer.
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| 334 | *
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| 335 | * This is used by PGM for device access handlers.
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| 336 | *
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| 337 | * @returns Device instance pointer if valid index, otherwise NULL (asserted).
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| 338 | * @param pVM The cross context VM structure.
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| 339 | * @param idxR0Device The ring-0 device instance index.
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| 340 | */
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| 341 | VMM_INT_DECL(PPDMDEVINS) PDMDeviceRing0IdxToInstance(PVMCC pVM, uint64_t idxR0Device)
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| 342 | {
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| 343 | #ifdef IN_RING0
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| 344 | AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdmr0.s.apDevInstances), ("%#RX64\n", idxR0Device), NULL);
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| 345 | PPDMDEVINS pDevIns = pVM->pdmr0.s.apDevInstances[idxR0Device];
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| 346 | #elif defined(IN_RING3)
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| 347 | AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdm.s.apDevRing0Instances), ("%#RX64\n", idxR0Device), NULL);
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| 348 | PPDMDEVINS pDevIns = pVM->pdm.s.apDevRing0Instances[idxR0Device];
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| 349 | #else
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| 350 | # error "Unsupported context"
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| 351 | #endif
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| 352 | AssertMsg(pDevIns, ("%#RX64\n", idxR0Device));
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| 353 | return pDevIns;
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| 354 | }
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| 355 |
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| 356 |
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| 357 | /**
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| 358 | * Locks PDM.
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| 359 | *
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| 360 | * This might block.
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| 361 | *
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| 362 | * @param pVM The cross context VM structure.
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| 363 | */
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| 364 | void pdmLock(PVMCC pVM)
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| 365 | {
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| 366 | int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VINF_SUCCESS);
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| 367 | PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pdm.s.CritSect, rc);
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| 368 | }
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| 369 |
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| 370 |
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| 371 | /**
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| 372 | * Locks PDM but don't go to ring-3 if it's owned by someone.
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| 373 | *
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| 374 | * @returns VINF_SUCCESS on success.
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| 375 | * @returns rc if we're in GC or R0 and can't get the lock.
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| 376 | * @param pVM The cross context VM structure.
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| 377 | * @param rcBusy The RC to return in GC or R0 when we can't get the lock.
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| 378 | */
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| 379 | int pdmLockEx(PVMCC pVM, int rcBusy)
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| 380 | {
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| 381 | return PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, rcBusy);
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| 382 | }
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| 383 |
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| 384 |
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| 385 | /**
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| 386 | * Unlocks PDM.
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| 387 | *
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| 388 | * @param pVM The cross context VM structure.
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| 389 | */
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| 390 | void pdmUnlock(PVMCC pVM)
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| 391 | {
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| 392 | PDMCritSectLeave(pVM, &pVM->pdm.s.CritSect);
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| 393 | }
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| 394 |
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| 395 |
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| 396 | /**
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| 397 | * Checks if this thread is owning the PDM lock.
|
|---|
| 398 | *
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| 399 | * @returns @c true if the lock is taken, @c false otherwise.
|
|---|
| 400 | * @param pVM The cross context VM structure.
|
|---|
| 401 | */
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|---|
| 402 | bool pdmLockIsOwner(PVMCC pVM)
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|---|
| 403 | {
|
|---|
| 404 | return PDMCritSectIsOwner(pVM, &pVM->pdm.s.CritSect);
|
|---|
| 405 | }
|
|---|
| 406 |
|
|---|
| 407 |
|
|---|
| 408 | /**
|
|---|
| 409 | * Converts ring 3 VMM heap pointer to a guest physical address
|
|---|
| 410 | *
|
|---|
| 411 | * @returns VBox status code.
|
|---|
| 412 | * @param pVM The cross context VM structure.
|
|---|
| 413 | * @param pv Ring-3 pointer.
|
|---|
| 414 | * @param pGCPhys GC phys address (out).
|
|---|
| 415 | */
|
|---|
| 416 | VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
|
|---|
| 417 | {
|
|---|
| 418 | if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
|
|---|
| 419 | {
|
|---|
| 420 | RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
|
|---|
| 421 | if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
|
|---|
| 422 | {
|
|---|
| 423 | *pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
|
|---|
| 424 | return VINF_SUCCESS;
|
|---|
| 425 | }
|
|---|
| 426 |
|
|---|
| 427 | /* Don't assert here as this is called before we can catch ring-0 assertions. */
|
|---|
| 428 | Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
|
|---|
| 429 | pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
|
|---|
| 430 | }
|
|---|
| 431 | else
|
|---|
| 432 | Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
|
|---|
| 433 | return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
|
|---|
| 434 | }
|
|---|
| 435 |
|
|---|
| 436 |
|
|---|
| 437 | /**
|
|---|
| 438 | * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
|
|---|
| 439 | *
|
|---|
| 440 | * @returns dev heap enabled status (true/false)
|
|---|
| 441 | * @param pVM The cross context VM structure.
|
|---|
| 442 | */
|
|---|
| 443 | VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
|
|---|
| 444 | {
|
|---|
| 445 | return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
|
|---|
| 446 | }
|
|---|
