VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncs.cpp@ 103739

Last change on this file since 103739 was 103739, checked in by vboxsync, 3 months ago

VMM/IEM: Implemented native emitter for ADD instructions taking immediates. bugref:10376
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 35.2 KB
Line 
1/* $Id: IEMAllThrdFuncs.cpp 103739 2024-03-09 00:03:05Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, Threaded Functions.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33# define LOG_GROUP LOG_GROUP_IEM
34#endif
35#define VMCPU_INCL_CPUM_GST_CTX
36#define IEM_WITH_OPAQUE_DECODER_STATE
37#include <VBox/vmm/iem.h>
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/apic.h>
40#include <VBox/vmm/pdm.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/iom.h>
43#include <VBox/vmm/em.h>
44#include <VBox/vmm/hm.h>
45#include <VBox/vmm/nem.h>
46#include <VBox/vmm/gim.h>
47#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
48# include <VBox/vmm/em.h>
49# include <VBox/vmm/hm_svm.h>
50#endif
51#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
52# include <VBox/vmm/hmvmxinline.h>
53#endif
54#include <VBox/vmm/tm.h>
55#include <VBox/vmm/dbgf.h>
56#include <VBox/vmm/dbgftrace.h>
57#include "IEMInternal.h"
58#include <VBox/vmm/vmcc.h>
59#include <VBox/log.h>
60#include <VBox/err.h>
61#include <VBox/param.h>
62#include <VBox/dis.h>
63#include <VBox/disopcode-x86-amd64.h>
64#include <iprt/asm-math.h>
65#include <iprt/assert.h>
66#include <iprt/string.h>
67#include <iprt/x86.h>
68
69#include "IEMInline.h"
70#include "IEMMc.h"
71
72#include "IEMThreadedFunctions.h"
73
74
75/*********************************************************************************************************************************
76* Defined Constants And Macros *
77*********************************************************************************************************************************/
78
79/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
80 * and only used when we're in 16-bit code on a pre-386 CPU. */
81#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) \
82 return iemRegAddToIp16AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal)
83
84/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
85 * and used for 16-bit and 32-bit code on 386 and later CPUs. */
86#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) \
87 return iemRegAddToEip32AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal)
88
89/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
90 * and only used when we're in 64-bit code. */
91#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) \
92 return iemRegAddToRip64AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal)
93
94
95/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
96 * and only used when we're in 16-bit code on a pre-386 CPU and we need to
97 * check and clear flags. */
98#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) \
99 return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal)
100
101/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
102 * and used for 16-bit and 32-bit code on 386 and later CPUs and we need to
103 * check and clear flags. */
104#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) \
105 return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal)
106
107/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
108 * and only used when we're in 64-bit code and we need to check and clear
109 * flags. */
110#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) \
111 return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal)
112
113#undef IEM_MC_ADVANCE_RIP_AND_FINISH
114
115
116/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
117 * parameter, for use in 16-bit code on a pre-386 CPU. */
118#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr, a_rcNormal) \
119 return iemRegIp16RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_rcNormal)
120
121/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
122 * size as extra parameters, for use in 16-bit and 32-bit code on 386 and
123 * later CPUs. */
124#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
125 return iemRegEip32RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
126
127/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
128 * size as extra parameters, for use in 64-bit code. */
129#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
130 return iemRegRip64RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
131
132
133/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
134 * parameter, for use in 16-bit code on a pre-386 CPU and we need to check and
135 * clear flags. */
136#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i8, a_cbInstr, a_rcNormal) \
137 return iemRegIp16RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_rcNormal)
138
139/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
140 * size as extra parameters, for use in 16-bit and 32-bit code on 386 and
141 * later CPUs and we need to check and clear flags. */
142#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
143 return iemRegEip32RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
144
145/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
146 * size as extra parameters, for use in 64-bit code and we need to check and
147 * clear flags. */
148#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
149 return iemRegRip64RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
150
151#undef IEM_MC_REL_JMP_S8_AND_FINISH
152
153
154/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
155 * param, for use in 16-bit code on a pre-386 CPU. */
156#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr, a_rcNormal) \
157 return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
158
159/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
160 * param, for use in 16-bit and 32-bit code on 386 and later CPUs. */
161#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr, a_rcNormal) \
162 return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
163
164/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
165 * param, for use in 64-bit code. */
166#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr, a_rcNormal) \
167 return iemRegRip64RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
168
169
170/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
171 * param, for use in 16-bit code on a pre-386 CPU and we need to check and
172 * clear flags. */
173#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
174 return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
175
176/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
177 * param, for use in 16-bit and 32-bit code on 386 and later CPUs and we need
178 * to check and clear flags. */
179#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
180 return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
181
182/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
183 * param, for use in 64-bit code and we need to check and clear flags. */
184#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
185 return iemRegRip64RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
186
187#undef IEM_MC_REL_JMP_S16_AND_FINISH
188
189
190/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
191 * an extra parameter - dummy for pre-386 variations not eliminated by the
192 * python script. */
193#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16(a_i32, a_cbInstr, a_rcNormal) \
194 do { RT_NOREF(pVCpu, a_i32, a_cbInstr, a_rcNormal); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
195
196/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
197 * an extra parameter, for use in 16-bit and 32-bit code on 386+. */
198#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr, a_rcNormal) \
199 return iemRegEip32RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
200
201/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
202 * an extra parameter, for use in 64-bit code. */
203#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr, a_rcNormal) \
204 return iemRegRip64RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
205
206
207/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
208 * an extra parameter - dummy for pre-386 variations not eliminated by the
209 * python script. */
210#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
211 do { RT_NOREF(pVCpu, a_i32, a_cbInstr, a_rcNormal); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
212
213/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
214 * an extra parameter, for use in 16-bit and 32-bit code on 386+ and we need
215 * to check and clear flags. */
216#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
217 return iemRegEip32RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
218
219/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
220 * an extra parameter, for use in 64-bit code and we need to check and clear
221 * flags. */
222#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
223 return iemRegRip64RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
224
225#undef IEM_MC_REL_JMP_S32_AND_FINISH
226
227
228
229/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for pre-386 targets. */
230#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16(a_u16NewIP) \
231 return iemRegRipJumpU16AndFinishNoFlags((pVCpu), (a_u16NewIP))
232
233/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for 386+ targets. */
234#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32(a_u16NewIP) \
235 return iemRegRipJumpU16AndFinishNoFlags((pVCpu), (a_u16NewIP))
236
237/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for use in 64-bit code. */
238#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64(a_u16NewIP) \
239 return iemRegRipJumpU16AndFinishNoFlags((pVCpu), (a_u16NewIP))
240
241/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for pre-386 targets that checks and
242 * clears flags. */
243#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_u16NewIP) \
244 return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
245
246/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for 386+ targets that checks and
247 * clears flags. */
248#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u16NewIP) \
249 return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
250
251/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for use in 64-bit code that checks and
252 * clears flags. */
253#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u16NewIP) \
254 return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
255
256#undef IEM_MC_SET_RIP_U16_AND_FINISH
257
258
259/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for 386+ targets. */
260#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32(a_u32NewEIP) \
261 return iemRegRipJumpU32AndFinishNoFlags((pVCpu), (a_u32NewEIP))
262
263/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for use in 64-bit code. */
264#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64(a_u32NewEIP) \
265 return iemRegRipJumpU32AndFinishNoFlags((pVCpu), (a_u32NewEIP))
266
267/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for 386+ targets that checks and
268 * clears flags. */
269#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u32NewEIP) \
270 return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
271
272/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for use in 64-bit code that checks
273 * and clears flags. */
274#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP) \
275 return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
276
277#undef IEM_MC_SET_RIP_U32_AND_FINISH
278
279
280/** Variant of IEM_MC_SET_RIP_U64_AND_FINISH for use in 64-bit code. */
281#define IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64(a_u32NewEIP) \
282 return iemRegRipJumpU64AndFinishNoFlags((pVCpu), (a_u32NewEIP))
283
284/** Variant of IEM_MC_SET_RIP_U64_AND_FINISH for use in 64-bit code that checks
285 * and clears flags. */
286#define IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP) \
287 return iemRegRipJumpU64AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
288
289#undef IEM_MC_SET_RIP_U64_AND_FINISH
290
291
292/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit. */
293#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp) \
294 (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
295
296/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit. */
297#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
298 (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
299
300/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
301#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
302 (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
303
304/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
305#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_FSGS(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
306 (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
307
308/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters.
309 * @todo How did that address prefix thing work for 64-bit code again? */
310#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
311 (a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
312
313#undef IEM_MC_CALC_RM_EFF_ADDR
314
315
316/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
317#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
318 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
319#undef IEM_MC_CALL_CIMPL_1
320
321/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
322#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
323 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
324#undef IEM_MC_CALL_CIMPL_2
325
326/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
327#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
328 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
329#undef IEM_MC_CALL_CIMPL_3
330
331/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
332#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
333 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
334#undef IEM_MC_CALL_CIMPL_4
335
336/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
337#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
338 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
339#undef IEM_MC_CALL_CIMPL_5
340
341
342/** Variant of IEM_MC_DEFER_TO_CIMPL_0_RET with explicit instruction
343 * length parameter. */
344#define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl) \
345 return (a_pfnCImpl)(pVCpu, (a_cbInstr))
346#undef IEM_MC_DEFER_TO_CIMPL_0_RET
347
348/** Variant of IEM_MC_DEFER_TO_CIMPL_1_RET with explicit instruction
349 * length parameter. */
350#define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
351 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
352#undef IEM_MC_DEFER_TO_CIMPL_1_RET
353
354/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
355#define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
356 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
357#undef IEM_MC_DEFER_TO_CIMPL_2_RET
358
359/** Variant of IEM_MC_DEFER_TO_CIMPL_3 with explicit instruction length
360 * parameter. */
361#define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
362 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
363#undef IEM_MC_DEFER_TO_CIMPL_3_RET
364
365/** Variant of IEM_MC_DEFER_TO_CIMPL_4 with explicit instruction length
366 * parameter. */
367#define IEM_MC_DEFER_TO_CIMPL_4_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
368 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
369#undef IEM_MC_DEFER_TO_CIMPL_4_RET
370
371/** Variant of IEM_MC_DEFER_TO_CIMPL_5 with explicit instruction length
372 * parameter. */
373#define IEM_MC_DEFER_TO_CIMPL_5_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
374 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
375#undef IEM_MC_DEFER_TO_CIMPL_5_RET
376
377
378/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
379#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
380 (a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
381
382/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
383#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
384 (a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
385
386/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
387#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
388 (a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
389
390/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
391#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
392 (a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
393
394/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
395#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
396 (a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
397
398/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
399#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
400 (a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
401#undef IEM_MC_FETCH_GREG_U8_SX_U32
402
403/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
404#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
405 (a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
406#undef IEM_MC_FETCH_GREG_U8_SX_U64
407
408/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
409#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
410 *iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
411#undef IEM_MC_STORE_GREG_U8
412
413/** Variant of IEM_MC_STORE_GREG_U8_CONST with extended (20) register index. */
414#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
415 *iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
416#undef IEM_MC_STORE_GREG_U8
417
418/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
419#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
420 (a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
421#undef IEM_MC_REF_GREG_U8
422
423/** Variant of IEM_MC_REF_GREG_U8_CONST with extended (20) register index. */
424#define IEM_MC_REF_GREG_U8_CONST_THREADED(a_pu8Dst, a_iGRegEx) \
425 (a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
426#undef IEM_MC_REF_GREG_U8
427
428/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
429#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
430 do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
431#undef IEM_MC_ADD_GREG_U8_TO_LOCAL
432
433/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
434#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
435 *iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
436#undef IEM_MC_AND_GREG_U8
437
438/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
439#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
440 *iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) |= (a_u8Value)
441#undef IEM_MC_OR_GREG_U8
442
443
444/** For asserting that only declared output flags changed. */
445#ifndef VBOX_STRICT
446# define IEM_MC_ASSERT_EFLAGS(a_fEflInput, a_fEflOutput) ((void)0)
447#else
448# undef IEM_MC_REF_EFLAGS_EX
449# define IEM_MC_REF_EFLAGS_EX(a_pEFlags, a_fEflInput, a_fEflOutput) \
450 uint32_t const fEflAssert = pVCpu->cpum.GstCtx.eflags.uBoth; \
451 IEM_MC_REF_EFLAGS(a_pEFlags)
452# define IEM_MC_ASSERT_EFLAGS(a_fEflInput, a_fEflOutput) \
453 AssertMsg((pVCpu->cpum.GstCtx.eflags.uBoth & ~(a_fEflOutput)) == (fEflAssert & ~(a_fEflOutput)), \
454 ("now %#x (%#x), was %#x (%#x) - diff %#x; a_fEflOutput=%#x\n", \
455 (pVCpu->cpum.GstCtx.eflags.uBoth & ~(a_fEflOutput)), pVCpu->cpum.GstCtx.eflags.uBoth, \
456 (fEflAssert & ~(a_fEflOutput)), fEflAssert, \
457 (pVCpu->cpum.GstCtx.eflags.uBoth ^ fEflAssert) & ~(a_fEflOutput), a_fEflOutput))
458#endif
459
460
461
462/**
463 * Calculates the effective address of a ModR/M memory operand, 16-bit
464 * addressing variant.
465 *
466 * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
467 *
468 * @returns The effective address.
469 * @param pVCpu The cross context virtual CPU structure of the calling thread.
470 * @param bRm The ModRM byte.
471 * @param u16Disp The displacement byte/word, if any.
472 * RIP relative addressing.
473 */
474static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
475{
476 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x u16Disp=%#x\n", bRm, u16Disp));
477 Assert(!IEM_IS_64BIT_CODE(pVCpu));
478
479 /* Handle the disp16 form with no registers first. */
480 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
481 {
482 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
483 return u16Disp;
484 }
485
486 /* Get the displacment. */
487 /** @todo we can eliminate this step by making u16Disp have this value
488 * already! */
489 uint16_t u16EffAddr;
490 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
491 {
492 case 0: u16EffAddr = 0; break;
493 case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
494 case 2: u16EffAddr = u16Disp; break;
495 default: AssertFailedStmt(u16EffAddr = 0);
496 }
497
498 /* Add the base and index registers to the disp. */
499 switch (bRm & X86_MODRM_RM_MASK)
500 {
501 case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
502 case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
503 case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
504 case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
505 case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
506 case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
507 case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
508 case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
509 }
510
511 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
512 return u16EffAddr;
513}
514
515
516/**
517 * Calculates the effective address of a ModR/M memory operand, 32-bit
518 * addressing variant.
519 *
520 * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
521 * IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
522 *
523 * @returns The effective address.
524 * @param pVCpu The cross context virtual CPU structure of the
525 * calling thread.
526 * @param bRm The ModRM byte.
527 * @param uSibAndRspOffset Two parts:
528 * - The first 8 bits make up the SIB byte.
529 * - The next 8 bits are the fixed RSP/ESP offse
530 * in case of a pop [xSP].
531 * @param u32Disp The displacement byte/dword, if any.
532 */
533static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint32_t uSibAndRspOffset,
534 uint32_t u32Disp) RT_NOEXCEPT
535{
536 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x uSibAndRspOffset=%#x u32Disp=%#x\n", bRm, uSibAndRspOffset, u32Disp));
537
538 /* Handle the disp32 form with no registers first. */
539 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
540 {
541 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
542 return u32Disp;
543 }
544
545 /* Get the register (or SIB) value. */
546 uint32_t u32EffAddr;
547#ifdef _MSC_VER
548 u32EffAddr = 0;/* MSC uninitialized variable analysis is too simple, it seems. */
549#endif
550 switch (bRm & X86_MODRM_RM_MASK)
551 {
552 case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
553 case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
554 case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
555 case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
556 case 4: /* SIB */
557 {
558 /* Get the index and scale it. */
559 switch ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
560 {
561 case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
562 case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
563 case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
564 case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
565 case 4: u32EffAddr = 0; /*none */ break;
566 case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
567 case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
568 case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
569 }
570 u32EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
571
572 /* add base */
573 switch (uSibAndRspOffset & X86_SIB_BASE_MASK)
574 {
575 case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
576 case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
577 case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
578 case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
579 case 4:
580 u32EffAddr += pVCpu->cpum.GstCtx.esp;
581 u32EffAddr += uSibAndRspOffset >> 8;
582 break;
583 case 5:
584 if ((bRm & X86_MODRM_MOD_MASK) != 0)
585 u32EffAddr += pVCpu->cpum.GstCtx.ebp;
586 else
587 u32EffAddr += u32Disp;
588 break;
589 case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
590 case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
591 }
592 break;
593 }
594 case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
595 case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
596 case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
597 }
598
599 /* Get and add the displacement. */
600 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
601 {
602 case 0: break;
603 case 1: u32EffAddr += (int8_t)u32Disp; break;
604 case 2: u32EffAddr += u32Disp; break;
605 default: AssertFailed();
606 }
607
608 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
609 return u32EffAddr;
610}
611
612
613/**
614 * Calculates the effective address of a ModR/M memory operand.
615 *
616 * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
617 *
618 * @returns The effective address.
619 * @param pVCpu The cross context virtual CPU structure of the
620 * calling thread.
621 * @param bRmEx The ModRM byte but with bit 3 set to REX.B and
622 * bit 4 to REX.X. The two bits are part of the
623 * REG sub-field, which isn't needed in this
624 * function.
625 * @param uSibAndRspOffset Two parts:
626 * - The first 8 bits make up the SIB byte.
627 * - The next 8 bits are the fixed RSP/ESP offset
628 * in case of a pop [xSP].
629 * @param u32Disp The displacement byte/word/dword, if any.
630 * @param cbInstr The size of the fully decoded instruction. Used
631 * for RIP relative addressing.
632 * @todo combine cbInstr and cbImm!
633 */
634static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint32_t uSibAndRspOffset,
635 uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
636{
637 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
638 Assert(IEM_IS_64BIT_CODE(pVCpu));
639
640 uint64_t u64EffAddr;
641
642 /* Handle the rip+disp32 form with no registers first. */
643 if ((bRmEx & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
644 {
645 u64EffAddr = (int32_t)u32Disp;
646 u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
647 }
648 else
649 {
650 /* Get the register (or SIB) value. */
651#ifdef _MSC_VER
652 u64EffAddr = 0; /* MSC uninitialized variable analysis is too simple, it seems. */
653#endif
654 switch (bRmEx & (X86_MODRM_RM_MASK | 0x8)) /* bRmEx[bit 3] = REX.B */
655 {
656 default:
657 case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
658 case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
659 case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
660 case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
661 case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
662 case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
663 case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
664 case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
665 case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
666 case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
667 case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
668 case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
669 case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
670 case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
671 /* SIB */
672 case 4:
673 case 12:
674 {
675 /* Get the index and scale it. */
676 switch ( ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
677 | ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
678 {
679 case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
680 case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
681 case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
682 case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
683 case 4: u64EffAddr = 0; /*none */ break;
684 case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
685 case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
686 case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
687 case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
688 case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
689 case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
690 case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
691 case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
692 case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
693 case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
694 case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
695 }
696 u64EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
697
698 /* add base */
699 switch ((uSibAndRspOffset & X86_SIB_BASE_MASK) | (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
700 {
701 case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
702 case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
703 case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
704 case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
705 case 4:
706 u64EffAddr += pVCpu->cpum.GstCtx.rsp;
707 u64EffAddr += uSibAndRspOffset >> 8;
708 break;
709 case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
710 case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
711 case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
712 case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
713 case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
714 case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
715 case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
716 case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
717 case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
718 /* complicated encodings */
719 case 5:
720 if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
721 u64EffAddr += pVCpu->cpum.GstCtx.rbp;
722 else
723 u64EffAddr += (int32_t)u32Disp;
724 break;
725 case 13:
726 if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
727 u64EffAddr += pVCpu->cpum.GstCtx.r13;
728 else
729 u64EffAddr += (int32_t)u32Disp;
730 break;
731 }
732 break;
733 }
734 }
735
736 /* Get and add the displacement. */
737 switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
738 {
739 case 0: break;
740 case 1: u64EffAddr += (int8_t)u32Disp; break;
741 case 2: u64EffAddr += (int32_t)u32Disp; break;
742 default: AssertFailed();
743 }
744 }
745
746 Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
747 return u64EffAddr;
748}
749
750
751/*
752 * The threaded functions.
753 */
754#include "IEMThreadedFunctions.cpp.h"
755
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use