| [98916] | 1 | /* $Id: IEMAllInstCommonBodyMacros.h 104195 2024-04-05 14:45:23Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IEM - Instruction Decoding and Emulation, Common Body Macros.
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| 4 | *
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| 5 | * This is placed in its own file without anything else in it, so that it can
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| [100733] | 6 | * be digested by SimplerParser in IEMAllInstPython.py prior processing
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| [98916] | 7 | * any of the other IEMAllInstruction*.cpp.h files. For instance
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| [100733] | 8 | * IEMAllInstCommon.cpp.h wouldn't do as it defines several invalid
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| [98916] | 9 | * instructions and such that could confuse the parser result.
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| 10 | */
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| 11 |
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| 12 | /*
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| 13 | * Copyright (C) 2011-2023 Oracle and/or its affiliates.
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| 14 | *
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| 15 | * This file is part of VirtualBox base platform packages, as
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| 16 | * available from https://www.virtualbox.org.
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| 17 | *
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| 18 | * This program is free software; you can redistribute it and/or
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| 19 | * modify it under the terms of the GNU General Public License
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| 20 | * as published by the Free Software Foundation, in version 3 of the
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| 21 | * License.
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| 22 | *
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| 23 | * This program is distributed in the hope that it will be useful, but
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| 24 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 26 | * General Public License for more details.
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| 27 | *
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| 28 | * You should have received a copy of the GNU General Public License
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| 29 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 30 | *
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| 31 | * SPDX-License-Identifier: GPL-3.0-only
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| 32 | */
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| 33 |
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| 34 |
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| 35 | /**
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| 36 | * Body for word/dword/qword instructions like ADD, AND, OR, ++ with a register
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| 37 | * as the destination.
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| 38 | *
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| 39 | * @note Used both in OneByte and TwoByte0f.
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| 40 | */
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| [103718] | 41 | #define IEMOP_BODY_BINARY_rv_rm(a_bRm, a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_f16BitMcFlag, a_EmitterBasename, a_fNativeArchs) \
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| [98916] | 42 | /* \
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| 43 | * If rm is denoting a register, no more instruction bytes. \
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| 44 | */ \
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| [103548] | 45 | if (IEM_IS_MODRM_REG_MODE(a_bRm)) \
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| [98916] | 46 | { \
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| 47 | switch (pVCpu->iem.s.enmEffOpSize) \
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| 48 | { \
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| 49 | case IEMMODE_16BIT: \
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| [104018] | 50 | IEM_MC_BEGIN(a_f16BitMcFlag, 0); \
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| [100714] | 51 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| [104195] | 52 | IEM_MC_ARG(uint16_t, u16Src, 2); \
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| [103548] | 53 | IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| [103640] | 54 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 55 | IEM_MC_LOCAL(uint16_t, u16Dst); \
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| 56 | IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 57 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [103640] | 58 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
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| 59 | IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
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| [103828] | 60 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103640] | 61 | } IEM_MC_NATIVE_ELSE() { \
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| [104195] | 62 | IEM_MC_ARG(uint16_t *, pu16Dst, 1); \
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| [103640] | 63 | IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104195] | 64 | IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
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| 65 | IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU16, fEFlagsIn, pu16Dst, u16Src); \
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| 66 | IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
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| [103640] | 67 | } IEM_MC_NATIVE_ENDIF(); \
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| [98916] | 68 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 69 | IEM_MC_END(); \
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| 70 | break; \
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| 71 | \
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| 72 | case IEMMODE_32BIT: \
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| [104018] | 73 | IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
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| [100714] | 74 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| [104195] | 75 | IEM_MC_ARG(uint32_t, u32Src, 2); \
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| [103548] | 76 | IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| [103640] | 77 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 78 | IEM_MC_LOCAL(uint32_t, u32Dst); \
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| 79 | IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 80 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [103640] | 81 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
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| 82 | IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
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| [103828] | 83 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103640] | 84 | } IEM_MC_NATIVE_ELSE() { \
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| [104195] | 85 | IEM_MC_ARG(uint32_t *, pu32Dst, 1); \
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| [103640] | 86 | IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104195] | 87 | IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
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| 88 | IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU32, fEFlagsIn, pu32Dst, u32Src); \
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| [103718] | 89 | IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| [104195] | 90 | IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
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| [103640] | 91 | } IEM_MC_NATIVE_ENDIF(); \
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| [98916] | 92 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 93 | IEM_MC_END(); \
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| 94 | break; \
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| 95 | \
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| 96 | case IEMMODE_64BIT: \
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| [104018] | 97 | IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
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| [100714] | 98 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| [104195] | 99 | IEM_MC_ARG(uint64_t, u64Src, 2); \
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| [103548] | 100 | IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| [103640] | 101 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 102 | IEM_MC_LOCAL(uint64_t, u64Dst); \
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| 103 | IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 104 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [103640] | 105 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
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| 106 | IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
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| [103828] | 107 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103640] | 108 | } IEM_MC_NATIVE_ELSE() { \
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| [104195] | 109 | IEM_MC_ARG(uint64_t *, pu64Dst, 1); \
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| [103640] | 110 | IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104195] | 111 | IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
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| 112 | IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU64, fEFlagsIn, pu64Dst, u64Src); \
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| 113 | IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
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| [103640] | 114 | } IEM_MC_NATIVE_ENDIF(); \
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| [98916] | 115 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 116 | IEM_MC_END(); \
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| 117 | break; \
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| 118 | \
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| 119 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
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| 120 | } \
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| 121 | } \
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| 122 | else \
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| 123 | { \
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| 124 | /* \
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| 125 | * We're accessing memory. \
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| 126 | */ \
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| 127 | switch (pVCpu->iem.s.enmEffOpSize) \
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| 128 | { \
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| 129 | case IEMMODE_16BIT: \
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| [104018] | 130 | IEM_MC_BEGIN(a_f16BitMcFlag, 0); \
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| [98916] | 131 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
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| [103548] | 132 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
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| [98916] | 133 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| [104195] | 134 | IEM_MC_ARG(uint16_t, u16Src, 2); \
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| [98916] | 135 | IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
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| [103642] | 136 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 137 | IEM_MC_LOCAL(uint16_t, u16Dst); \
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| 138 | IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 139 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [103642] | 140 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
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| 141 | IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
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| [103828] | 142 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103642] | 143 | } IEM_MC_NATIVE_ELSE() { \
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| [104195] | 144 | IEM_MC_ARG(uint16_t *, pu16Dst, 1); \
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| [103642] | 145 | IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| [104195] | 146 | IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
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| 147 | IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU16, fEFlagsIn, pu16Dst, u16Src); \
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| 148 | IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
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| [103642] | 149 | } IEM_MC_NATIVE_ENDIF(); \
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| [98916] | 150 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 151 | IEM_MC_END(); \
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| 152 | break; \
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| 153 | \
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| 154 | case IEMMODE_32BIT: \
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| [104018] | 155 | IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
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| [98916] | 156 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
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| [103548] | 157 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
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| [98916] | 158 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| [104195] | 159 | IEM_MC_ARG(uint32_t, u32Src, 2); \
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| [98916] | 160 | IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
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| [103642] | 161 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 162 | IEM_MC_LOCAL(uint32_t, u32Dst); \
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| 163 | IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 164 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [103642] | 165 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
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| 166 | IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
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| [103828] | 167 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103642] | 168 | } IEM_MC_NATIVE_ELSE() { \
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| [104195] | 169 | IEM_MC_ARG(uint32_t *, pu32Dst, 1); \
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| [103642] | 170 | IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| [104195] | 171 | IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
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| 172 | IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU32, fEFlagsIn, pu32Dst, u32Src); \
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| [103718] | 173 | IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| [104195] | 174 | IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
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| [103642] | 175 | } IEM_MC_NATIVE_ENDIF(); \
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| [98916] | 176 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 177 | IEM_MC_END(); \
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| 178 | break; \
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| 179 | \
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| 180 | case IEMMODE_64BIT: \
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| [104018] | 181 | IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
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| [98916] | 182 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
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| [103548] | 183 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
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| [98916] | 184 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| [104195] | 185 | IEM_MC_ARG(uint64_t, u64Src, 2); \
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| [98916] | 186 | IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
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| [103642] | 187 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 188 | IEM_MC_LOCAL(uint64_t, u64Dst); \
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| 189 | IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 190 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [103642] | 191 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
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| 192 | IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
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| [103828] | 193 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103642] | 194 | } IEM_MC_NATIVE_ELSE() { \
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| [104195] | 195 | IEM_MC_ARG(uint64_t *, pu64Dst, 1); \
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| [103642] | 196 | IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| [104195] | 197 | IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
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| 198 | IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU64, fEFlagsIn, pu64Dst, u64Src); \
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| 199 | IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
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| [103642] | 200 | } IEM_MC_NATIVE_ENDIF(); \
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| [98916] | 201 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 202 | IEM_MC_END(); \
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| 203 | break; \
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| 204 | \
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| 205 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
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| 206 | } \
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| 207 | } \
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| 208 | (void)0
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| 209 |
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| [104195] | 210 |
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| [103718] | 211 | /**
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| [104195] | 212 | * Body for word/dword/qword instructions like ADD, AND, OR, ++ with a register
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| 213 | * as the destination.
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| [103718] | 214 | *
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| 215 | * @note Used both in OneByte and TwoByte0f.
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| 216 | */
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| [104195] | 217 | #define IEMOP_BODY_BINARY_TODO_rv_rm(a_bRm, a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_f16BitMcFlag, a_EmitterBasename, a_fNativeArchs) \
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| [103718] | 218 | /* \
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| 219 | * If rm is denoting a register, no more instruction bytes. \
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| 220 | */ \
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| 221 | if (IEM_IS_MODRM_REG_MODE(a_bRm)) \
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| 222 | { \
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| 223 | switch (pVCpu->iem.s.enmEffOpSize) \
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| 224 | { \
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| 225 | case IEMMODE_16BIT: \
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| [104195] | 226 | IEM_MC_BEGIN(a_f16BitMcFlag, 0); \
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| [103718] | 227 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 228 | IEM_MC_ARG(uint16_t, u16Src, 1); \
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| 229 | IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| 230 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 231 | IEM_MC_LOCAL(uint16_t, u16Dst); \
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| 232 | IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 233 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [104195] | 234 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
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| 235 | IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
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| [103828] | 236 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103718] | 237 | } IEM_MC_NATIVE_ELSE() { \
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| 238 | IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
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| 239 | IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 240 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 241 | IEM_MC_REF_EFLAGS(pEFlags); \
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| [104195] | 242 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
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| [103718] | 243 | } IEM_MC_NATIVE_ENDIF(); \
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| 244 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 245 | IEM_MC_END(); \
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| 246 | break; \
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| 247 | \
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| 248 | case IEMMODE_32BIT: \
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| [104018] | 249 | IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
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| [103718] | 250 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 251 | IEM_MC_ARG(uint32_t, u32Src, 1); \
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| 252 | IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| 253 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 254 | IEM_MC_LOCAL(uint32_t, u32Dst); \
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| 255 | IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 256 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [104195] | 257 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
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| 258 | IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
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| [103828] | 259 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103718] | 260 | } IEM_MC_NATIVE_ELSE() { \
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| 261 | IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
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| 262 | IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 263 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 264 | IEM_MC_REF_EFLAGS(pEFlags); \
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| [104195] | 265 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
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| 266 | IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| [103718] | 267 | } IEM_MC_NATIVE_ENDIF(); \
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| 268 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 269 | IEM_MC_END(); \
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| 270 | break; \
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| 271 | \
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| 272 | case IEMMODE_64BIT: \
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| [104018] | 273 | IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
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| [103718] | 274 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 275 | IEM_MC_ARG(uint64_t, u64Src, 1); \
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| 276 | IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| 277 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 278 | IEM_MC_LOCAL(uint64_t, u64Dst); \
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| 279 | IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| [104016] | 280 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
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| [104195] | 281 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
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| 282 | IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
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| [103828] | 283 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
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| [103718] | 284 | } IEM_MC_NATIVE_ELSE() { \
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| 285 | IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
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| 286 | IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 287 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 288 | IEM_MC_REF_EFLAGS(pEFlags); \
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| [104195] | 289 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
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| [103718] | 290 | } IEM_MC_NATIVE_ENDIF(); \
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| 291 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 292 | IEM_MC_END(); \
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| 293 | break; \
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| 294 | \
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| 295 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
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| 296 | } \
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| 297 | } \
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| 298 | else \
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| 299 | { \
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| 300 | /* \
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| 301 | * We're accessing memory. \
|
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| 302 | */ \
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| 303 | switch (pVCpu->iem.s.enmEffOpSize) \
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| 304 | { \
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| 305 | case IEMMODE_16BIT: \
|
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| [104195] | 306 | IEM_MC_BEGIN(a_f16BitMcFlag, 0); \
|
|---|
| [103718] | 307 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
|
|---|
| 308 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
|
|---|
| 309 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
|
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| 310 | IEM_MC_ARG(uint16_t, u16Src, 1); \
|
|---|
| 311 | IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
|
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| 312 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
|
|---|
| 313 | IEM_MC_LOCAL(uint16_t, u16Dst); \
|
|---|
| 314 | IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
|
|---|
| [104016] | 315 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
|
|---|
| [104195] | 316 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
|
|---|
| 317 | IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
|
|---|
| [103828] | 318 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
|
|---|
| [103718] | 319 | } IEM_MC_NATIVE_ELSE() { \
|
|---|
| 320 | IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
|
|---|
| 321 | IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
|
|---|
| 322 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
|
|---|
| 323 | IEM_MC_REF_EFLAGS(pEFlags); \
|
|---|
| [104195] | 324 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
|
|---|
| [103718] | 325 | } IEM_MC_NATIVE_ENDIF(); \
|
|---|
| 326 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
|
|---|
| 327 | IEM_MC_END(); \
|
|---|
| 328 | break; \
|
|---|
| 329 | \
|
|---|
| 330 | case IEMMODE_32BIT: \
|
|---|
| [104018] | 331 | IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
|
|---|
| [103718] | 332 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
|
|---|
| 333 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
|
|---|
| 334 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
|
|---|
| 335 | IEM_MC_ARG(uint32_t, u32Src, 1); \
|
|---|
| 336 | IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
|
|---|
| 337 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
|
|---|
| 338 | IEM_MC_LOCAL(uint32_t, u32Dst); \
|
|---|
| 339 | IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
|
|---|
| [104016] | 340 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
|
|---|
| [104195] | 341 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
|
|---|
| 342 | IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
|
|---|
| [103828] | 343 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
|
|---|
| [103718] | 344 | } IEM_MC_NATIVE_ELSE() { \
|
|---|
| 345 | IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
|
|---|
| 346 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
|
|---|
| 347 | IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
|
|---|
| 348 | IEM_MC_REF_EFLAGS(pEFlags); \
|
|---|
| [104195] | 349 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
|
|---|
| 350 | IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
|
|---|
| [103718] | 351 | } IEM_MC_NATIVE_ENDIF(); \
|
|---|
| 352 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
|
|---|
| 353 | IEM_MC_END(); \
|
|---|
| 354 | break; \
|
|---|
| 355 | \
|
|---|
| 356 | case IEMMODE_64BIT: \
|
|---|
| [104018] | 357 | IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
|
|---|
| [103718] | 358 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
|
|---|
| 359 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
|
|---|
| 360 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
|
|---|
| 361 | IEM_MC_ARG(uint64_t, u64Src, 1); \
|
|---|
| 362 | IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
|
|---|
| 363 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
|
|---|
| 364 | IEM_MC_LOCAL(uint64_t, u64Dst); \
|
|---|
| 365 | IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
|
|---|
| [104016] | 366 | IEM_MC_LOCAL_EFLAGS(uEFlags); \
|
|---|
| [104195] | 367 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
|
|---|
| 368 | IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
|
|---|
| [103828] | 369 | IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
|
|---|
| [103718] | 370 | } IEM_MC_NATIVE_ELSE() { \
|
|---|
| 371 | IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
|
|---|
| 372 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
|
|---|
| 373 | IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
|
|---|
| 374 | IEM_MC_REF_EFLAGS(pEFlags); \
|
|---|
| [104195] | 375 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
|
|---|
| [103718] | 376 | } IEM_MC_NATIVE_ENDIF(); \
|
|---|
| 377 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
|
|---|
| 378 | IEM_MC_END(); \
|
|---|
| 379 | break; \
|
|---|
| 380 | \
|
|---|
| 381 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
|
|---|
| 382 | } \
|
|---|
| 383 | } \
|
|---|
| 384 | (void)0
|
|---|
| 385 |
|
|---|
