[23] | 1 | /* $Id: EMAll.cpp 99220 2023-03-30 12:40:46Z vboxsync $ */
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[1] | 2 | /** @file
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| 3 | * EM - Execution Monitor(/Manager) - All contexts
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| 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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[1] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[1] | 26 | */
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| 27 |
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[57358] | 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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[1] | 32 | #define LOG_GROUP LOG_GROUP_EM
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[35346] | 33 | #include <VBox/vmm/em.h>
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| 34 | #include <VBox/vmm/mm.h>
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| 35 | #include <VBox/vmm/selm.h>
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| 36 | #include <VBox/vmm/pgm.h>
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[72885] | 37 | #include <VBox/vmm/iem.h>
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[35346] | 38 | #include <VBox/vmm/iom.h>
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[72885] | 39 | #include <VBox/vmm/hm.h>
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| 40 | #include <VBox/vmm/pdmapi.h>
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| 41 | #include <VBox/vmm/vmm.h>
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[35346] | 42 | #include <VBox/vmm/stam.h>
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[1] | 43 | #include "EMInternal.h"
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[80253] | 44 | #include <VBox/vmm/vmcc.h>
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[1] | 45 | #include <VBox/param.h>
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| 46 | #include <VBox/err.h>
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| 47 | #include <VBox/dis.h>
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| 48 | #include <VBox/log.h>
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| 49 | #include <iprt/assert.h>
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| 50 | #include <iprt/string.h>
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| 51 |
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[2505] | 52 |
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[45276] | 53 |
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[45485] | 54 |
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[1] | 55 | /**
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| 56 | * Get the current execution manager status.
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| 57 | *
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| 58 | * @returns Current status.
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[58123] | 59 | * @param pVCpu The cross context virtual CPU structure.
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[1] | 60 | */
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[44375] | 61 | VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
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[1] | 62 | {
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[18927] | 63 | return pVCpu->em.s.enmState;
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[1] | 64 | }
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| 65 |
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[58126] | 66 |
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[19611] | 67 | /**
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| 68 | * Sets the current execution manager status. (use only when you know what you're doing!)
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| 69 | *
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[58126] | 70 | * @param pVCpu The cross context virtual CPU structure.
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| 71 | * @param enmNewState The new state, EMSTATE_WAIT_SIPI or EMSTATE_HALTED.
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[19611] | 72 | */
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[44375] | 73 | VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
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[19611] | 74 | {
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| 75 | /* Only allowed combination: */
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| 76 | Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
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| 77 | pVCpu->em.s.enmState = enmNewState;
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| 78 | }
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| 79 |
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| 80 |
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[1] | 81 | /**
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[72462] | 82 | * Enables / disable hypercall instructions.
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| 83 | *
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| 84 | * This interface is used by GIM to tell the execution monitors whether the
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| 85 | * hypercall instruction (VMMCALL & VMCALL) are allowed or should \#UD.
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| 86 | *
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| 87 | * @param pVCpu The cross context virtual CPU structure this applies to.
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| 88 | * @param fEnabled Whether hypercall instructions are enabled (true) or not.
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| 89 | */
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| 90 | VMMDECL(void) EMSetHypercallInstructionsEnabled(PVMCPU pVCpu, bool fEnabled)
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| 91 | {
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| 92 | pVCpu->em.s.fHypercallEnabled = fEnabled;
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| 93 | }
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| 94 |
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| 95 |
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| 96 | /**
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| 97 | * Checks if hypercall instructions (VMMCALL & VMCALL) are enabled or not.
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| 98 | *
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| 99 | * @returns true if enabled, false if not.
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| 100 | * @param pVCpu The cross context virtual CPU structure.
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| 101 | *
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| 102 | * @note If this call becomes a performance factor, we can make the data
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| 103 | * field available thru a read-only view in VMCPU. See VM::cpum.ro.
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| 104 | */
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| 105 | VMMDECL(bool) EMAreHypercallInstructionsEnabled(PVMCPU pVCpu)
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| 106 | {
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| 107 | return pVCpu->em.s.fHypercallEnabled;
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| 108 | }
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| 109 |
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| 110 |
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[99051] | 111 | #if !defined(VBOX_VMM_TARGET_ARMV8)
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[72462] | 112 | /**
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[40357] | 113 | * Prepare an MWAIT - essentials of the MONITOR instruction.
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| 114 | *
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| 115 | * @returns VINF_SUCCESS
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[58123] | 116 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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[40357] | 117 | * @param rax The content of RAX.
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| 118 | * @param rcx The content of RCX.
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| 119 | * @param rdx The content of RDX.
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[47326] | 120 | * @param GCPhys The physical address corresponding to rax.
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[40357] | 121 | */
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[47326] | 122 | VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
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[40357] | 123 | {
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| 124 | pVCpu->em.s.MWait.uMonitorRAX = rax;
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| 125 | pVCpu->em.s.MWait.uMonitorRCX = rcx;
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| 126 | pVCpu->em.s.MWait.uMonitorRDX = rdx;
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| 127 | pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_MONITOR_ACTIVE;
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[47326] | 128 | /** @todo Make use of GCPhys. */
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[49481] | 129 | NOREF(GCPhys);
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[40357] | 130 | /** @todo Complete MONITOR implementation. */
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| 131 | return VINF_SUCCESS;
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| 132 | }
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| 133 |
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| 134 |
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| 135 | /**
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[66581] | 136 | * Checks if the monitor hardware is armed / active.
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| 137 | *
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| 138 | * @returns true if armed, false otherwise.
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| 139 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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| 140 | */
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| 141 | VMM_INT_DECL(bool) EMMonitorIsArmed(PVMCPU pVCpu)
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| 142 | {
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| 143 | return RT_BOOL(pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_MONITOR_ACTIVE);
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| 144 | }
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| 145 |
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| 146 |
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| 147 | /**
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[75646] | 148 | * Checks if we're in a MWAIT.
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| 149 | *
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| 150 | * @retval 1 if regular,
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| 151 | * @retval > 1 if MWAIT with EMMWAIT_FLAG_BREAKIRQIF0
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| 152 | * @retval 0 if not armed
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| 153 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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| 154 | */
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| 155 | VMM_INT_DECL(unsigned) EMMonitorWaitIsActive(PVMCPU pVCpu)
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| 156 | {
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| 157 | uint32_t fWait = pVCpu->em.s.MWait.fWait;
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| 158 | AssertCompile(EMMWAIT_FLAG_ACTIVE == 1);
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| 159 | AssertCompile(EMMWAIT_FLAG_BREAKIRQIF0 == 2);
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| 160 | AssertCompile((EMMWAIT_FLAG_ACTIVE << 1) == EMMWAIT_FLAG_BREAKIRQIF0);
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| 161 | return fWait & (EMMWAIT_FLAG_ACTIVE | ((fWait & EMMWAIT_FLAG_ACTIVE) << 1));
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| 162 | }
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| 163 |
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| 164 |
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| 165 | /**
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[40357] | 166 | * Performs an MWAIT.
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| 167 | *
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| 168 | * @returns VINF_SUCCESS
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[58123] | 169 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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[40357] | 170 | * @param rax The content of RAX.
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| 171 | * @param rcx The content of RCX.
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| 172 | */
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| 173 | VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
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| 174 | {
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| 175 | pVCpu->em.s.MWait.uMWaitRAX = rax;
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| 176 | pVCpu->em.s.MWait.uMWaitRCX = rcx;
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| 177 | pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_ACTIVE;
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| 178 | if (rcx)
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| 179 | pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_BREAKIRQIF0;
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| 180 | else
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| 181 | pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
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| 182 | /** @todo not completely correct?? */
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| 183 | return VINF_EM_HALT;
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| 184 | }
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| 185 |
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| 186 |
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[74204] | 187 | /**
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| 188 | * Clears any address-range monitoring that is active.
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| 189 | *
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| 190 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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| 191 | */
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| 192 | VMM_INT_DECL(void) EMMonitorWaitClear(PVMCPU pVCpu)
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| 193 | {
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| 194 | LogFlowFunc(("Clearing MWAIT\n"));
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| 195 | pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
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| 196 | }
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[40357] | 197 |
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[74204] | 198 |
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[40357] | 199 | /**
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[60804] | 200 | * Determine if we should continue execution in HM after encountering an mwait
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| 201 | * instruction.
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[40357] | 202 | *
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| 203 | * Clears MWAIT flags if returning @c true.
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| 204 | *
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[48370] | 205 | * @returns true if we should continue, false if we should halt.
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[58123] | 206 | * @param pVCpu The cross context virtual CPU structure.
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[40357] | 207 | * @param pCtx Current CPU context.
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| 208 | */
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[48370] | 209 | VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
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[40357] | 210 | {
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[75998] | 211 | if (CPUMGetGuestGif(pCtx))
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[40357] | 212 | {
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[75998] | 213 | if ( CPUMIsGuestPhysIntrEnabled(pVCpu)
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| 214 | || ( CPUMIsGuestInNestedHwvirtMode(pCtx)
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| 215 | && CPUMIsGuestVirtIntrEnabled(pVCpu))
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| 216 | || ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
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| 217 | == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0)) )
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[48370] | 218 | {
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[75998] | 219 | if (VMCPU_FF_IS_ANY_SET(pVCpu, ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
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| 220 | | VMCPU_FF_INTERRUPT_NESTED_GUEST)))
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| 221 | {
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| 222 | pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
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| 223 | return true;
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| 224 | }
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[48370] | 225 | }
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[40357] | 226 | }
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| 227 |
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| 228 | return false;
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| 229 | }
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| 230 |
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| 231 |
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| 232 | /**
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[60804] | 233 | * Determine if we should continue execution in HM after encountering a hlt
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| 234 | * instruction.
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[48370] | 235 | *
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| 236 | * @returns true if we should continue, false if we should halt.
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[58123] | 237 | * @param pVCpu The cross context virtual CPU structure.
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[48370] | 238 | * @param pCtx Current CPU context.
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| 239 | */
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| 240 | VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
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| 241 | {
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[75998] | 242 | if (CPUMGetGuestGif(pCtx))
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| 243 | {
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| 244 | if (CPUMIsGuestPhysIntrEnabled(pVCpu))
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| 245 | return VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC));
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| 246 |
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| 247 | if ( CPUMIsGuestInNestedHwvirtMode(pCtx)
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| 248 | && CPUMIsGuestVirtIntrEnabled(pVCpu))
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| 249 | return VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
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| 250 | }
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[48370] | 251 | return false;
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| 252 | }
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[99051] | 253 | #endif
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[48370] | 254 |
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| 255 |
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| 256 | /**
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[65792] | 257 | * Unhalts and wakes up the given CPU.
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| 258 | *
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| 259 | * This is an API for assisting the KVM hypercall API in implementing KICK_CPU.
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| 260 | * It sets VMCPU_FF_UNHALT for @a pVCpuDst and makes sure it is woken up. If
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| 261 | * the CPU isn't currently in a halt, the next HLT instruction it executes will
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| 262 | * be affected.
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| 263 | *
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| 264 | * @returns GVMMR0SchedWakeUpEx result or VINF_SUCCESS depending on context.
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| 265 | * @param pVM The cross context VM structure.
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| 266 | * @param pVCpuDst The cross context virtual CPU structure of the
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| 267 | * CPU to unhalt and wake up. This is usually not the
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| 268 | * same as the caller.
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| 269 | * @thread EMT
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| 270 | */
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[80281] | 271 | VMM_INT_DECL(int) EMUnhaltAndWakeUp(PVMCC pVM, PVMCPUCC pVCpuDst)
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[65792] | 272 | {
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| 273 | /*
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| 274 | * Flag the current(/next) HLT to unhalt immediately.
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| 275 | */
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| 276 | VMCPU_FF_SET(pVCpuDst, VMCPU_FF_UNHALT);
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| 277 |
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| 278 | /*
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| 279 | * Wake up the EMT (technically should be abstracted by VMM/VMEmt, but
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| 280 | * just do it here for now).
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| 281 | */
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| 282 | #ifdef IN_RING0
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| 283 | /* We might be here with preemption disabled or enabled (i.e. depending on
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| 284 | thread-context hooks being used), so don't try obtaining the GVMMR0 used
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| 285 | lock here. See @bugref{7270#c148}. */
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[67989] | 286 | int rc = GVMMR0SchedWakeUpNoGVMNoLock(pVM, pVCpuDst->idCpu);
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[65792] | 287 | AssertRC(rc);
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| 288 |
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| 289 | #elif defined(IN_RING3)
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[92723] | 290 | VMR3NotifyCpuFFU(pVCpuDst->pUVCpu, 0 /*fFlags*/);
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| 291 | int rc = VINF_SUCCESS;
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| 292 | RT_NOREF(pVM);
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[65792] | 293 |
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| 294 | #else
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| 295 | /* Nothing to do for raw-mode, shouldn't really be used by raw-mode guests anyway. */
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| 296 | Assert(pVM->cCpus == 1); NOREF(pVM);
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| 297 | int rc = VINF_SUCCESS;
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| 298 | #endif
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| 299 | return rc;
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| 300 | }
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| 301 |
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[72490] | 302 | #ifndef IN_RING3
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[65792] | 303 |
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| 304 | /**
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[72490] | 305 | * Makes an I/O port write pending for ring-3 processing.
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| 306 | *
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| 307 | * @returns VINF_EM_PENDING_R3_IOPORT_READ
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| 308 | * @param pVCpu The cross context virtual CPU structure.
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| 309 | * @param uPort The I/O port.
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| 310 | * @param cbInstr The instruction length (for RIP updating).
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| 311 | * @param cbValue The write size.
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| 312 | * @param uValue The value being written.
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| 313 | * @sa emR3ExecutePendingIoPortWrite
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| 314 | *
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| 315 | * @note Must not be used when I/O port breakpoints are pending or when single stepping.
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| 316 | */
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| 317 | VMMRZ_INT_DECL(VBOXSTRICTRC)
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| 318 | EMRZSetPendingIoPortWrite(PVMCPU pVCpu, RTIOPORT uPort, uint8_t cbInstr, uint8_t cbValue, uint32_t uValue)
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| 319 | {
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| 320 | Assert(pVCpu->em.s.PendingIoPortAccess.cbValue == 0);
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| 321 | pVCpu->em.s.PendingIoPortAccess.uPort = uPort;
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| 322 | pVCpu->em.s.PendingIoPortAccess.cbValue = cbValue;
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| 323 | pVCpu->em.s.PendingIoPortAccess.cbInstr = cbInstr;
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| 324 | pVCpu->em.s.PendingIoPortAccess.uValue = uValue;
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| 325 | return VINF_EM_PENDING_R3_IOPORT_WRITE;
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| 326 | }
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| 327 |
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| 328 |
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| 329 | /**
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| 330 | * Makes an I/O port read pending for ring-3 processing.
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| 331 | *
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| 332 | * @returns VINF_EM_PENDING_R3_IOPORT_READ
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| 333 | * @param pVCpu The cross context virtual CPU structure.
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| 334 | * @param uPort The I/O port.
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| 335 | * @param cbInstr The instruction length (for RIP updating).
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| 336 | * @param cbValue The read size.
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| 337 | * @sa emR3ExecutePendingIoPortRead
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| 338 | *
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| 339 | * @note Must not be used when I/O port breakpoints are pending or when single stepping.
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| 340 | */
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| 341 | VMMRZ_INT_DECL(VBOXSTRICTRC)
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| 342 | EMRZSetPendingIoPortRead(PVMCPU pVCpu, RTIOPORT uPort, uint8_t cbInstr, uint8_t cbValue)
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| 343 | {
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| 344 | Assert(pVCpu->em.s.PendingIoPortAccess.cbValue == 0);
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| 345 | pVCpu->em.s.PendingIoPortAccess.uPort = uPort;
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| 346 | pVCpu->em.s.PendingIoPortAccess.cbValue = cbValue;
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| 347 | pVCpu->em.s.PendingIoPortAccess.cbInstr = cbInstr;
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| 348 | pVCpu->em.s.PendingIoPortAccess.uValue = UINT32_C(0x52454144); /* 'READ' */
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| 349 | return VINF_EM_PENDING_R3_IOPORT_READ;
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| 350 | }
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| 351 |
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| 352 | #endif /* IN_RING3 */
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| 353 |
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[72555] | 354 |
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[72490] | 355 | /**
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[72580] | 356 | * Worker for EMHistoryExec that checks for ring-3 returns and flags
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| 357 | * continuation of the EMHistoryExec run there.
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| 358 | */
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| 359 | DECL_FORCE_INLINE(void) emHistoryExecSetContinueExitRecIdx(PVMCPU pVCpu, VBOXSTRICTRC rcStrict, PCEMEXITREC pExitRec)
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| 360 | {
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| 361 | pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
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| 362 | #ifdef IN_RING3
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| 363 | RT_NOREF_PV(rcStrict); RT_NOREF_PV(pExitRec);
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| 364 | #else
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| 365 | switch (VBOXSTRICTRC_VAL(rcStrict))
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| 366 | {
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| 367 | case VINF_SUCCESS:
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| 368 | default:
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| 369 | break;
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| 370 |
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[72582] | 371 | /*
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| 372 | * Only status codes that EMHandleRCTmpl.h will resume EMHistoryExec with.
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| 373 | */
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[72580] | 374 | case VINF_IOM_R3_IOPORT_READ: /* -> emR3ExecuteIOInstruction */
|
---|
| 375 | case VINF_IOM_R3_IOPORT_WRITE: /* -> emR3ExecuteIOInstruction */
|
---|
| 376 | case VINF_IOM_R3_IOPORT_COMMIT_WRITE: /* -> VMCPU_FF_IOM -> VINF_EM_RESUME_R3_HISTORY_EXEC -> emR3ExecuteIOInstruction */
|
---|
| 377 | case VINF_IOM_R3_MMIO_READ: /* -> emR3ExecuteInstruction */
|
---|
| 378 | case VINF_IOM_R3_MMIO_WRITE: /* -> emR3ExecuteInstruction */
|
---|
| 379 | case VINF_IOM_R3_MMIO_READ_WRITE: /* -> emR3ExecuteInstruction */
|
---|
| 380 | case VINF_IOM_R3_MMIO_COMMIT_WRITE: /* -> VMCPU_FF_IOM -> VINF_EM_RESUME_R3_HISTORY_EXEC -> emR3ExecuteIOInstruction */
|
---|
| 381 | case VINF_CPUM_R3_MSR_READ: /* -> emR3ExecuteInstruction */
|
---|
| 382 | case VINF_CPUM_R3_MSR_WRITE: /* -> emR3ExecuteInstruction */
|
---|
| 383 | case VINF_GIM_R3_HYPERCALL: /* -> emR3ExecuteInstruction */
|
---|
| 384 | pVCpu->em.s.idxContinueExitRec = (uint16_t)(pExitRec - &pVCpu->em.s.aExitRecords[0]);
|
---|
| 385 | break;
|
---|
| 386 | }
|
---|
| 387 | #endif /* !IN_RING3 */
|
---|
| 388 | }
|
---|
| 389 |
|
---|
| 390 |
|
---|
| 391 | /**
|
---|
[72569] | 392 | * Execute using history.
|
---|
| 393 | *
|
---|
| 394 | * This function will be called when EMHistoryAddExit() and friends returns a
|
---|
| 395 | * non-NULL result. This happens in response to probing or when probing has
|
---|
| 396 | * uncovered adjacent exits which can more effectively be reached by using IEM
|
---|
| 397 | * than restarting execution using the main execution engine and fielding an
|
---|
| 398 | * regular exit.
|
---|
| 399 | *
|
---|
| 400 | * @returns VBox strict status code, see IEMExecForExits.
|
---|
| 401 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 402 | * @param pExitRec The exit record return by a previous history add
|
---|
| 403 | * or update call.
|
---|
| 404 | * @param fWillExit Flags indicating to IEM what will cause exits, TBD.
|
---|
| 405 | */
|
---|
[80253] | 406 | VMM_INT_DECL(VBOXSTRICTRC) EMHistoryExec(PVMCPUCC pVCpu, PCEMEXITREC pExitRec, uint32_t fWillExit)
|
---|
[72569] | 407 | {
|
---|
| 408 | Assert(pExitRec);
|
---|
| 409 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 410 | IEMEXECFOREXITSTATS ExecStats;
|
---|
| 411 | switch (pExitRec->enmAction)
|
---|
| 412 | {
|
---|
| 413 | /*
|
---|
| 414 | * Executes multiple instruction stopping only when we've gone a given
|
---|
| 415 | * number without perceived exits.
|
---|
| 416 | */
|
---|
| 417 | case EMEXITACTION_EXEC_WITH_MAX:
|
---|
| 418 | {
|
---|
[72582] | 419 | STAM_REL_PROFILE_START(&pVCpu->em.s.StatHistoryExec, a);
|
---|
[72569] | 420 | LogFlow(("EMHistoryExec/EXEC_WITH_MAX: %RX64, max %u\n", pExitRec->uFlatPC, pExitRec->cMaxInstructionsWithoutExit));
|
---|
| 421 | VBOXSTRICTRC rcStrict = IEMExecForExits(pVCpu, fWillExit,
|
---|
| 422 | pExitRec->cMaxInstructionsWithoutExit /* cMinInstructions*/,
|
---|
[72657] | 423 | pVCpu->em.s.cHistoryExecMaxInstructions,
|
---|
[72569] | 424 | pExitRec->cMaxInstructionsWithoutExit,
|
---|
| 425 | &ExecStats);
|
---|
| 426 | LogFlow(("EMHistoryExec/EXEC_WITH_MAX: %Rrc cExits=%u cMaxExitDistance=%u cInstructions=%u\n",
|
---|
| 427 | VBOXSTRICTRC_VAL(rcStrict), ExecStats.cExits, ExecStats.cMaxExitDistance, ExecStats.cInstructions));
|
---|
[72580] | 428 | emHistoryExecSetContinueExitRecIdx(pVCpu, rcStrict, pExitRec);
|
---|
[72674] | 429 |
|
---|
| 430 | /* Ignore instructions IEM doesn't know about. */
|
---|
| 431 | if ( ( rcStrict != VERR_IEM_INSTR_NOT_IMPLEMENTED
|
---|
| 432 | && rcStrict != VERR_IEM_ASPECT_NOT_IMPLEMENTED)
|
---|
| 433 | || ExecStats.cInstructions == 0)
|
---|
| 434 | { /* likely */ }
|
---|
| 435 | else
|
---|
| 436 | rcStrict = VINF_SUCCESS;
|
---|
| 437 |
|
---|
[72582] | 438 | if (ExecStats.cExits > 1)
|
---|
| 439 | STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryExecSavedExits, ExecStats.cExits - 1);
|
---|
| 440 | STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryExecInstructions, ExecStats.cInstructions);
|
---|
| 441 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHistoryExec, a);
|
---|
[72569] | 442 | return rcStrict;
|
---|
| 443 | }
|
---|
| 444 |
|
---|
| 445 | /*
|
---|
| 446 | * Probe a exit for close by exits.
|
---|
| 447 | */
|
---|
| 448 | case EMEXITACTION_EXEC_PROBE:
|
---|
| 449 | {
|
---|
[72582] | 450 | STAM_REL_PROFILE_START(&pVCpu->em.s.StatHistoryProbe, b);
|
---|
[72570] | 451 | LogFlow(("EMHistoryExec/EXEC_PROBE: %RX64\n", pExitRec->uFlatPC));
|
---|
[72569] | 452 | PEMEXITREC pExitRecUnconst = (PEMEXITREC)pExitRec;
|
---|
| 453 | VBOXSTRICTRC rcStrict = IEMExecForExits(pVCpu, fWillExit,
|
---|
[72657] | 454 | pVCpu->em.s.cHistoryProbeMinInstructions,
|
---|
| 455 | pVCpu->em.s.cHistoryExecMaxInstructions,
|
---|
| 456 | pVCpu->em.s.cHistoryProbeMaxInstructionsWithoutExit,
|
---|
[72569] | 457 | &ExecStats);
|
---|
| 458 | LogFlow(("EMHistoryExec/EXEC_PROBE: %Rrc cExits=%u cMaxExitDistance=%u cInstructions=%u\n",
|
---|
| 459 | VBOXSTRICTRC_VAL(rcStrict), ExecStats.cExits, ExecStats.cMaxExitDistance, ExecStats.cInstructions));
|
---|
[72580] | 460 | emHistoryExecSetContinueExitRecIdx(pVCpu, rcStrict, pExitRecUnconst);
|
---|
[72674] | 461 | if ( ExecStats.cExits >= 2
|
---|
| 462 | && RT_SUCCESS(rcStrict))
|
---|
[72569] | 463 | {
|
---|
| 464 | Assert(ExecStats.cMaxExitDistance > 0 && ExecStats.cMaxExitDistance <= 32);
|
---|
| 465 | pExitRecUnconst->cMaxInstructionsWithoutExit = ExecStats.cMaxExitDistance;
|
---|
| 466 | pExitRecUnconst->enmAction = EMEXITACTION_EXEC_WITH_MAX;
|
---|
| 467 | LogFlow(("EMHistoryExec/EXEC_PROBE: -> EXEC_WITH_MAX %u\n", ExecStats.cMaxExitDistance));
|
---|
[72582] | 468 | STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedExecWithMax);
|
---|
[72569] | 469 | }
|
---|
[72580] | 470 | #ifndef IN_RING3
|
---|
[72674] | 471 | else if ( pVCpu->em.s.idxContinueExitRec != UINT16_MAX
|
---|
| 472 | && RT_SUCCESS(rcStrict))
|
---|
[72582] | 473 | {
|
---|
| 474 | STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedToRing3);
|
---|
[72580] | 475 | LogFlow(("EMHistoryExec/EXEC_PROBE: -> ring-3\n"));
|
---|
[72582] | 476 | }
|
---|
[72580] | 477 | #endif
|
---|
[72569] | 478 | else
|
---|
| 479 | {
|
---|
| 480 | pExitRecUnconst->enmAction = EMEXITACTION_NORMAL_PROBED;
|
---|
[72580] | 481 | pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
|
---|
[72569] | 482 | LogFlow(("EMHistoryExec/EXEC_PROBE: -> PROBED\n"));
|
---|
[72582] | 483 | STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedNormal);
|
---|
[72674] | 484 | if ( rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED
|
---|
| 485 | || rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
|
---|
| 486 | rcStrict = VINF_SUCCESS;
|
---|
[72569] | 487 | }
|
---|
[72582] | 488 | STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryProbeInstructions, ExecStats.cInstructions);
|
---|
| 489 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHistoryProbe, b);
|
---|
[72569] | 490 | return rcStrict;
|
---|
| 491 | }
|
---|
| 492 |
|
---|
| 493 | /* We shouldn't ever see these here! */
|
---|
| 494 | case EMEXITACTION_FREE_RECORD:
|
---|
| 495 | case EMEXITACTION_NORMAL:
|
---|
| 496 | case EMEXITACTION_NORMAL_PROBED:
|
---|
| 497 | break;
|
---|
| 498 |
|
---|
| 499 | /* No default case, want compiler warnings. */
|
---|
| 500 | }
|
---|
| 501 | AssertLogRelFailedReturn(VERR_EM_INTERNAL_ERROR);
|
---|
| 502 | }
|
---|
| 503 |
|
---|
| 504 |
|
---|
[72580] | 505 | /**
|
---|
| 506 | * Worker for emHistoryAddOrUpdateRecord.
|
---|
| 507 | */
|
---|
[72569] | 508 | DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInit(PEMEXITREC pExitRec, uint64_t uFlatPC, uint32_t uFlagsAndType, uint64_t uExitNo)
|
---|
| 509 | {
|
---|
| 510 | pExitRec->uFlatPC = uFlatPC;
|
---|
| 511 | pExitRec->uFlagsAndType = uFlagsAndType;
|
---|
| 512 | pExitRec->enmAction = EMEXITACTION_NORMAL;
|
---|
| 513 | pExitRec->bUnused = 0;
|
---|
| 514 | pExitRec->cMaxInstructionsWithoutExit = 64;
|
---|
| 515 | pExitRec->uLastExitNo = uExitNo;
|
---|
| 516 | pExitRec->cHits = 1;
|
---|
| 517 | return NULL;
|
---|
| 518 | }
|
---|
| 519 |
|
---|
| 520 |
|
---|
[72580] | 521 | /**
|
---|
| 522 | * Worker for emHistoryAddOrUpdateRecord.
|
---|
| 523 | */
|
---|
[72569] | 524 | DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInitNew(PVMCPU pVCpu, PEMEXITENTRY pHistEntry, uintptr_t idxSlot,
|
---|
| 525 | PEMEXITREC pExitRec, uint64_t uFlatPC,
|
---|
| 526 | uint32_t uFlagsAndType, uint64_t uExitNo)
|
---|
| 527 | {
|
---|
| 528 | pHistEntry->idxSlot = (uint32_t)idxSlot;
|
---|
| 529 | pVCpu->em.s.cExitRecordUsed++;
|
---|
| 530 | LogFlow(("emHistoryRecordInitNew: [%#x] = %#07x %016RX64; (%u of %u used)\n", idxSlot, uFlagsAndType, uFlatPC,
|
---|
| 531 | pVCpu->em.s.cExitRecordUsed, RT_ELEMENTS(pVCpu->em.s.aExitRecords) ));
|
---|
| 532 | return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
|
---|
| 533 | }
|
---|
| 534 |
|
---|
| 535 |
|
---|
| 536 | /**
|
---|
[72580] | 537 | * Worker for emHistoryAddOrUpdateRecord.
|
---|
| 538 | */
|
---|
| 539 | DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInitReplacement(PEMEXITENTRY pHistEntry, uintptr_t idxSlot,
|
---|
| 540 | PEMEXITREC pExitRec, uint64_t uFlatPC,
|
---|
| 541 | uint32_t uFlagsAndType, uint64_t uExitNo)
|
---|
| 542 | {
|
---|
| 543 | pHistEntry->idxSlot = (uint32_t)idxSlot;
|
---|
| 544 | LogFlow(("emHistoryRecordInitReplacement: [%#x] = %#07x %016RX64 replacing %#07x %016RX64 with %u hits, %u exits old\n",
|
---|
| 545 | idxSlot, uFlagsAndType, uFlatPC, pExitRec->uFlagsAndType, pExitRec->uFlatPC, pExitRec->cHits,
|
---|
| 546 | uExitNo - pExitRec->uLastExitNo));
|
---|
| 547 | return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
|
---|
| 548 | }
|
---|
| 549 |
|
---|
| 550 |
|
---|
| 551 | /**
|
---|
[72569] | 552 | * Adds or updates the EMEXITREC for this PC/type and decide on an action.
|
---|
| 553 | *
|
---|
| 554 | * @returns Pointer to an exit record if special action should be taken using
|
---|
| 555 | * EMHistoryExec(). Take normal exit action when NULL.
|
---|
| 556 | *
|
---|
| 557 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 558 | * @param uFlagsAndType Combined flags and type, EMEXIT_F_KIND_EM set and
|
---|
| 559 | * both EMEXIT_F_CS_EIP and EMEXIT_F_UNFLATTENED_PC are clear.
|
---|
| 560 | * @param uFlatPC The flattened program counter.
|
---|
| 561 | * @param pHistEntry The exit history entry.
|
---|
| 562 | * @param uExitNo The current exit number.
|
---|
| 563 | */
|
---|
| 564 | static PCEMEXITREC emHistoryAddOrUpdateRecord(PVMCPU pVCpu, uint64_t uFlagsAndType, uint64_t uFlatPC,
|
---|
| 565 | PEMEXITENTRY pHistEntry, uint64_t uExitNo)
|
---|
| 566 | {
|
---|
[72642] | 567 | # ifdef IN_RING0
|
---|
[72655] | 568 | /* Disregard the hm flag. */
|
---|
| 569 | uFlagsAndType &= ~EMEXIT_F_HM;
|
---|
[72642] | 570 | # endif
|
---|
| 571 |
|
---|
[72569] | 572 | /*
|
---|
| 573 | * Work the hash table.
|
---|
| 574 | */
|
---|
| 575 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitRecords) == 1024);
|
---|
[72642] | 576 | # define EM_EXIT_RECORDS_IDX_MASK 0x3ff
|
---|
[72569] | 577 | uintptr_t idxSlot = ((uintptr_t)uFlatPC >> 1) & EM_EXIT_RECORDS_IDX_MASK;
|
---|
| 578 | PEMEXITREC pExitRec = &pVCpu->em.s.aExitRecords[idxSlot];
|
---|
| 579 | if (pExitRec->uFlatPC == uFlatPC)
|
---|
| 580 | {
|
---|
| 581 | Assert(pExitRec->enmAction != EMEXITACTION_FREE_RECORD);
|
---|
| 582 | pHistEntry->idxSlot = (uint32_t)idxSlot;
|
---|
| 583 | if (pExitRec->uFlagsAndType == uFlagsAndType)
|
---|
[72579] | 584 | {
|
---|
[72569] | 585 | pExitRec->uLastExitNo = uExitNo;
|
---|
[72579] | 586 | STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecHits[0]);
|
---|
| 587 | }
|
---|
[72569] | 588 | else
|
---|
[72579] | 589 | {
|
---|
| 590 | STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecTypeChanged[0]);
|
---|
[72569] | 591 | return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
|
---|
[72579] | 592 | }
|
---|
[72569] | 593 | }
|
---|
| 594 | else if (pExitRec->enmAction == EMEXITACTION_FREE_RECORD)
|
---|
[72579] | 595 | {
|
---|
| 596 | STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecNew[0]);
|
---|
[72569] | 597 | return emHistoryRecordInitNew(pVCpu, pHistEntry, idxSlot, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
|
---|
[72579] | 598 | }
|
---|
[72569] | 599 | else
|
---|
| 600 | {
|
---|
| 601 | /*
|
---|
[72579] | 602 | * Collision. We calculate a new hash for stepping away from the first,
|
---|
| 603 | * doing up to 8 steps away before replacing the least recently used record.
|
---|
[72569] | 604 | */
|
---|
[72579] | 605 | uintptr_t idxOldest = idxSlot;
|
---|
| 606 | uint64_t uOldestExitNo = pExitRec->uLastExitNo;
|
---|
| 607 | unsigned iOldestStep = 0;
|
---|
| 608 | unsigned iStep = 1;
|
---|
| 609 | uintptr_t const idxAdd = (uintptr_t)(uFlatPC >> 11) & (EM_EXIT_RECORDS_IDX_MASK / 4);
|
---|
| 610 | for (;;)
|
---|
| 611 | {
|
---|
| 612 | Assert(iStep < RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
|
---|
| 613 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecNew) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
|
---|
| 614 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecReplaced) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
|
---|
| 615 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecTypeChanged) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
|
---|
| 616 |
|
---|
| 617 | /* Step to the next slot. */
|
---|
| 618 | idxSlot += idxAdd;
|
---|
| 619 | idxSlot &= EM_EXIT_RECORDS_IDX_MASK;
|
---|
| 620 | pExitRec = &pVCpu->em.s.aExitRecords[idxSlot];
|
---|
| 621 |
|
---|
| 622 | /* Does it match? */
|
---|
| 623 | if (pExitRec->uFlatPC == uFlatPC)
|
---|
| 624 | {
|
---|
| 625 | Assert(pExitRec->enmAction != EMEXITACTION_FREE_RECORD);
|
---|
| 626 | pHistEntry->idxSlot = (uint32_t)idxSlot;
|
---|
| 627 | if (pExitRec->uFlagsAndType == uFlagsAndType)
|
---|
| 628 | {
|
---|
| 629 | pExitRec->uLastExitNo = uExitNo;
|
---|
| 630 | STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecHits[iStep]);
|
---|
| 631 | break;
|
---|
| 632 | }
|
---|
| 633 | STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecTypeChanged[iStep]);
|
---|
| 634 | return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
|
---|
| 635 | }
|
---|
| 636 |
|
---|
| 637 | /* Is it free? */
|
---|
| 638 | if (pExitRec->enmAction == EMEXITACTION_FREE_RECORD)
|
---|
| 639 | {
|
---|
| 640 | STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecNew[iStep]);
|
---|
| 641 | return emHistoryRecordInitNew(pVCpu, pHistEntry, idxSlot, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
|
---|
| 642 | }
|
---|
| 643 |
|
---|
| 644 | /* Is it the least recently used one? */
|
---|
| 645 | if (pExitRec->uLastExitNo < uOldestExitNo)
|
---|
| 646 | {
|
---|
| 647 | uOldestExitNo = pExitRec->uLastExitNo;
|
---|
| 648 | idxOldest = idxSlot;
|
---|
| 649 | iOldestStep = iStep;
|
---|
| 650 | }
|
---|
| 651 |
|
---|
| 652 | /* Next iteration? */
|
---|
| 653 | iStep++;
|
---|
| 654 | Assert(iStep < RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecReplaced));
|
---|
| 655 | if (RT_LIKELY(iStep < 8 + 1))
|
---|
| 656 | { /* likely */ }
|
---|
| 657 | else
|
---|
| 658 | {
|
---|
| 659 | /* Replace the least recently used slot. */
|
---|
| 660 | STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecReplaced[iOldestStep]);
|
---|
| 661 | pExitRec = &pVCpu->em.s.aExitRecords[idxOldest];
|
---|
[72580] | 662 | return emHistoryRecordInitReplacement(pHistEntry, idxOldest, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
|
---|
[72579] | 663 | }
|
---|
| 664 | }
|
---|
[72569] | 665 | }
|
---|
| 666 |
|
---|
| 667 | /*
|
---|
| 668 | * Found an existing record.
|
---|
| 669 | */
|
---|
| 670 | switch (pExitRec->enmAction)
|
---|
| 671 | {
|
---|
| 672 | case EMEXITACTION_NORMAL:
|
---|
| 673 | {
|
---|
| 674 | uint64_t const cHits = ++pExitRec->cHits;
|
---|
| 675 | if (cHits < 256)
|
---|
| 676 | return NULL;
|
---|
| 677 | LogFlow(("emHistoryAddOrUpdateRecord: [%#x] %#07x %16RX64: -> EXEC_PROBE\n", idxSlot, uFlagsAndType, uFlatPC));
|
---|
| 678 | pExitRec->enmAction = EMEXITACTION_EXEC_PROBE;
|
---|
| 679 | return pExitRec;
|
---|
| 680 | }
|
---|
| 681 |
|
---|
| 682 | case EMEXITACTION_NORMAL_PROBED:
|
---|
| 683 | pExitRec->cHits += 1;
|
---|
| 684 | return NULL;
|
---|
| 685 |
|
---|
| 686 | default:
|
---|
| 687 | pExitRec->cHits += 1;
|
---|
| 688 | return pExitRec;
|
---|
| 689 |
|
---|
| 690 | /* This will happen if the caller ignores or cannot serve the probe
|
---|
| 691 | request (forced to ring-3, whatever). We retry this 256 times. */
|
---|
| 692 | case EMEXITACTION_EXEC_PROBE:
|
---|
| 693 | {
|
---|
| 694 | uint64_t const cHits = ++pExitRec->cHits;
|
---|
| 695 | if (cHits < 512)
|
---|
| 696 | return pExitRec;
|
---|
| 697 | pExitRec->enmAction = EMEXITACTION_NORMAL_PROBED;
|
---|
| 698 | LogFlow(("emHistoryAddOrUpdateRecord: [%#x] %#07x %16RX64: -> PROBED\n", idxSlot, uFlagsAndType, uFlatPC));
|
---|
| 699 | return NULL;
|
---|
| 700 | }
|
---|
| 701 | }
|
---|
| 702 | }
|
---|
| 703 |
|
---|
| 704 |
|
---|
| 705 | /**
|
---|
[72555] | 706 | * Adds an exit to the history for this CPU.
|
---|
| 707 | *
|
---|
[72569] | 708 | * @returns Pointer to an exit record if special action should be taken using
|
---|
| 709 | * EMHistoryExec(). Take normal exit action when NULL.
|
---|
| 710 | *
|
---|
[72560] | 711 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[95560] | 712 | * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FT).
|
---|
[72560] | 713 | * @param uFlatPC The flattened program counter (RIP). UINT64_MAX if not available.
|
---|
[72555] | 714 | * @param uTimestamp The TSC value for the exit, 0 if not available.
|
---|
| 715 | * @thread EMT(pVCpu)
|
---|
| 716 | */
|
---|
[80253] | 717 | VMM_INT_DECL(PCEMEXITREC) EMHistoryAddExit(PVMCPUCC pVCpu, uint32_t uFlagsAndType, uint64_t uFlatPC, uint64_t uTimestamp)
|
---|
[72555] | 718 | {
|
---|
| 719 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 720 |
|
---|
| 721 | /*
|
---|
| 722 | * Add the exit history entry.
|
---|
| 723 | */
|
---|
| 724 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
|
---|
[72569] | 725 | uint64_t uExitNo = pVCpu->em.s.iNextExit++;
|
---|
| 726 | PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
|
---|
[72555] | 727 | pHistEntry->uFlatPC = uFlatPC;
|
---|
| 728 | pHistEntry->uTimestamp = uTimestamp;
|
---|
| 729 | pHistEntry->uFlagsAndType = uFlagsAndType;
|
---|
| 730 | pHistEntry->idxSlot = UINT32_MAX;
|
---|
| 731 |
|
---|
| 732 | /*
|
---|
[72569] | 733 | * If common exit type, we will insert/update the exit into the exit record hash table.
|
---|
[72555] | 734 | */
|
---|
[72569] | 735 | if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
|
---|
[80161] | 736 | #ifdef IN_RING0
|
---|
[72642] | 737 | && pVCpu->em.s.fExitOptimizationEnabledR0
|
---|
[72655] | 738 | && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
|
---|
[80161] | 739 | #else
|
---|
[72580] | 740 | && pVCpu->em.s.fExitOptimizationEnabled
|
---|
[80161] | 741 | #endif
|
---|
[72642] | 742 | && uFlatPC != UINT64_MAX
|
---|
| 743 | )
|
---|
[72569] | 744 | return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, uFlatPC, pHistEntry, uExitNo);
|
---|
| 745 | return NULL;
|
---|
[72555] | 746 | }
|
---|
| 747 |
|
---|
| 748 |
|
---|
[72559] | 749 | /**
|
---|
[72560] | 750 | * Interface that VT-x uses to supply the PC of an exit when CS:RIP is being read.
|
---|
| 751 | *
|
---|
| 752 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[72564] | 753 | * @param uFlatPC The flattened program counter (RIP).
|
---|
[72560] | 754 | * @param fFlattened Set if RIP was subjected to CS.BASE, clear if not.
|
---|
| 755 | */
|
---|
[92216] | 756 | VMM_INT_DECL(void) EMHistoryUpdatePC(PVMCPUCC pVCpu, uint64_t uFlatPC, bool fFlattened)
|
---|
[72560] | 757 | {
|
---|
[92216] | 758 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 759 |
|
---|
[72560] | 760 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
|
---|
[72569] | 761 | uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
|
---|
| 762 | PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
|
---|
[72560] | 763 | pHistEntry->uFlatPC = uFlatPC;
|
---|
| 764 | if (fFlattened)
|
---|
| 765 | pHistEntry->uFlagsAndType &= ~EMEXIT_F_UNFLATTENED_PC;
|
---|
| 766 | else
|
---|
| 767 | pHistEntry->uFlagsAndType |= EMEXIT_F_UNFLATTENED_PC;
|
---|
| 768 | }
|
---|
| 769 |
|
---|
| 770 |
|
---|
| 771 | /**
|
---|
[72564] | 772 | * Interface for convering a engine specific exit to a generic one and get guidance.
|
---|
| 773 | *
|
---|
[72569] | 774 | * @returns Pointer to an exit record if special action should be taken using
|
---|
| 775 | * EMHistoryExec(). Take normal exit action when NULL.
|
---|
| 776 | *
|
---|
[72564] | 777 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 778 | * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
|
---|
| 779 | * @thread EMT(pVCpu)
|
---|
| 780 | */
|
---|
[80253] | 781 | VMM_INT_DECL(PCEMEXITREC) EMHistoryUpdateFlagsAndType(PVMCPUCC pVCpu, uint32_t uFlagsAndType)
|
---|
[72564] | 782 | {
|
---|
| 783 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 784 |
|
---|
| 785 | /*
|
---|
| 786 | * Do the updating.
|
---|
| 787 | */
|
---|
| 788 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
|
---|
[72569] | 789 | uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
|
---|
| 790 | PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
|
---|
[72564] | 791 | pHistEntry->uFlagsAndType = uFlagsAndType | (pHistEntry->uFlagsAndType & (EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC));
|
---|
| 792 |
|
---|
| 793 | /*
|
---|
[72569] | 794 | * If common exit type, we will insert/update the exit into the exit record hash table.
|
---|
[72564] | 795 | */
|
---|
[72569] | 796 | if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
|
---|
[80161] | 797 | #ifdef IN_RING0
|
---|
[72642] | 798 | && pVCpu->em.s.fExitOptimizationEnabledR0
|
---|
[72655] | 799 | && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
|
---|
[80161] | 800 | #else
|
---|
[72580] | 801 | && pVCpu->em.s.fExitOptimizationEnabled
|
---|
[80161] | 802 | #endif
|
---|
[72642] | 803 | && pHistEntry->uFlatPC != UINT64_MAX
|
---|
| 804 | )
|
---|
[72569] | 805 | return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, pHistEntry->uFlatPC, pHistEntry, uExitNo);
|
---|
| 806 | return NULL;
|
---|
[72564] | 807 | }
|
---|
| 808 |
|
---|
| 809 |
|
---|
| 810 | /**
|
---|
| 811 | * Interface for convering a engine specific exit to a generic one and get
|
---|
| 812 | * guidance, supplying flattened PC too.
|
---|
| 813 | *
|
---|
[72569] | 814 | * @returns Pointer to an exit record if special action should be taken using
|
---|
| 815 | * EMHistoryExec(). Take normal exit action when NULL.
|
---|
| 816 | *
|
---|
[72564] | 817 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 818 | * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
|
---|
| 819 | * @param uFlatPC The flattened program counter (RIP).
|
---|
| 820 | * @thread EMT(pVCpu)
|
---|
| 821 | */
|
---|
[80253] | 822 | VMM_INT_DECL(PCEMEXITREC) EMHistoryUpdateFlagsAndTypeAndPC(PVMCPUCC pVCpu, uint32_t uFlagsAndType, uint64_t uFlatPC)
|
---|
[72564] | 823 | {
|
---|
| 824 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
[97331] | 825 | //Assert(uFlatPC != UINT64_MAX); - disable to make the pc wrapping tests in bs3-cpu-weird-1 work.
|
---|
[72564] | 826 |
|
---|
| 827 | /*
|
---|
| 828 | * Do the updating.
|
---|
| 829 | */
|
---|
| 830 | AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
|
---|
[72569] | 831 | uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
|
---|
| 832 | PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
|
---|
[72564] | 833 | pHistEntry->uFlagsAndType = uFlagsAndType;
|
---|
| 834 | pHistEntry->uFlatPC = uFlatPC;
|
---|
| 835 |
|
---|
| 836 | /*
|
---|
[72569] | 837 | * If common exit type, we will insert/update the exit into the exit record hash table.
|
---|
[72564] | 838 | */
|
---|
[72580] | 839 | if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
|
---|
[80161] | 840 | #ifdef IN_RING0
|
---|
[72642] | 841 | && pVCpu->em.s.fExitOptimizationEnabledR0
|
---|
[72655] | 842 | && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
|
---|
[80161] | 843 | #else
|
---|
[72642] | 844 | && pVCpu->em.s.fExitOptimizationEnabled
|
---|
[80161] | 845 | #endif
|
---|
[72642] | 846 | )
|
---|
[72569] | 847 | return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, uFlatPC, pHistEntry, uExitNo);
|
---|
| 848 | return NULL;
|
---|
[72564] | 849 | }
|
---|
| 850 |
|
---|
| 851 |
|
---|
| 852 | /**
|
---|
[41658] | 853 | * @callback_method_impl{FNDISREADBYTES}
|
---|
[1] | 854 | */
|
---|
[99208] | 855 | static DECLCALLBACK(int) emReadBytes(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
|
---|
[1] | 856 | {
|
---|
[80281] | 857 | PVMCPUCC pVCpu = (PVMCPUCC)pDis->pvUser;
|
---|
[41766] | 858 | RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
|
---|
[18927] | 859 |
|
---|
[41766] | 860 | /*
|
---|
| 861 | * Figure how much we can or must read.
|
---|
| 862 | */
|
---|
[93554] | 863 | size_t cbToRead = GUEST_PAGE_SIZE - (uSrcAddr & (GUEST_PAGE_SIZE - 1));
|
---|
[41766] | 864 | if (cbToRead > cbMaxRead)
|
---|
| 865 | cbToRead = cbMaxRead;
|
---|
| 866 | else if (cbToRead < cbMinRead)
|
---|
| 867 | cbToRead = cbMinRead;
|
---|
[21174] | 868 |
|
---|
[99220] | 869 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->u.abInstr[offInstr], uSrcAddr, cbToRead);
|
---|
[80016] | 870 | if (RT_FAILURE(rc))
|
---|
[21174] | 871 | {
|
---|
[80016] | 872 | if (cbToRead > cbMinRead)
|
---|
[41766] | 873 | {
|
---|
| 874 | cbToRead = cbMinRead;
|
---|
[99220] | 875 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->u.abInstr[offInstr], uSrcAddr, cbToRead);
|
---|
[41766] | 876 | }
|
---|
[80016] | 877 | if (RT_FAILURE(rc))
|
---|
[1] | 878 | {
|
---|
[99051] | 879 | #if defined(VBOX_VMM_TARGET_ARMV8)
|
---|
| 880 | AssertReleaseFailed();
|
---|
| 881 | #else
|
---|
[80016] | 882 | /*
|
---|
| 883 | * If we fail to find the page via the guest's page tables
|
---|
| 884 | * we invalidate the page in the host TLB (pertaining to
|
---|
| 885 | * the guest in the NestedPaging case). See @bugref{6043}.
|
---|
| 886 | */
|
---|
| 887 | if (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
|
---|
[41766] | 888 | {
|
---|
[80016] | 889 | HMInvalidatePage(pVCpu, uSrcAddr);
|
---|
[93554] | 890 | if (((uSrcAddr + cbToRead - 1) >> GUEST_PAGE_SHIFT) != (uSrcAddr >> GUEST_PAGE_SHIFT))
|
---|
[80016] | 891 | HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
|
---|
| 892 | }
|
---|
[99051] | 893 | #endif
|
---|
[1] | 894 | }
|
---|
| 895 | }
|
---|
[25550] | 896 |
|
---|
[41771] | 897 | pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
|
---|
[41766] | 898 | return rc;
|
---|
[1] | 899 | }
|
---|
| 900 |
|
---|
[25550] | 901 |
|
---|
[1] | 902 | /**
|
---|
[42186] | 903 | * Disassembles the current instruction.
|
---|
[1] | 904 | *
|
---|
[18338] | 905 | * @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
|
---|
| 906 | * details.
|
---|
| 907 | *
|
---|
[58123] | 908 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[20530] | 909 | * @param pDis Where to return the parsed instruction info.
|
---|
[1] | 910 | * @param pcbInstr Where to return the instruction size. (optional)
|
---|
| 911 | */
|
---|
[99208] | 912 | VMM_INT_DECL(int) EMInterpretDisasCurrent(PVMCPUCC pVCpu, PDISSTATE pDis, unsigned *pcbInstr)
|
---|
[1] | 913 | {
|
---|
[99051] | 914 | #if defined(VBOX_VMM_TARGET_ARMV8)
|
---|
| 915 | return EMInterpretDisasOneEx(pVCpu, (RTGCUINTPTR)CPUMGetGuestFlatPC(pVCpu), pDis, pcbInstr);
|
---|
| 916 | #else
|
---|
[97193] | 917 | PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
---|
| 918 | RTGCPTR GCPtrInstr;
|
---|
[99051] | 919 |
|
---|
| 920 | # if 0
|
---|
[97193] | 921 | int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtx, pCtx->rip, 0, &GCPtrInstr);
|
---|
[99051] | 922 | # else
|
---|
[41823] | 923 | /** @todo Get the CPU mode as well while we're at it! */
|
---|
[97218] | 924 | int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtx->eflags.u, pCtx->ss.Sel, pCtx->cs.Sel, &pCtx->cs, pCtx->rip, &GCPtrInstr);
|
---|
[99051] | 925 | # endif
|
---|
[97193] | 926 | if (RT_SUCCESS(rc))
|
---|
| 927 | return EMInterpretDisasOneEx(pVCpu, (RTGCUINTPTR)GCPtrInstr, pDis, pcbInstr);
|
---|
| 928 |
|
---|
| 929 | Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
|
---|
| 930 | pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->ss.Sel & X86_SEL_RPL, rc));
|
---|
| 931 | return rc;
|
---|
[99051] | 932 | #endif
|
---|
[1] | 933 | }
|
---|
| 934 |
|
---|
| 935 |
|
---|
| 936 | /**
|
---|
| 937 | * Disassembles one instruction.
|
---|
| 938 | *
|
---|
| 939 | * This is used by internally by the interpreter and by trap/access handlers.
|
---|
| 940 | *
|
---|
[18338] | 941 | * @returns VBox status code.
|
---|
| 942 | *
|
---|
[58123] | 943 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[1] | 944 | * @param GCPtrInstr The flat address of the instruction.
|
---|
[20530] | 945 | * @param pDis Where to return the parsed instruction info.
|
---|
[1] | 946 | * @param pcbInstr Where to return the instruction size. (optional)
|
---|
| 947 | */
|
---|
[99208] | 948 | VMM_INT_DECL(int) EMInterpretDisasOneEx(PVMCPUCC pVCpu, RTGCUINTPTR GCPtrInstr, PDISSTATE pDis, unsigned *pcbInstr)
|
---|
[1] | 949 | {
|
---|
[42186] | 950 | DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
|
---|
[41823] | 951 | /** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
|
---|
| 952 | * \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
|
---|
[41766] | 953 | int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
|
---|
[13816] | 954 | if (RT_SUCCESS(rc))
|
---|
[1] | 955 | return VINF_SUCCESS;
|
---|
[45428] | 956 | AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
|
---|
| 957 | return rc;
|
---|
[1] | 958 | }
|
---|
| 959 |
|
---|
| 960 |
|
---|
| 961 | /**
|
---|
| 962 | * Interprets the current instruction.
|
---|
| 963 | *
|
---|
| 964 | * @returns VBox status code.
|
---|
| 965 | * @retval VINF_* Scheduling instructions.
|
---|
| 966 | * @retval VERR_EM_INTERPRETER Something we can't cope with.
|
---|
| 967 | * @retval VERR_* Fatal errors.
|
---|
| 968 | *
|
---|
[58123] | 969 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[1] | 970 | *
|
---|
[97197] | 971 | * @remark Invalid opcode exceptions have a higher priority than \#GP (see
|
---|
| 972 | * Intel Architecture System Developers Manual, Vol 3, 5.5) so we don't
|
---|
| 973 | * need to worry about e.g. invalid modrm combinations (!)
|
---|
[1] | 974 | */
|
---|
[97197] | 975 | VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu)
|
---|
[1] | 976 | {
|
---|
[99051] | 977 | #if defined(VBOX_VMM_TARGET_ARMV8)
|
---|
| 978 | LogFlow(("EMInterpretInstruction %RGv\n", (RTGCPTR)CPUMGetGuestFlatPC(pVCpu)));
|
---|
| 979 | #else
|
---|
[97197] | 980 | LogFlow(("EMInterpretInstruction %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
|
---|
[99051] | 981 | #endif
|
---|
[42707] | 982 |
|
---|
[97197] | 983 | VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, NULL /*pcbWritten*/);
|
---|
[40453] | 984 | if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
|
---|
| 985 | || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
|
---|
[42707] | 986 | rc = VERR_EM_INTERPRETER;
|
---|
| 987 | if (rc != VINF_SUCCESS)
|
---|
| 988 | Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
|
---|
| 989 |
|
---|
[40442] | 990 | return rc;
|
---|
[1] | 991 | }
|
---|
| 992 |
|
---|
[12688] | 993 |
|
---|
[1] | 994 | /**
|
---|
[99208] | 995 | * Interprets the current instruction using the supplied DISSTATE structure.
|
---|
[1] | 996 | *
|
---|
[40442] | 997 | * IP/EIP/RIP *IS* updated!
|
---|
| 998 | *
|
---|
| 999 | * @returns VBox strict status code.
|
---|
| 1000 | * @retval VINF_* Scheduling instructions. When these are returned, it
|
---|
| 1001 | * starts to get a bit tricky to know whether code was
|
---|
| 1002 | * executed or not... We'll address this when it becomes a problem.
|
---|
| 1003 | * @retval VERR_EM_INTERPRETER Something we can't cope with.
|
---|
| 1004 | * @retval VERR_* Fatal errors.
|
---|
| 1005 | *
|
---|
[58126] | 1006 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[40442] | 1007 | * @param pDis The disassembler cpu state for the instruction to be
|
---|
| 1008 | * interpreted.
|
---|
[97200] | 1009 | * @param rip The instruction pointer value.
|
---|
[40442] | 1010 | *
|
---|
| 1011 | * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
|
---|
| 1012 | * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
|
---|
| 1013 | * to worry about e.g. invalid modrm combinations (!)
|
---|
| 1014 | *
|
---|
| 1015 | * @todo At this time we do NOT check if the instruction overwrites vital information.
|
---|
| 1016 | * Make sure this can't happen!! (will add some assertions/checks later)
|
---|
[1] | 1017 | */
|
---|
[99208] | 1018 | VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPUCC pVCpu, PDISSTATE pDis, uint64_t rip)
|
---|
[1] | 1019 | {
|
---|
[97200] | 1020 | LogFlow(("EMInterpretInstructionDisasState %RGv\n", (RTGCPTR)rip));
|
---|
[42707] | 1021 |
|
---|
[99220] | 1022 | VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, rip, pDis->u.abInstr, pDis->cbCachedInstr);
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[40453] | 1023 | if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
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| 1024 | || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
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[42707] | 1025 | rc = VERR_EM_INTERPRETER;
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| 1026 |
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| 1027 | if (rc != VINF_SUCCESS)
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| 1028 | Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
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| 1029 |
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[40453] | 1030 | return rc;
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[1] | 1031 | }
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| 1032 |
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