[99196] | 1 | /* $Id: CPUMAllSysRegs-armv8.cpp 99956 2023-05-24 11:39:15Z vboxsync $ */
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| 2 | /** @file
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| 3 | * CPUM - ARMv8 CPU System Registers.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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| 32 | #define LOG_GROUP LOG_GROUP_CPUM
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| 33 | #include <VBox/vmm/cpum.h>
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| 34 | #include "CPUMInternal-armv8.h"
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[99385] | 35 | #include <VBox/vmm/gic.h>
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[99196] | 36 | #include <VBox/vmm/vmcc.h>
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| 37 | #include <VBox/err.h>
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| 38 |
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[99956] | 39 | #include <iprt/armv8.h>
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[99196] | 40 |
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[99956] | 41 |
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[99196] | 42 | /*********************************************************************************************************************************
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| 43 | * Defined Constants And Macros *
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| 44 | *********************************************************************************************************************************/
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| 45 | /**
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| 46 | * Validates the CPUMSYSREGRANGE::offCpumCpu value and declares a local variable
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| 47 | * pointing to it.
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| 48 | *
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| 49 | * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
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| 50 | * correctly.
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| 51 | */
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| 52 | #define CPUM_SYSREG_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
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| 53 | AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
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| 54 | && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
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| 55 | && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
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| 56 | , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
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| 57 | VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
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| 58 | a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
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| 59 |
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| 60 |
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| 61 | /*********************************************************************************************************************************
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| 62 | * Structures and Typedefs *
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| 63 | *********************************************************************************************************************************/
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| 64 |
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| 65 | /**
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| 66 | * Implements reading one or more system registers.
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| 67 | *
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| 68 | * @returns VBox status code.
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| 69 | * @retval VINF_SUCCESS on success.
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| 70 | * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
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| 71 | * current context (raw-mode or ring-0).
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| 72 | * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid system register).
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| 73 | *
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| 74 | * @param pVCpu The cross context virtual CPU structure.
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| 75 | * @param idSysReg The system register we're reading.
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| 76 | * @param pRange The system register range descriptor.
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| 77 | * @param puValue Where to return the value.
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| 78 | */
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| 79 | typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMRDSYSREG,(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue));
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| 80 | /** Pointer to a MRS worker for a specific system register or range of system registers. */
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| 81 | typedef FNCPUMRDSYSREG *PFNCPUMRDSYSREG;
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| 82 |
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| 83 |
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| 84 | /**
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| 85 | * Implements writing one or more system registers.
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| 86 | *
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| 87 | * @retval VINF_SUCCESS on success.
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| 88 | * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
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| 89 | * current context (raw-mode or ring-0).
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| 90 | * @retval VERR_CPUM_RAISE_GP_0 on failure.
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| 91 | *
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| 92 | * @param pVCpu The cross context virtual CPU structure.
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| 93 | * @param idSysReg The system register we're writing.
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| 94 | * @param pRange The system register range descriptor.
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| 95 | * @param uValue The value to set, ignored bits masked.
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| 96 | * @param uRawValue The raw value with the ignored bits not masked.
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| 97 | */
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| 98 | typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMWRSYSREG,(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange,
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| 99 | uint64_t uValue, uint64_t uRawValue));
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| 100 | /** Pointer to a MSR worker for a specific system register or range of system registers. */
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| 101 | typedef FNCPUMWRSYSREG *PFNCPUMWRSYSREG;
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| 102 |
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| 103 |
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| 104 |
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| 105 | /*
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| 106 | * Generic functions.
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| 107 | * Generic functions.
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| 108 | * Generic functions.
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| 109 | */
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| 110 |
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| 111 |
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| 112 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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| 113 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_FixedValue(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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| 114 | {
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| 115 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg);
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| 116 | *puValue = pRange->uValue;
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| 117 | return VINF_SUCCESS;
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| 118 | }
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| 119 |
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| 120 |
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| 121 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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| 122 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_IgnoreWrite(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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| 123 | {
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| 124 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
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| 125 | Log(("CPUM: Ignoring MSR %#x (%s), %#llx\n", idSysReg, pRange->szName, uValue));
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| 126 | return VINF_SUCCESS;
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| 127 | }
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| 128 |
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| 129 |
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| 130 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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| 131 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_WriteOnly(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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| 132 | {
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| 133 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
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| 134 | return VERR_CPUM_RAISE_GP_0;
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| 135 | }
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| 136 |
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| 137 |
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| 138 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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| 139 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_ReadOnly(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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| 140 | {
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| 141 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
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| 142 | Assert(pRange->fWrExcpMask == UINT64_MAX);
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| 143 | return VERR_CPUM_RAISE_GP_0;
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| 144 | }
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| 145 |
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| 146 |
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| 147 |
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[99388] | 148 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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[99385] | 149 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_GicV3Icc(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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| 150 | {
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| 151 | RT_NOREF_PV(pRange);
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| 152 | return GICReadSysReg(pVCpu, idSysReg, puValue);
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| 153 | }
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[99196] | 154 |
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[99385] | 155 |
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[99388] | 156 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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[99385] | 157 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_GicV3Icc(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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| 158 | {
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| 159 | RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
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| 160 | return GICWriteSysReg(pVCpu, idSysReg, uValue);
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| 161 | }
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| 162 |
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| 163 |
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[99956] | 164 |
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| 165 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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| 166 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_OslsrEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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| 167 | {
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| 168 | RT_NOREF(idSysReg, pRange);
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| 169 | *puValue = pVCpu->cpum.s.Guest.fOsLck ? ARMV8_OSLSR_EL1_AARCH64_OSLK : 0;
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| 170 | return VINF_SUCCESS;
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| 171 | }
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| 172 |
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| 173 |
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| 174 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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| 175 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_OslarEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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| 176 | {
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| 177 | RT_NOREF(idSysReg, pRange, uRawValue);
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| 178 | Assert(!(uValue & ~ARMV8_OSLAR_EL1_AARCH64_OSLK));
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| 179 | pVCpu->cpum.s.Guest.fOsLck = RT_BOOL(uValue);
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| 180 | return VINF_SUCCESS;
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| 181 | }
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| 182 |
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| 183 |
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[99196] | 184 | /**
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| 185 | * System register read function table.
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| 186 | */
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| 187 | static const struct READSYSREGCLANG11WEIRDNOTHROW { PFNCPUMRDSYSREG pfnRdSysReg; } g_aCpumRdSysRegFns[kCpumSysRegRdFn_End] =
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| 188 | {
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| 189 | { NULL }, /* Invalid */
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| 190 | { cpumSysRegRd_FixedValue },
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| 191 | { NULL }, /* Alias */
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| 192 | { cpumSysRegRd_WriteOnly },
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[99385] | 193 | { cpumSysRegRd_GicV3Icc },
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[99956] | 194 | { cpumSysRegRd_OslsrEl1 },
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[99196] | 195 | };
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| 196 |
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| 197 |
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| 198 | /**
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| 199 | * System register write function table.
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| 200 | */
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| 201 | static const struct WRITESYSREGCLANG11WEIRDNOTHROW { PFNCPUMWRSYSREG pfnWrSysReg; } g_aCpumWrSysRegFns[kCpumSysRegWrFn_End] =
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| 202 | {
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| 203 | { NULL }, /* Invalid */
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| 204 | { cpumSysRegWr_IgnoreWrite },
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| 205 | { cpumSysRegWr_ReadOnly },
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| 206 | { NULL }, /* Alias */
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[99385] | 207 | { cpumSysRegWr_GicV3Icc },
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[99956] | 208 | { cpumSysRegWr_OslarEl1 },
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[99196] | 209 | };
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| 210 |
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| 211 |
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| 212 | /**
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| 213 | * Looks up the range for the given system register.
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| 214 | *
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| 215 | * @returns Pointer to the range if found, NULL if not.
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| 216 | * @param pVM The cross context VM structure.
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| 217 | * @param idSysReg The system register to look up.
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| 218 | */
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| 219 | # ifndef IN_RING3
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| 220 | static
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| 221 | # endif
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| 222 | PCPUMSYSREGRANGE cpumLookupSysRegRange(PVM pVM, uint32_t idSysReg)
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| 223 | {
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| 224 | /*
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| 225 | * Binary lookup.
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| 226 | */
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| 227 | uint32_t cRanges = RT_MIN(pVM->cpum.s.GuestInfo.cSysRegRanges, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aSysRegRanges));
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| 228 | if (!cRanges)
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| 229 | return NULL;
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| 230 | PCPUMSYSREGRANGE paRanges = pVM->cpum.s.GuestInfo.aSysRegRanges;
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| 231 | for (;;)
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| 232 | {
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| 233 | uint32_t i = cRanges / 2;
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| 234 | if (idSysReg < paRanges[i].uFirst)
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| 235 | {
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| 236 | if (i == 0)
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| 237 | break;
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| 238 | cRanges = i;
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| 239 | }
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| 240 | else if (idSysReg > paRanges[i].uLast)
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| 241 | {
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| 242 | i++;
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| 243 | if (i >= cRanges)
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| 244 | break;
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| 245 | cRanges -= i;
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| 246 | paRanges = &paRanges[i];
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| 247 | }
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| 248 | else
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| 249 | {
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| 250 | if (paRanges[i].enmRdFn == kCpumSysRegRdFn_Alias)
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| 251 | return cpumLookupSysRegRange(pVM, paRanges[i].uValue);
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| 252 | return &paRanges[i];
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| 253 | }
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| 254 | }
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| 255 |
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| 256 | # ifdef VBOX_STRICT
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| 257 | /*
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| 258 | * Linear lookup to verify the above binary search.
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| 259 | */
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| 260 | uint32_t cLeft = RT_MIN(pVM->cpum.s.GuestInfo.cSysRegRanges, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aSysRegRanges));
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| 261 | PCPUMSYSREGRANGE pCur = pVM->cpum.s.GuestInfo.aSysRegRanges;
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| 262 | while (cLeft-- > 0)
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| 263 | {
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| 264 | if (idSysReg >= pCur->uFirst && idSysReg <= pCur->uLast)
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| 265 | {
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| 266 | AssertFailed();
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| 267 | if (pCur->enmRdFn == kCpumSysRegRdFn_Alias)
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| 268 | return cpumLookupSysRegRange(pVM, pCur->uValue);
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| 269 | return pCur;
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| 270 | }
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| 271 | pCur++;
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| 272 | }
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| 273 | # endif
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| 274 | return NULL;
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| 275 | }
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| 276 |
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| 277 |
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| 278 | /**
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| 279 | * Query a guest system register.
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| 280 | *
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| 281 | * The caller is responsible for checking privilege if the call is the result of
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| 282 | * a MRS instruction. We'll do the rest.
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| 283 | *
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| 284 | * @retval VINF_SUCCESS on success.
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| 285 | * @retval VINF_CPUM_R3_MSR_READ if the system register read could not be serviced in the
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| 286 | * current context (raw-mode or ring-0).
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| 287 | * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid system register), the caller is
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| 288 | * expected to take the appropriate actions. @a *puValue is set to 0.
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| 289 | * @param pVCpu The cross context virtual CPU structure.
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| 290 | * @param idSysReg The system register.
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| 291 | * @param puValue Where to return the value.
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| 292 | *
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| 293 | * @remarks This will always return the right values, even when we're in the
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| 294 | * recompiler.
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| 295 | */
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| 296 | VMMDECL(VBOXSTRICTRC) CPUMQueryGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t *puValue)
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| 297 | {
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| 298 | *puValue = 0;
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| 299 |
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| 300 | VBOXSTRICTRC rcStrict;
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| 301 | PVM pVM = pVCpu->CTX_SUFF(pVM);
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| 302 | PCPUMSYSREGRANGE pRange = cpumLookupSysRegRange(pVM, idSysReg);
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| 303 | if (pRange)
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| 304 | {
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| 305 | CPUMSYSREGRDFN enmRdFn = (CPUMSYSREGRDFN)pRange->enmRdFn;
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| 306 | AssertReturn(enmRdFn > kCpumSysRegRdFn_Invalid && enmRdFn < kCpumSysRegRdFn_End, VERR_CPUM_IPE_1);
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| 307 |
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| 308 | PFNCPUMRDSYSREG pfnRdSysReg = g_aCpumRdSysRegFns[enmRdFn].pfnRdSysReg;
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| 309 | AssertReturn(pfnRdSysReg, VERR_CPUM_IPE_2);
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| 310 |
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| 311 | STAM_COUNTER_INC(&pRange->cReads);
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| 312 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReads);
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| 313 |
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| 314 | rcStrict = pfnRdSysReg(pVCpu, idSysReg, pRange, puValue);
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| 315 | if (rcStrict == VINF_SUCCESS)
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| 316 | Log2(("CPUM: MRS %#x (%s) -> %#llx\n", idSysReg, pRange->szName, *puValue));
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| 317 | else if (rcStrict == VERR_CPUM_RAISE_GP_0)
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| 318 | {
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| 319 | Log(("CPUM: MRS %#x (%s) -> #GP(0)\n", idSysReg, pRange->szName));
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| 320 | STAM_COUNTER_INC(&pRange->cExcp);
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| 321 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReadsRaiseExcp);
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| 322 | }
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| 323 | #ifndef IN_RING3
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| 324 | else if (rcStrict == VINF_CPUM_R3_MSR_READ)
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| 325 | Log(("CPUM: MRS %#x (%s) -> ring-3\n", idSysReg, pRange->szName));
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| 326 | #endif
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| 327 | else
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| 328 | {
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| 329 | Log(("CPUM: MRS %#x (%s) -> rcStrict=%Rrc\n", idSysReg, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
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| 330 | AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idSysReg=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idSysReg),
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| 331 | rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
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| 332 | Assert(rcStrict != VERR_EM_INTERPRETER);
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| 333 | }
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| 334 | }
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| 335 | else
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| 336 | {
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| 337 | Log(("CPUM: Unknown MRS %#x -> Ignore\n", idSysReg));
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| 338 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReads);
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| 339 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReadsUnknown);
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| 340 | *puValue = 0;
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| 341 | rcStrict = VINF_SUCCESS;
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| 342 | }
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| 343 | return rcStrict;
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| 344 | }
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| 345 |
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| 346 |
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| 347 | /**
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| 348 | * Writes to a guest system register.
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| 349 | *
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| 350 | * The caller is responsible for checking privilege if the call is the result of
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| 351 | * a MSR instruction. We'll do the rest.
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| 352 | *
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| 353 | * @retval VINF_SUCCESS on success.
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| 354 | * @retval VINF_CPUM_R3_MSR_WRITE if the system register write could not be serviced in the
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| 355 | * current context (raw-mode or ring-0).
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| 356 | * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
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| 357 | * appropriate actions.
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| 358 | *
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| 359 | * @param pVCpu The cross context virtual CPU structure.
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| 360 | * @param idSysReg The system register id.
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| 361 | * @param uValue The value to set.
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| 362 | *
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| 363 | * @remarks Everyone changing system register values, shall do it
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| 364 | * by calling this method. This makes sure we have current values and
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| 365 | * that we trigger all the right actions when something changes.
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| 366 | */
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| 367 | VMMDECL(VBOXSTRICTRC) CPUMSetGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t uValue)
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| 368 | {
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| 369 | VBOXSTRICTRC rcStrict;
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| 370 | PVM pVM = pVCpu->CTX_SUFF(pVM);
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| 371 | PCPUMSYSREGRANGE pRange = cpumLookupSysRegRange(pVM, idSysReg);
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| 372 | if (pRange)
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| 373 | {
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| 374 | STAM_COUNTER_INC(&pRange->cWrites);
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| 375 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWrites);
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| 376 |
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| 377 | if (!(uValue & pRange->fWrExcpMask))
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| 378 | {
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| 379 | CPUMSYSREGWRFN enmWrFn = (CPUMSYSREGWRFN)pRange->enmWrFn;
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| 380 | AssertReturn(enmWrFn > kCpumSysRegWrFn_Invalid && enmWrFn < kCpumSysRegWrFn_End, VERR_CPUM_IPE_1);
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| 381 |
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| 382 | PFNCPUMWRSYSREG pfnWrSysReg = g_aCpumWrSysRegFns[enmWrFn].pfnWrSysReg;
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| 383 | AssertReturn(pfnWrSysReg, VERR_CPUM_IPE_2);
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| 384 |
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| 385 | uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
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| 386 | if (uValueAdjusted != uValue)
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| 387 | {
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| 388 | STAM_COUNTER_INC(&pRange->cIgnoredBits);
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| 389 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesToIgnoredBits);
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| 390 | }
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| 391 |
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| 392 | rcStrict = pfnWrSysReg(pVCpu, idSysReg, pRange, uValueAdjusted, uValue);
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| 393 | if (rcStrict == VINF_SUCCESS)
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| 394 | Log2(("CPUM: MSR %#x (%s), %#llx [%#llx]\n", idSysReg, pRange->szName, uValueAdjusted, uValue));
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| 395 | else if (rcStrict == VERR_CPUM_RAISE_GP_0)
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| 396 | {
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| 397 | Log(("CPUM: MSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idSysReg, pRange->szName, uValueAdjusted, uValue));
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| 398 | STAM_COUNTER_INC(&pRange->cExcp);
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| 399 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesRaiseExcp);
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| 400 | }
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| 401 | #ifndef IN_RING3
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| 402 | else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
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| 403 | Log(("CPUM: MSR %#x (%s), %#llx [%#llx] -> ring-3\n", idSysReg, pRange->szName, uValueAdjusted, uValue));
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| 404 | #endif
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| 405 | else
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| 406 | {
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| 407 | Log(("CPUM: MSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
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| 408 | idSysReg, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
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| 409 | AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idSysReg=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idSysReg),
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| 410 | rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
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| 411 | Assert(rcStrict != VERR_EM_INTERPRETER);
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| 412 | }
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| 413 | }
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| 414 | else
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| 415 | {
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| 416 | Log(("CPUM: MSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
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| 417 | idSysReg, pRange->szName, uValue, uValue & pRange->fWrExcpMask));
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| 418 | STAM_COUNTER_INC(&pRange->cExcp);
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| 419 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesRaiseExcp);
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| 420 | rcStrict = VERR_CPUM_RAISE_GP_0;
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| 421 | }
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| 422 | }
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| 423 | else
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| 424 | {
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| 425 | Log(("CPUM: Unknown MSR %#x, %#llx -> #GP(0)\n", idSysReg, uValue));
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| 426 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWrites);
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| 427 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesUnknown);
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[99956] | 428 | rcStrict = VERR_CPUM_RAISE_GP_0; /** @todo Better status code. */
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[99196] | 429 | }
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| 430 | return rcStrict;
|
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| 431 | }
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| 432 |
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| 433 |
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| 434 | #if defined(VBOX_STRICT) && defined(IN_RING3)
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| 435 | /**
|
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| 436 | * Performs some checks on the static data related to MSRs.
|
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| 437 | *
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| 438 | * @returns VINF_SUCCESS on success, error on failure.
|
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| 439 | */
|
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[99385] | 440 | DECLHIDDEN(int) cpumR3SysRegStrictInitChecks(void)
|
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[99196] | 441 | {
|
---|
| 442 | #define CPUM_ASSERT_RD_SYSREG_FN(a_Register) \
|
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| 443 | AssertReturn(g_aCpumRdSysRegFns[kCpumSysRegRdFn_##a_Register].pfnRdSysReg == cpumSysRegRd_##a_Register, VERR_CPUM_IPE_2);
|
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| 444 | #define CPUM_ASSERT_WR_SYSREG_FN(a_Register) \
|
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| 445 | AssertReturn(g_aCpumWrSysRegFns[kCpumSysRegWrFn_##a_Register].pfnWrSysReg == cpumSysRegWr_##a_Register, VERR_CPUM_IPE_2);
|
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| 446 |
|
---|
| 447 | AssertReturn(g_aCpumRdSysRegFns[kCpumSysRegRdFn_Invalid].pfnRdSysReg == NULL, VERR_CPUM_IPE_2);
|
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| 448 | CPUM_ASSERT_RD_SYSREG_FN(FixedValue);
|
---|
| 449 | CPUM_ASSERT_RD_SYSREG_FN(WriteOnly);
|
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[99385] | 450 | CPUM_ASSERT_RD_SYSREG_FN(GicV3Icc);
|
---|
[99956] | 451 | CPUM_ASSERT_RD_SYSREG_FN(OslsrEl1);
|
---|
[99196] | 452 |
|
---|
| 453 | AssertReturn(g_aCpumWrSysRegFns[kCpumSysRegWrFn_Invalid].pfnWrSysReg == NULL, VERR_CPUM_IPE_2);
|
---|
[99385] | 454 | CPUM_ASSERT_WR_SYSREG_FN(IgnoreWrite);
|
---|
| 455 | CPUM_ASSERT_WR_SYSREG_FN(ReadOnly);
|
---|
| 456 | CPUM_ASSERT_WR_SYSREG_FN(GicV3Icc);
|
---|
[99956] | 457 | CPUM_ASSERT_WR_SYSREG_FN(OslarEl1);
|
---|
[99196] | 458 |
|
---|
| 459 | return VINF_SUCCESS;
|
---|
| 460 | }
|
---|
| 461 | #endif /* VBOX_STRICT && IN_RING3 */
|
---|