VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 13762

Last change on this file since 13762 was 13742, checked in by vboxsync, 16 years ago

Some initial VM data restructuring.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 83.5 KB
Line 
1/* $Id: VMM.cpp 13742 2008-11-03 12:19:40Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * The VMM component is two things at the moment, it's a component doing a few
27 * management and routing tasks, and it's the whole virtual machine monitor
28 * thing. For hysterical reasons, it is not doing all the management that one
29 * would expect, this is instead done by @ref pg_vm. We'll address this
30 * misdesign eventually.
31 *
32 * @see grp_vmm, grp_vm
33 *
34 *
35 * @section sec_vmmstate VMM State
36 *
37 * @image html VM_Statechart_Diagram.gif
38 *
39 * To be written.
40 *
41 *
42 * @subsection subsec_vmm_init VMM Initialization
43 *
44 * To be written.
45 *
46 *
47 * @subsection subsec_vmm_term VMM Termination
48 *
49 * To be written.
50 *
51 */
52
53/*******************************************************************************
54* Header Files *
55*******************************************************************************/
56#define LOG_GROUP LOG_GROUP_VMM
57#include <VBox/vmm.h>
58#include <VBox/vmapi.h>
59#include <VBox/pgm.h>
60#include <VBox/cfgm.h>
61#include <VBox/pdmqueue.h>
62#include <VBox/pdmapi.h>
63#include <VBox/cpum.h>
64#include <VBox/mm.h>
65#include <VBox/iom.h>
66#include <VBox/trpm.h>
67#include <VBox/selm.h>
68#include <VBox/em.h>
69#include <VBox/sup.h>
70#include <VBox/dbgf.h>
71#include <VBox/csam.h>
72#include <VBox/patm.h>
73#include <VBox/rem.h>
74#include <VBox/ssm.h>
75#include <VBox/tm.h>
76#include "VMMInternal.h"
77#include "VMMSwitcher/VMMSwitcher.h"
78#include <VBox/vm.h>
79
80#include <VBox/err.h>
81#include <VBox/param.h>
82#include <VBox/version.h>
83#include <VBox/x86.h>
84#include <VBox/hwaccm.h>
85#include <iprt/assert.h>
86#include <iprt/alloc.h>
87#include <iprt/asm.h>
88#include <iprt/time.h>
89#include <iprt/stream.h>
90#include <iprt/string.h>
91#include <iprt/stdarg.h>
92#include <iprt/ctype.h>
93
94
95
96/** The saved state version. */
97#define VMM_SAVED_STATE_VERSION 3
98
99
100/*******************************************************************************
101* Global Variables *
102*******************************************************************************/
103/** Array of switcher defininitions.
104 * The type and index shall match!
105 */
106static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
107{
108 NULL, /* invalid entry */
109#ifndef RT_ARCH_AMD64
110 &vmmR3Switcher32BitTo32Bit_Def,
111 &vmmR3Switcher32BitToPAE_Def,
112 NULL, //&vmmR3Switcher32BitToAMD64_Def,
113 &vmmR3SwitcherPAETo32Bit_Def,
114 &vmmR3SwitcherPAEToPAE_Def,
115 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
116# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
117 &vmmR3SwitcherAMD64ToPAE_Def,
118# else
119 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
120# endif
121 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
122#else /* RT_ARCH_AMD64 */
123 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
124 NULL, //&vmmR3Switcher32BitToPAE_Def,
125 NULL, //&vmmR3Switcher32BitToAMD64_Def,
126 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
127 NULL, //&vmmR3SwitcherPAEToPAE_Def,
128 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
129 &vmmR3SwitcherAMD64ToPAE_Def,
130 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
131#endif /* RT_ARCH_AMD64 */
132};
133
134
135/*******************************************************************************
136* Internal Functions *
137*******************************************************************************/
138static int vmmR3InitCoreCode(PVM pVM);
139static int vmmR3InitStacks(PVM pVM);
140static int vmmR3InitLoggers(PVM pVM);
141static void vmmR3InitRegisterStats(PVM pVM);
142static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
143static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
144static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
145static int vmmR3ServiceCallHostRequest(PVM pVM);
146static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
147
148
149/**
150 * Initializes the VMM.
151 *
152 * @returns VBox status code.
153 * @param pVM The VM to operate on.
154 */
155VMMR3DECL(int) VMMR3Init(PVM pVM)
156{
157 LogFlow(("VMMR3Init\n"));
158
159 /*
160 * Assert alignment, sizes and order.
161 */
162 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
163 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
164 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
165 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
166
167 /*
168 * Init basic VM VMM members.
169 */
170 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
171 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
172 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
173 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
174 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
175 else
176 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
177
178 /* GC switchers are enabled by default. Turned off by HWACCM. */
179 pVM->vmm.s.fSwitcherDisabled = false;
180
181 /*
182 * Register the saved state data unit.
183 */
184 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
185 NULL, vmmR3Save, NULL,
186 NULL, vmmR3Load, NULL);
187 if (VBOX_FAILURE(rc))
188 return rc;
189
190 /*
191 * Register the Ring-0 VM handle with the session for fast ioctl calls.
192 */
193 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
194 if (VBOX_FAILURE(rc))
195 return rc;
196
197 /*
198 * Init various sub-components.
199 */
200 rc = vmmR3InitCoreCode(pVM);
201 if (RT_SUCCESS(rc))
202 {
203 rc = vmmR3InitStacks(pVM);
204 if (RT_SUCCESS(rc))
205 {
206 rc = vmmR3InitLoggers(pVM);
207
208#ifdef VBOX_WITH_NMI
209 /*
210 * Allocate mapping for the host APIC.
211 */
212 if (RT_SUCCESS(rc))
213 {
214 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
215 AssertRC(rc);
216 }
217#endif
218 if (RT_SUCCESS(rc))
219 {
220 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
221 if (VBOX_SUCCESS(rc))
222 {
223 /*
224 * Debug info and statistics.
225 */
226 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
227 vmmR3InitRegisterStats(pVM);
228
229 return VINF_SUCCESS;
230 }
231 }
232 }
233 /** @todo: Need failure cleanup. */
234
235 //more todo in here?
236 //if (VBOX_SUCCESS(rc))
237 //{
238 //}
239 //int rc2 = vmmR3TermCoreCode(pVM);
240 //AssertRC(rc2));
241 }
242
243 return rc;
244}
245
246
247/**
248 * VMMR3Init worker that initiates the core code.
249 *
250 * This is core per VM code which might need fixups and/or for ease of use are
251 * put on linear contiguous backing.
252 *
253 * @returns VBox status code.
254 * @param pVM Pointer to the shared VM structure.
255 */
256static int vmmR3InitCoreCode(PVM pVM)
257{
258 /*
259 * Calc the size.
260 */
261 unsigned cbCoreCode = 0;
262 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
263 {
264 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
265 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
266 if (pSwitcher)
267 {
268 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
269 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
270 }
271 }
272
273 /*
274 * Allocate continguous pages for switchers and deal with
275 * conflicts in the intermediate mapping of the code.
276 */
277 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
278 pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
279 int rc = VERR_NO_MEMORY;
280 if (pVM->vmm.s.pvCoreCodeR3)
281 {
282 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
283 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
284 {
285 /* try more allocations - Solaris, Linux. */
286 const unsigned cTries = 8234;
287 struct VMMInitBadTry
288 {
289 RTR0PTR pvR0;
290 void *pvR3;
291 RTHCPHYS HCPhys;
292 RTUINT cb;
293 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
294 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
295 unsigned i = 0;
296 do
297 {
298 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
299 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
300 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
301 i++;
302 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
303 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
304 pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
305 if (!pVM->vmm.s.pvCoreCodeR3)
306 break;
307 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
308 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
309 && i < cTries - 1);
310
311 /* cleanup */
312 if (VBOX_FAILURE(rc))
313 {
314 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
315 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
316 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
317 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
318 i++;
319 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
320 }
321 while (i-- > 0)
322 {
323 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
324 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
325 SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
326 }
327 RTMemTmpFree(paBadTries);
328 }
329 }
330 if (VBOX_SUCCESS(rc))
331 {
332 /*
333 * copy the code.
334 */
335 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
336 {
337 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
338 if (pSwitcher)
339 memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
340 pSwitcher->pvCode, pSwitcher->cbCode);
341 }
342
343 /*
344 * Map the code into the GC address space.
345 */
346 RTGCPTR GCPtr;
347 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
348 if (VBOX_SUCCESS(rc))
349 {
350 pVM->vmm.s.pvCoreCodeRC = GCPtr;
351 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
352 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
353 pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
354
355 /*
356 * Finally, PGM probably have selected a switcher already but we need
357 * to get the routine addresses, so we'll reselect it.
358 * This may legally fail so, we're ignoring the rc.
359 */
360 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
361 return rc;
362 }
363
364 /* shit */
365 AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
366 SUPContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
367 }
368 else
369 VMSetError(pVM, rc, RT_SRC_POS,
370 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
371 cbCoreCode);
372
373 pVM->vmm.s.pvCoreCodeR3 = NULL;
374 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
375 pVM->vmm.s.pvCoreCodeRC = 0;
376 return rc;
377}
378
379
380/**
381 * Allocate & setup the VMM RC stack(s) (for EMTs).
382 *
383 * The stacks are also used for long jumps in Ring-0.
384 *
385 * @returns VBox status code.
386 * @param pVM Pointer to the shared VM structure.
387 *
388 * @remarks The optional guard page gets it protection setup up during R3 init
389 * completion because of init order issues.
390 */
391static int vmmR3InitStacks(PVM pVM)
392{
393 /** @todo SMP: On stack per vCPU. */
394#ifdef VBOX_STRICT_VMM_STACK
395 int rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbEMTStackR3);
396#else
397 int rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbEMTStackR3);
398#endif
399 if (VBOX_SUCCESS(rc))
400 {
401 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = MMHyperR3ToR0(pVM, pVM->vmm.s.pbEMTStackR3);
402 pVM->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3);
403 pVM->vmm.s.pbEMTStackBottomRC = pVM->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
404 AssertRelease(pVM->vmm.s.pbEMTStackRC);
405
406 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC);
407 }
408
409 return rc;
410}
411
412
413/**
414 * Initialize the loggers.
415 *
416 * @returns VBox status code.
417 * @param pVM Pointer to the shared VM structure.
418 */
419static int vmmR3InitLoggers(PVM pVM)
420{
421 int rc;
422
423 /*
424 * Allocate RC & R0 Logger instances (they are finalized in the relocator).
425 */
426#ifdef LOG_ENABLED
427 PRTLOGGER pLogger = RTLogDefaultInstance();
428 if (pLogger)
429 {
430 pVM->vmm.s.cbRCLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
431 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRCLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCLoggerR3);
432 if (RT_FAILURE(rc))
433 return rc;
434 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
435
436# ifdef VBOX_WITH_R0_LOGGING
437 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
438 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0LoggerR3);
439 if (RT_FAILURE(rc))
440 return rc;
441 pVM->vmm.s.pR0LoggerR3->pVM = pVM->pVMR0;
442 //pVM->vmm.s.pR0LoggerR3->fCreated = false;
443 pVM->vmm.s.pR0LoggerR3->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
444 pVM->vmm.s.pR0LoggerR0 = MMHyperR3ToR0(pVM, pVM->vmm.s.pR0LoggerR3);
445# endif
446 }
447#endif /* LOG_ENABLED */
448
449#ifdef VBOX_WITH_RC_RELEASE_LOGGING
450 /*
451 * Allocate RC release logger instances (finalized in the relocator).
452 */
453 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
454 if (pRelLogger)
455 {
456 pVM->vmm.s.cbRCRelLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
457 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRCRelLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCRelLoggerR3);
458 if (RT_FAILURE(rc))
459 return rc;
460 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
461 }
462#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
463 return VINF_SUCCESS;
464}
465
466
467/**
468 * VMMR3Init worker that register the statistics with STAM.
469 *
470 * @param pVM The shared VM structure.
471 */
472static void vmmR3InitRegisterStats(PVM pVM)
473{
474 /*
475 * Statistics.
476 */
477 STAM_REG(pVM, &pVM->vmm.s.StatRunRC, STAMTYPE_COUNTER, "/VMM/RunRC", STAMUNIT_OCCURENCES, "Number of context switches.");
478 STAM_REG(pVM, &pVM->vmm.s.StatRZRetNormal, STAMTYPE_COUNTER, "/VMM/RZRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
479 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterrupt, STAMTYPE_COUNTER, "/VMM/RZRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
480 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
481 STAM_REG(pVM, &pVM->vmm.s.StatRZRetGuestTrap, STAMTYPE_COUNTER, "/VMM/RZRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
482 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitch, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
483 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
484 STAM_REG(pVM, &pVM->vmm.s.StatRZRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/RZRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
485 STAM_REG(pVM, &pVM->vmm.s.StatRZRetStaleSelector, STAMTYPE_COUNTER, "/VMM/RZRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
486 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIRETTrap, STAMTYPE_COUNTER, "/VMM/RZRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
487 STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
488 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIORead, STAMTYPE_COUNTER, "/VMM/RZRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIORead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatRZRetLDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatRZRetGDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatRZRetTSSFault, STAMTYPE_COUNTER, "/VMM/RZRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPDFault, STAMTYPE_COUNTER, "/VMM/RZRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatRZRetCSAMTask, STAMTYPE_COUNTER, "/VMM/RZRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatRZRetSyncCR3, STAMTYPE_COUNTER, "/VMM/RZRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMisc, STAMTYPE_COUNTER, "/VMM/RZRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchInt3, STAMTYPE_COUNTER, "/VMM/RZRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchPF, STAMTYPE_COUNTER, "/VMM/RZRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchGP, STAMTYPE_COUNTER, "/VMM/RZRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/RZRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPageOverflow, STAMTYPE_COUNTER, "/VMM/RZRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/RZRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatRZRetTimerPending, STAMTYPE_COUNTER, "/VMM/RZRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptPending, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/RZRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/RZRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulHlt, STAMTYPE_COUNTER, "/VMM/RZRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPendingRequest, STAMTYPE_COUNTER, "/VMM/RZRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
517
518 STAM_REG(pVM, &pVM->vmm.s.StatRZRetCallHost, STAMTYPE_COUNTER, "/VMM/RZCallR3/Misc", STAMUNIT_OCCURENCES, "Number of Other ring-3 calls.");
519 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PDM_LOCK calls.");
520 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMQueueFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PDM_QUEUE_FLUSH calls.");
521 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_LOCK calls.");
522 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMPoolGrow", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_POOL_GROW calls.");
523 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMMapChunk, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMMapChunk", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_MAP_CHUNK calls.");
524 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMAllocHandy, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMAllocHandy", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES calls.");
525#ifndef VBOX_WITH_NEW_PHYS_CODE
526 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMGrowRAM", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_RAM_GROW_RANGE calls.");
527#endif
528 STAM_REG(pVM, &pVM->vmm.s.StatRZCallRemReplay, STAMTYPE_COUNTER, "/VMM/RZCallR3/REMReplay", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS calls.");
529 STAM_REG(pVM, &pVM->vmm.s.StatRZCallLogFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMMLogFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VMM_LOGGER_FLUSH calls.");
530 STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMSetError", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VM_SET_ERROR calls.");
531 STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetRuntimeError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMRuntimeError", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VM_SET_RUNTIME_ERROR calls.");
532}
533
534
535/**
536 * Ring-3 init finalizing.
537 *
538 * @returns VBox status code.
539 * @param pVM The VM handle.
540 */
541VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
542{
543#ifdef VBOX_STRICT_VMM_STACK
544 /*
545 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
546 */
547 memset(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, 0xcc, PAGE_SIZE);
548 PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE), PAGE_SIZE, 0);
549 RTMemProtect(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
550
551 memset(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
552 PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE), PAGE_SIZE, 0);
553 RTMemProtect(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
554#endif
555
556 /*
557 * Set page attributes to r/w for stack pages.
558 */
559 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbEMTStackRC, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
560 AssertRC(rc);
561 if (VBOX_SUCCESS(rc))
562 {
563 /*
564 * Create the EMT yield timer.
565 */
566 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
567 if (VBOX_SUCCESS(rc))
568 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
569 }
570
571#ifdef VBOX_WITH_NMI
572 /*
573 * Map the host APIC into GC - This is AMD/Intel + Host OS specific!
574 */
575 if (VBOX_SUCCESS(rc))
576 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
577 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
578#endif
579 return rc;
580}
581
582
583/**
584 * Initializes the R0 VMM.
585 *
586 * @returns VBox status code.
587 * @param pVM The VM to operate on.
588 */
589VMMR3DECL(int) VMMR3InitR0(PVM pVM)
590{
591 int rc;
592
593 /*
594 * Initialize the ring-0 logger if we haven't done so yet.
595 */
596 if ( pVM->vmm.s.pR0LoggerR3
597 && !pVM->vmm.s.pR0LoggerR3->fCreated)
598 {
599 rc = VMMR3UpdateLoggers(pVM);
600 if (VBOX_FAILURE(rc))
601 return rc;
602 }
603
604 /*
605 * Call Ring-0 entry with init code.
606 */
607 for (;;)
608 {
609#ifdef NO_SUPCALLR0VMM
610 //rc = VERR_GENERAL_FAILURE;
611 rc = VINF_SUCCESS;
612#else
613 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
614#endif
615 if ( pVM->vmm.s.pR0LoggerR3
616 && pVM->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
617 RTLogFlushToLogger(&pVM->vmm.s.pR0LoggerR3->Logger, NULL);
618 if (rc != VINF_VMM_CALL_HOST)
619 break;
620 rc = vmmR3ServiceCallHostRequest(pVM);
621 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
622 break;
623 /* Resume R0 */
624 }
625
626 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
627 {
628 LogRel(("R0 init failed, rc=%Vra\n", rc));
629 if (VBOX_SUCCESS(rc))
630 rc = VERR_INTERNAL_ERROR;
631 }
632 return rc;
633}
634
635
636/**
637 * Initializes the RC VMM.
638 *
639 * @returns VBox status code.
640 * @param pVM The VM to operate on.
641 */
642VMMR3DECL(int) VMMR3InitRC(PVM pVM)
643{
644 /* In VMX mode, there's no need to init RC. */
645 if (pVM->vmm.s.fSwitcherDisabled)
646 return VINF_SUCCESS;
647
648 /*
649 * Call VMMGCInit():
650 * -# resolve the address.
651 * -# setup stackframe and EIP to use the trampoline.
652 * -# do a generic hypervisor call.
653 */
654 RTGCPTR32 GCPtrEP;
655 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
656 if (VBOX_SUCCESS(rc))
657 {
658 CPUMHyperSetCtxCore(pVM, NULL);
659 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
660 uint64_t u64TS = RTTimeProgramStartNanoTS();
661 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
662 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
663 CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
664 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
665 CPUMPushHyper(pVM, pVM->pVMRC); /* Param 0: pVM */
666 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
667 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
668 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnCallTrampolineRC);
669
670 for (;;)
671 {
672#ifdef NO_SUPCALLR0VMM
673 //rc = VERR_GENERAL_FAILURE;
674 rc = VINF_SUCCESS;
675#else
676 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
677#endif
678#ifdef LOG_ENABLED
679 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
680 if ( pLogger
681 && pLogger->offScratch > 0)
682 RTLogFlushRC(NULL, pLogger);
683#endif
684#ifdef VBOX_WITH_RC_RELEASE_LOGGING
685 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
686 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
687 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
688#endif
689 if (rc != VINF_VMM_CALL_HOST)
690 break;
691 rc = vmmR3ServiceCallHostRequest(pVM);
692 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
693 break;
694 }
695
696 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
697 {
698 VMMR3FatalDump(pVM, rc);
699 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
700 rc = VERR_INTERNAL_ERROR;
701 }
702 AssertRC(rc);
703 }
704 return rc;
705}
706
707
708/**
709 * Terminate the VMM bits.
710 *
711 * @returns VINF_SUCCESS.
712 * @param pVM The VM handle.
713 */
714VMMR3DECL(int) VMMR3Term(PVM pVM)
715{
716 /*
717 * Call Ring-0 entry with termination code.
718 */
719 int rc;
720 for (;;)
721 {
722#ifdef NO_SUPCALLR0VMM
723 //rc = VERR_GENERAL_FAILURE;
724 rc = VINF_SUCCESS;
725#else
726 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
727#endif
728 if ( pVM->vmm.s.pR0LoggerR3
729 && pVM->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
730 RTLogFlushToLogger(&pVM->vmm.s.pR0LoggerR3->Logger, NULL);
731 if (rc != VINF_VMM_CALL_HOST)
732 break;
733 rc = vmmR3ServiceCallHostRequest(pVM);
734 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
735 break;
736 /* Resume R0 */
737 }
738 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
739 {
740 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
741 if (VBOX_SUCCESS(rc))
742 rc = VERR_INTERNAL_ERROR;
743 }
744
745#ifdef VBOX_STRICT_VMM_STACK
746 /*
747 * Make the two stack guard pages present again.
748 */
749 RTMemProtect(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
750 RTMemProtect(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
751#endif
752 return rc;
753}
754
755
756/**
757 * Applies relocations to data and code managed by this
758 * component. This function will be called at init and
759 * whenever the VMM need to relocate it self inside the GC.
760 *
761 * The VMM will need to apply relocations to the core code.
762 *
763 * @param pVM The VM handle.
764 * @param offDelta The relocation delta.
765 */
766VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
767{
768 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
769
770 /*
771 * Recalc the RC address.
772 */
773 pVM->vmm.s.pvCoreCodeRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pvCoreCodeR3);
774
775 /*
776 * The stack.
777 */
778 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
779 pVM->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3);
780 pVM->vmm.s.pbEMTStackBottomRC = pVM->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
781
782 /*
783 * All the switchers.
784 */
785 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
786 {
787 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
788 if (pSwitcher && pSwitcher->pfnRelocate)
789 {
790 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
791 pSwitcher->pfnRelocate(pVM,
792 pSwitcher,
793 pVM->vmm.s.pvCoreCodeR0 + off,
794 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
795 pVM->vmm.s.pvCoreCodeRC + off,
796 pVM->vmm.s.HCPhysCoreCode + off);
797 }
798 }
799
800 /*
801 * Recalc the RC address for the current switcher.
802 */
803 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
804 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
805 pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
806 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
807 pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
808 pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
809 pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
810
811 /*
812 * Get other RC entry points.
813 */
814 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMRCResumeGuest);
815 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
816
817 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMRCResumeGuestV86);
818 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
819
820 /*
821 * Update the logger.
822 */
823 VMMR3UpdateLoggers(pVM);
824}
825
826
827/**
828 * Updates the settings for the RC and R0 loggers.
829 *
830 * @returns VBox status code.
831 * @param pVM The VM handle.
832 */
833VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
834{
835 /*
836 * Simply clone the logger instance (for RC).
837 */
838 int rc = VINF_SUCCESS;
839 RTRCPTR RCPtrLoggerFlush = 0;
840
841 if (pVM->vmm.s.pRCLoggerR3
842#ifdef VBOX_WITH_RC_RELEASE_LOGGING
843 || pVM->vmm.s.pRCRelLoggerR3
844#endif
845 )
846 {
847 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &RCPtrLoggerFlush);
848 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
849 }
850
851 if (pVM->vmm.s.pRCLoggerR3)
852 {
853 RTRCPTR RCPtrLoggerWrapper = 0;
854 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &RCPtrLoggerWrapper);
855 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
856
857 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
858 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pRCLoggerR3, pVM->vmm.s.cbRCLogger,
859 RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
860 AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Vra\n", rc));
861 }
862
863#ifdef VBOX_WITH_RC_RELEASE_LOGGING
864 if (pVM->vmm.s.pRCRelLoggerR3)
865 {
866 RTRCPTR RCPtrLoggerWrapper = 0;
867 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &RCPtrLoggerWrapper);
868 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
869
870 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
871 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRCRelLoggerR3, pVM->vmm.s.cbRCRelLogger,
872 RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
873 AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Vra\n", rc));
874 }
875#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
876
877 /*
878 * For the ring-0 EMT logger, we use a per-thread logger instance
879 * in ring-0. Only initialize it once.
880 */
881 PVMMR0LOGGER pR0LoggerR3 = pVM->vmm.s.pR0LoggerR3;
882 if (pR0LoggerR3)
883 {
884 if (!pR0LoggerR3->fCreated)
885 {
886 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
887 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
888 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
889
890 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
891 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
892 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
893
894 rc = RTLogCreateForR0(&pR0LoggerR3->Logger, pR0LoggerR3->cbLogger,
895 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
896 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
897 AssertReleaseMsgRCReturn(rc, ("RTLogCreateForR0 failed! rc=%Vra\n", rc), rc);
898 pR0LoggerR3->fCreated = true;
899 }
900
901 rc = RTLogCopyGroupsAndFlags(&pR0LoggerR3->Logger, NULL /* default */, pVM->vmm.s.pRCLoggerR3->fFlags, RTLOGFLAGS_BUFFERED);
902 AssertRC(rc);
903 }
904
905 return rc;
906}
907
908
909/**
910 * Generic switch code relocator.
911 *
912 * @param pVM The VM handle.
913 * @param pSwitcher The switcher definition.
914 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
915 * @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
916 * @param GCPtrCode The guest context address corresponding to pu8Code.
917 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
918 * @param SelCS The hypervisor CS selector.
919 * @param SelDS The hypervisor DS selector.
920 * @param SelTSS The hypervisor TSS selector.
921 * @param GCPtrGDT The GC address of the hypervisor GDT.
922 * @param SelCS64 The 64-bit mode hypervisor CS selector.
923 */
924static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
925 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
926{
927 union
928 {
929 const uint8_t *pu8;
930 const uint16_t *pu16;
931 const uint32_t *pu32;
932 const uint64_t *pu64;
933 const void *pv;
934 uintptr_t u;
935 } u;
936 u.pv = pSwitcher->pvFixups;
937
938 /*
939 * Process fixups.
940 */
941 uint8_t u8;
942 while ((u8 = *u.pu8++) != FIX_THE_END)
943 {
944 /*
945 * Get the source (where to write the fixup).
946 */
947 uint32_t offSrc = *u.pu32++;
948 Assert(offSrc < pSwitcher->cbCode);
949 union
950 {
951 uint8_t *pu8;
952 uint16_t *pu16;
953 uint32_t *pu32;
954 uint64_t *pu64;
955 uintptr_t u;
956 } uSrc;
957 uSrc.pu8 = pu8CodeR3 + offSrc;
958
959 /* The fixup target and method depends on the type. */
960 switch (u8)
961 {
962 /*
963 * 32-bit relative, source in HC and target in GC.
964 */
965 case FIX_HC_2_GC_NEAR_REL:
966 {
967 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
968 uint32_t offTrg = *u.pu32++;
969 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
970 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
971 break;
972 }
973
974 /*
975 * 32-bit relative, source in HC and target in ID.
976 */
977 case FIX_HC_2_ID_NEAR_REL:
978 {
979 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
980 uint32_t offTrg = *u.pu32++;
981 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
982 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
983 break;
984 }
985
986 /*
987 * 32-bit relative, source in GC and target in HC.
988 */
989 case FIX_GC_2_HC_NEAR_REL:
990 {
991 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
992 uint32_t offTrg = *u.pu32++;
993 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
994 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
995 break;
996 }
997
998 /*
999 * 32-bit relative, source in GC and target in ID.
1000 */
1001 case FIX_GC_2_ID_NEAR_REL:
1002 {
1003 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1004 uint32_t offTrg = *u.pu32++;
1005 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1006 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1007 break;
1008 }
1009
1010 /*
1011 * 32-bit relative, source in ID and target in HC.
1012 */
1013 case FIX_ID_2_HC_NEAR_REL:
1014 {
1015 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1016 uint32_t offTrg = *u.pu32++;
1017 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1018 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
1019 break;
1020 }
1021
1022 /*
1023 * 32-bit relative, source in ID and target in HC.
1024 */
1025 case FIX_ID_2_GC_NEAR_REL:
1026 {
1027 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1028 uint32_t offTrg = *u.pu32++;
1029 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1030 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1031 break;
1032 }
1033
1034 /*
1035 * 16:32 far jump, target in GC.
1036 */
1037 case FIX_GC_FAR32:
1038 {
1039 uint32_t offTrg = *u.pu32++;
1040 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1041 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1042 *uSrc.pu16++ = SelCS;
1043 break;
1044 }
1045
1046 /*
1047 * Make 32-bit GC pointer given CPUM offset.
1048 */
1049 case FIX_GC_CPUM_OFF:
1050 {
1051 uint32_t offCPUM = *u.pu32++;
1052 Assert(offCPUM < sizeof(pVM->cpum));
1053 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1054 break;
1055 }
1056
1057 /*
1058 * Make 32-bit GC pointer given VM offset.
1059 */
1060 case FIX_GC_VM_OFF:
1061 {
1062 uint32_t offVM = *u.pu32++;
1063 Assert(offVM < sizeof(VM));
1064 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1065 break;
1066 }
1067
1068 /*
1069 * Make 32-bit HC pointer given CPUM offset.
1070 */
1071 case FIX_HC_CPUM_OFF:
1072 {
1073 uint32_t offCPUM = *u.pu32++;
1074 Assert(offCPUM < sizeof(pVM->cpum));
1075 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1076 break;
1077 }
1078
1079 /*
1080 * Make 32-bit R0 pointer given VM offset.
1081 */
1082 case FIX_HC_VM_OFF:
1083 {
1084 uint32_t offVM = *u.pu32++;
1085 Assert(offVM < sizeof(VM));
1086 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1087 break;
1088 }
1089
1090 /*
1091 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1092 */
1093 case FIX_INTER_32BIT_CR3:
1094 {
1095
1096 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1097 break;
1098 }
1099
1100 /*
1101 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1102 */
1103 case FIX_INTER_PAE_CR3:
1104 {
1105
1106 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1107 break;
1108 }
1109
1110 /*
1111 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1112 */
1113 case FIX_INTER_AMD64_CR3:
1114 {
1115
1116 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1117 break;
1118 }
1119
1120 /*
1121 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1122 */
1123 case FIX_HYPER_32BIT_CR3:
1124 {
1125
1126 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1127 break;
1128 }
1129
1130 /*
1131 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1132 */
1133 case FIX_HYPER_PAE_CR3:
1134 {
1135
1136 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1137 break;
1138 }
1139
1140 /*
1141 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1142 */
1143 case FIX_HYPER_AMD64_CR3:
1144 {
1145
1146 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1147 break;
1148 }
1149
1150 /*
1151 * Store Hypervisor CS (16-bit).
1152 */
1153 case FIX_HYPER_CS:
1154 {
1155 *uSrc.pu16 = SelCS;
1156 break;
1157 }
1158
1159 /*
1160 * Store Hypervisor DS (16-bit).
1161 */
1162 case FIX_HYPER_DS:
1163 {
1164 *uSrc.pu16 = SelDS;
1165 break;
1166 }
1167
1168 /*
1169 * Store Hypervisor TSS (16-bit).
1170 */
1171 case FIX_HYPER_TSS:
1172 {
1173 *uSrc.pu16 = SelTSS;
1174 break;
1175 }
1176
1177 /*
1178 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1179 */
1180 case FIX_GC_TSS_GDTE_DW2:
1181 {
1182 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1183 *uSrc.pu32 = (uint32_t)GCPtr;
1184 break;
1185 }
1186
1187
1188 ///@todo case FIX_CR4_MASK:
1189 ///@todo case FIX_CR4_OSFSXR:
1190
1191 /*
1192 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1193 */
1194 case FIX_NO_FXSAVE_JMP:
1195 {
1196 uint32_t offTrg = *u.pu32++;
1197 Assert(offTrg < pSwitcher->cbCode);
1198 if (!CPUMSupportsFXSR(pVM))
1199 {
1200 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1201 *uSrc.pu32++ = offTrg - (offSrc + 5);
1202 }
1203 else
1204 {
1205 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1206 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1207 }
1208 break;
1209 }
1210
1211 /*
1212 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1213 */
1214 case FIX_NO_SYSENTER_JMP:
1215 {
1216 uint32_t offTrg = *u.pu32++;
1217 Assert(offTrg < pSwitcher->cbCode);
1218 if (!CPUMIsHostUsingSysEnter(pVM))
1219 {
1220 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1221 *uSrc.pu32++ = offTrg - (offSrc + 5);
1222 }
1223 else
1224 {
1225 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1226 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1227 }
1228 break;
1229 }
1230
1231 /*
1232 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1233 */
1234 case FIX_NO_SYSCALL_JMP:
1235 {
1236 uint32_t offTrg = *u.pu32++;
1237 Assert(offTrg < pSwitcher->cbCode);
1238 if (!CPUMIsHostUsingSysEnter(pVM))
1239 {
1240 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1241 *uSrc.pu32++ = offTrg - (offSrc + 5);
1242 }
1243 else
1244 {
1245 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1246 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1247 }
1248 break;
1249 }
1250
1251 /*
1252 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1253 */
1254 case FIX_HC_32BIT:
1255 {
1256 uint32_t offTrg = *u.pu32++;
1257 Assert(offSrc < pSwitcher->cbCode);
1258 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1259 *uSrc.pu32 = R0PtrCode + offTrg;
1260 break;
1261 }
1262
1263#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1264 /*
1265 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1266 */
1267 case FIX_HC_64BIT:
1268 {
1269 uint32_t offTrg = *u.pu32++;
1270 Assert(offSrc < pSwitcher->cbCode);
1271 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1272 *uSrc.pu64 = R0PtrCode + offTrg;
1273 break;
1274 }
1275
1276 /*
1277 * 64-bit HC Code Selector (no argument).
1278 */
1279 case FIX_HC_64BIT_CS:
1280 {
1281 Assert(offSrc < pSwitcher->cbCode);
1282#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1283 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1284#else
1285 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1286#endif
1287 break;
1288 }
1289
1290 /*
1291 * 64-bit HC pointer to the CPUM instance data (no argument).
1292 */
1293 case FIX_HC_64BIT_CPUM:
1294 {
1295 Assert(offSrc < pSwitcher->cbCode);
1296 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1297 break;
1298 }
1299#endif
1300
1301 /*
1302 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1303 */
1304 case FIX_ID_32BIT:
1305 {
1306 uint32_t offTrg = *u.pu32++;
1307 Assert(offSrc < pSwitcher->cbCode);
1308 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1309 *uSrc.pu32 = u32IDCode + offTrg;
1310 break;
1311 }
1312
1313 /*
1314 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1315 */
1316 case FIX_ID_64BIT:
1317 {
1318 uint32_t offTrg = *u.pu32++;
1319 Assert(offSrc < pSwitcher->cbCode);
1320 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1321 *uSrc.pu64 = u32IDCode + offTrg;
1322 break;
1323 }
1324
1325 /*
1326 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1327 */
1328 case FIX_ID_FAR32_TO_64BIT_MODE:
1329 {
1330 uint32_t offTrg = *u.pu32++;
1331 Assert(offSrc < pSwitcher->cbCode);
1332 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1333 *uSrc.pu32++ = u32IDCode + offTrg;
1334 *uSrc.pu16 = SelCS64;
1335 AssertRelease(SelCS64);
1336 break;
1337 }
1338
1339#ifdef VBOX_WITH_NMI
1340 /*
1341 * 32-bit address to the APIC base.
1342 */
1343 case FIX_GC_APIC_BASE_32BIT:
1344 {
1345 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1346 break;
1347 }
1348#endif
1349
1350 default:
1351 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1352 break;
1353 }
1354 }
1355
1356#ifdef LOG_ENABLED
1357 /*
1358 * If Log2 is enabled disassemble the switcher code.
1359 *
1360 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1361 */
1362 if (LogIs2Enabled())
1363 {
1364 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1365 " R0PtrCode = %p\n"
1366 " pu8CodeR3 = %p\n"
1367 " GCPtrCode = %VGv\n"
1368 " u32IDCode = %08x\n"
1369 " pVMGC = %VGv\n"
1370 " pCPUMGC = %VGv\n"
1371 " pVMHC = %p\n"
1372 " pCPUMHC = %p\n"
1373 " GCPtrGDT = %VGv\n"
1374 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1375 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1376 " SelCS = %04x\n"
1377 " SelDS = %04x\n"
1378 " SelCS64 = %04x\n"
1379 " SelTSS = %04x\n",
1380 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1381 R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1382 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1383 GCPtrGDT,
1384 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1385 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1386 SelCS, SelDS, SelCS64, SelTSS);
1387
1388 uint32_t offCode = 0;
1389 while (offCode < pSwitcher->cbCode)
1390 {
1391 /*
1392 * Figure out where this is.
1393 */
1394 const char *pszDesc = NULL;
1395 RTUINTPTR uBase;
1396 uint32_t cbCode;
1397 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1398 {
1399 pszDesc = "HCCode0";
1400 uBase = R0PtrCode;
1401 offCode = pSwitcher->offHCCode0;
1402 cbCode = pSwitcher->cbHCCode0;
1403 }
1404 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1405 {
1406 pszDesc = "HCCode1";
1407 uBase = R0PtrCode;
1408 offCode = pSwitcher->offHCCode1;
1409 cbCode = pSwitcher->cbHCCode1;
1410 }
1411 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1412 {
1413 pszDesc = "GCCode";
1414 uBase = GCPtrCode;
1415 offCode = pSwitcher->offGCCode;
1416 cbCode = pSwitcher->cbGCCode;
1417 }
1418 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1419 {
1420 pszDesc = "IDCode0";
1421 uBase = u32IDCode;
1422 offCode = pSwitcher->offIDCode0;
1423 cbCode = pSwitcher->cbIDCode0;
1424 }
1425 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1426 {
1427 pszDesc = "IDCode1";
1428 uBase = u32IDCode;
1429 offCode = pSwitcher->offIDCode1;
1430 cbCode = pSwitcher->cbIDCode1;
1431 }
1432 else
1433 {
1434 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1435 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1436 offCode++;
1437 continue;
1438 }
1439
1440 /*
1441 * Disassemble it.
1442 */
1443 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1444 DISCPUSTATE Cpu;
1445
1446 memset(&Cpu, 0, sizeof(Cpu));
1447 Cpu.mode = CPUMODE_32BIT;
1448 while (cbCode > 0)
1449 {
1450 /* try label it */
1451 if (pSwitcher->offR0HostToGuest == offCode)
1452 RTLogPrintf(" *R0HostToGuest:\n");
1453 if (pSwitcher->offGCGuestToHost == offCode)
1454 RTLogPrintf(" *GCGuestToHost:\n");
1455 if (pSwitcher->offGCCallTrampoline == offCode)
1456 RTLogPrintf(" *GCCallTrampoline:\n");
1457 if (pSwitcher->offGCGuestToHostAsm == offCode)
1458 RTLogPrintf(" *GCGuestToHostAsm:\n");
1459 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1460 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1461 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1462 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1463
1464 /* disas */
1465 uint32_t cbInstr = 0;
1466 char szDisas[256];
1467 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1468 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1469 else
1470 {
1471 RTLogPrintf(" %04x: %02x '%c'\n",
1472 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1473 cbInstr = 1;
1474 }
1475 offCode += cbInstr;
1476 cbCode -= RT_MIN(cbInstr, cbCode);
1477 }
1478 }
1479 }
1480#endif
1481}
1482
1483
1484/**
1485 * Relocator for the 32-Bit to 32-Bit world switcher.
1486 */
1487DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1488{
1489 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1490 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1491}
1492
1493
1494/**
1495 * Relocator for the 32-Bit to PAE world switcher.
1496 */
1497DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1498{
1499 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1500 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1501}
1502
1503
1504/**
1505 * Relocator for the PAE to 32-Bit world switcher.
1506 */
1507DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1508{
1509 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1510 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1511}
1512
1513
1514/**
1515 * Relocator for the PAE to PAE world switcher.
1516 */
1517DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1518{
1519 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1520 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1521}
1522
1523
1524/**
1525 * Relocator for the AMD64 to PAE world switcher.
1526 */
1527DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1528{
1529 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1530 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1531}
1532
1533
1534/**
1535 * Gets the pointer to g_szRTAssertMsg1 in GC.
1536 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1537 * Returns NULL if not present.
1538 * @param pVM The VM handle.
1539 */
1540VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1541{
1542 RTGCPTR32 GCPtr;
1543 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1544 if (VBOX_SUCCESS(rc))
1545 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1546 return NULL;
1547}
1548
1549
1550/**
1551 * Gets the pointer to g_szRTAssertMsg2 in GC.
1552 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1553 * Returns NULL if not present.
1554 * @param pVM The VM handle.
1555 */
1556VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1557{
1558 RTGCPTR32 GCPtr;
1559 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1560 if (VBOX_SUCCESS(rc))
1561 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1562 return NULL;
1563}
1564
1565
1566/**
1567 * Execute state save operation.
1568 *
1569 * @returns VBox status code.
1570 * @param pVM VM Handle.
1571 * @param pSSM SSM operation handle.
1572 */
1573static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1574{
1575 LogFlow(("vmmR3Save:\n"));
1576
1577 /*
1578 * The hypervisor stack.
1579 * Note! See not in vmmR3Load.
1580 */
1581 SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbEMTStackBottomRC);
1582 RTRCPTR RCPtrESP = CPUMGetHyperESP(pVM);
1583 AssertMsg(pVM->vmm.s.pbEMTStackBottomRC - RCPtrESP <= VMM_STACK_SIZE, ("Bottom %RRv ESP=%RRv\n", pVM->vmm.s.pbEMTStackBottomRC, RCPtrESP));
1584 SSMR3PutRCPtr(pSSM, RCPtrESP);
1585 SSMR3PutMem(pSSM, pVM->vmm.s.pbEMTStackR3, VMM_STACK_SIZE);
1586 return SSMR3PutU32(pSSM, ~0); /* terminator */
1587}
1588
1589
1590/**
1591 * Execute state load operation.
1592 *
1593 * @returns VBox status code.
1594 * @param pVM VM Handle.
1595 * @param pSSM SSM operation handle.
1596 * @param u32Version Data layout version.
1597 */
1598static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1599{
1600 LogFlow(("vmmR3Load:\n"));
1601
1602 /*
1603 * Validate version.
1604 */
1605 if (u32Version != VMM_SAVED_STATE_VERSION)
1606 {
1607 AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1608 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1609 }
1610
1611 /*
1612 * Check that the stack is in the same place, or that it's fearly empty.
1613 *
1614 * Note! This can be skipped next time we update saved state as we will
1615 * never be in a R0/RC -> ring-3 call when saving the state. The
1616 * stack and the two associated pointers are not required.
1617 */
1618 RTRCPTR RCPtrStackBottom;
1619 SSMR3GetRCPtr(pSSM, &RCPtrStackBottom);
1620 RTRCPTR RCPtrESP;
1621 int rc = SSMR3GetRCPtr(pSSM, &RCPtrESP);
1622 if (VBOX_FAILURE(rc))
1623 return rc;
1624
1625 /* restore the stack. */
1626 SSMR3GetMem(pSSM, pVM->vmm.s.pbEMTStackR3, VMM_STACK_SIZE);
1627
1628 /* terminator */
1629 uint32_t u32;
1630 rc = SSMR3GetU32(pSSM, &u32);
1631 if (VBOX_FAILURE(rc))
1632 return rc;
1633 if (u32 != ~0U)
1634 {
1635 AssertMsgFailed(("u32=%#x\n", u32));
1636 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1637 }
1638 return VINF_SUCCESS;
1639}
1640
1641
1642/**
1643 * Selects the switcher to be used for switching to GC.
1644 *
1645 * @returns VBox status code.
1646 * @param pVM VM handle.
1647 * @param enmSwitcher The new switcher.
1648 * @remark This function may be called before the VMM is initialized.
1649 */
1650VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1651{
1652 /*
1653 * Validate input.
1654 */
1655 if ( enmSwitcher < VMMSWITCHER_INVALID
1656 || enmSwitcher >= VMMSWITCHER_MAX)
1657 {
1658 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1659 return VERR_INVALID_PARAMETER;
1660 }
1661
1662 /* Do nothing if the switcher is disabled. */
1663 if (pVM->vmm.s.fSwitcherDisabled)
1664 return VINF_SUCCESS;
1665
1666 /*
1667 * Select the new switcher.
1668 */
1669 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1670 if (pSwitcher)
1671 {
1672 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1673 pVM->vmm.s.enmSwitcher = enmSwitcher;
1674
1675 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1676 pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
1677
1678 RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1679 pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
1680 pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
1681 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1682 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1683 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1684 return VINF_SUCCESS;
1685 }
1686 return VERR_NOT_IMPLEMENTED;
1687}
1688
1689/**
1690 * Disable the switcher logic permanently.
1691 *
1692 * @returns VBox status code.
1693 * @param pVM VM handle.
1694 */
1695VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1696{
1697/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1698 * @code
1699 * mov eax, VERR_INTERNAL_ERROR
1700 * ret
1701 * @endcode
1702 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1703 */
1704 pVM->vmm.s.fSwitcherDisabled = true;
1705 return VINF_SUCCESS;
1706}
1707
1708
1709/**
1710 * Resolve a builtin RC symbol.
1711 *
1712 * Called by PDM when loading or relocating RC modules.
1713 *
1714 * @returns VBox status
1715 * @param pVM VM Handle.
1716 * @param pszSymbol Symbol to resolv
1717 * @param pRCPtrValue Where to store the symbol value.
1718 *
1719 * @remark This has to work before VMMR3Relocate() is called.
1720 */
1721VMMR3DECL(int) VMMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
1722{
1723 if (!strcmp(pszSymbol, "g_Logger"))
1724 {
1725 if (pVM->vmm.s.pRCLoggerR3)
1726 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
1727 *pRCPtrValue = pVM->vmm.s.pRCLoggerRC;
1728 }
1729 else if (!strcmp(pszSymbol, "g_RelLogger"))
1730 {
1731#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1732 if (pVM->vmm.s.pRCRelLoggerR3)
1733 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
1734 *pRCPtrValue = pVM->vmm.s.pRCRelLoggerRC;
1735#else
1736 *pRCPtrValue = NIL_RTRCPTR;
1737#endif
1738 }
1739 else
1740 return VERR_SYMBOL_NOT_FOUND;
1741 return VINF_SUCCESS;
1742}
1743
1744
1745/**
1746 * Suspends the the CPU yielder.
1747 *
1748 * @param pVM The VM handle.
1749 */
1750VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1751{
1752 if (!pVM->vmm.s.cYieldResumeMillies)
1753 {
1754 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1755 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1756 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1757 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1758 else
1759 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1760 TMTimerStop(pVM->vmm.s.pYieldTimer);
1761 }
1762 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1763}
1764
1765
1766/**
1767 * Stops the the CPU yielder.
1768 *
1769 * @param pVM The VM handle.
1770 */
1771VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1772{
1773 if (!pVM->vmm.s.cYieldResumeMillies)
1774 TMTimerStop(pVM->vmm.s.pYieldTimer);
1775 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1776 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1777}
1778
1779
1780/**
1781 * Resumes the CPU yielder when it has been a suspended or stopped.
1782 *
1783 * @param pVM The VM handle.
1784 */
1785VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1786{
1787 if (pVM->vmm.s.cYieldResumeMillies)
1788 {
1789 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1790 pVM->vmm.s.cYieldResumeMillies = 0;
1791 }
1792}
1793
1794
1795/**
1796 * Internal timer callback function.
1797 *
1798 * @param pVM The VM.
1799 * @param pTimer The timer handle.
1800 * @param pvUser User argument specified upon timer creation.
1801 */
1802static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1803{
1804 /*
1805 * This really needs some careful tuning. While we shouldn't be too gready since
1806 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1807 * because that'll cause us to stop up.
1808 *
1809 * The current logic is to use the default interval when there is no lag worth
1810 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1811 *
1812 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1813 * so the lag is up to date.)
1814 */
1815 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1816 if ( u64Lag < 50000000 /* 50ms */
1817 || ( u64Lag < 1000000000 /* 1s */
1818 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1819 )
1820 {
1821 uint64_t u64Elapsed = RTTimeNanoTS();
1822 pVM->vmm.s.u64LastYield = u64Elapsed;
1823
1824 RTThreadYield();
1825
1826#ifdef LOG_ENABLED
1827 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1828 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1829#endif
1830 }
1831 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1832}
1833
1834
1835/**
1836 * Acquire global VM lock.
1837 *
1838 * @returns VBox status code
1839 * @param pVM The VM to operate on.
1840 *
1841 * @remarks The global VMM lock isn't really used for anything any longer.
1842 */
1843VMMR3DECL(int) VMMR3Lock(PVM pVM)
1844{
1845 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1846}
1847
1848
1849/**
1850 * Release global VM lock.
1851 *
1852 * @returns VBox status code
1853 * @param pVM The VM to operate on.
1854 *
1855 * @remarks The global VMM lock isn't really used for anything any longer.
1856 */
1857VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1858{
1859 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1860}
1861
1862
1863/**
1864 * Return global VM lock owner.
1865 *
1866 * @returns Thread id of owner.
1867 * @returns NIL_RTTHREAD if no owner.
1868 * @param pVM The VM to operate on.
1869 *
1870 * @remarks The global VMM lock isn't really used for anything any longer.
1871 */
1872VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1873{
1874 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1875}
1876
1877
1878/**
1879 * Checks if the current thread is the owner of the global VM lock.
1880 *
1881 * @returns true if owner.
1882 * @returns false if not owner.
1883 * @param pVM The VM to operate on.
1884 *
1885 * @remarks The global VMM lock isn't really used for anything any longer.
1886 */
1887VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1888{
1889 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1890}
1891
1892
1893/**
1894 * Executes guest code in the raw-mode context.
1895 *
1896 * @param pVM VM handle.
1897 */
1898VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1899{
1900 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1901
1902 /*
1903 * Set the EIP and ESP.
1904 */
1905 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1906 ? pVM->vmm.s.pfnCPUMRCResumeGuestV86
1907 : pVM->vmm.s.pfnCPUMRCResumeGuest);
1908 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC);
1909
1910 /*
1911 * We hide log flushes (outer) and hypervisor interrupts (inner).
1912 */
1913 for (;;)
1914 {
1915 int rc;
1916 do
1917 {
1918#ifdef NO_SUPCALLR0VMM
1919 rc = VERR_GENERAL_FAILURE;
1920#else
1921 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1922 if (RT_LIKELY(rc == VINF_SUCCESS))
1923 rc = pVM->vmm.s.iLastGZRc;
1924#endif
1925 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1926
1927 /*
1928 * Flush the logs.
1929 */
1930#ifdef LOG_ENABLED
1931 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
1932 if ( pLogger
1933 && pLogger->offScratch > 0)
1934 RTLogFlushRC(NULL, pLogger);
1935#endif
1936#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1937 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
1938 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1939 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
1940#endif
1941 if (rc != VINF_VMM_CALL_HOST)
1942 {
1943 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1944 return rc;
1945 }
1946 rc = vmmR3ServiceCallHostRequest(pVM);
1947 if (VBOX_FAILURE(rc))
1948 return rc;
1949 /* Resume GC */
1950 }
1951}
1952
1953
1954/**
1955 * Executes guest code (Intel VT-x and AMD-V).
1956 *
1957 * @param pVM VM handle.
1958 */
1959VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1960{
1961 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1962
1963 for (;;)
1964 {
1965 int rc;
1966 do
1967 {
1968#ifdef NO_SUPCALLR0VMM
1969 rc = VERR_GENERAL_FAILURE;
1970#else
1971 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
1972 if (RT_LIKELY(rc == VINF_SUCCESS))
1973 rc = pVM->vmm.s.iLastGZRc;
1974#endif
1975 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1976
1977#ifdef LOG_ENABLED
1978 /*
1979 * Flush the log
1980 */
1981 PVMMR0LOGGER pR0LoggerR3 = pVM->vmm.s.pR0LoggerR3;
1982 if ( pR0LoggerR3
1983 && pR0LoggerR3->Logger.offScratch > 0)
1984 RTLogFlushToLogger(&pR0LoggerR3->Logger, NULL);
1985#endif /* !LOG_ENABLED */
1986 if (rc != VINF_VMM_CALL_HOST)
1987 {
1988 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1989 return rc;
1990 }
1991 rc = vmmR3ServiceCallHostRequest(pVM);
1992 if (VBOX_FAILURE(rc))
1993 return rc;
1994 /* Resume R0 */
1995 }
1996}
1997
1998/**
1999 * Calls GC a function.
2000 *
2001 * @param pVM The VM handle.
2002 * @param GCPtrEntry The GC function address.
2003 * @param cArgs The number of arguments in the ....
2004 * @param ... Arguments to the function.
2005 */
2006VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
2007{
2008 va_list args;
2009 va_start(args, cArgs);
2010 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2011 va_end(args);
2012 return rc;
2013}
2014
2015
2016/**
2017 * Calls GC a function.
2018 *
2019 * @param pVM The VM handle.
2020 * @param GCPtrEntry The GC function address.
2021 * @param cArgs The number of arguments in the ....
2022 * @param args Arguments to the function.
2023 */
2024VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
2025{
2026 Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
2027
2028 /*
2029 * Setup the call frame using the trampoline.
2030 */
2031 CPUMHyperSetCtxCore(pVM, NULL);
2032 memset(pVM->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2033 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC - cArgs * sizeof(RTGCUINTPTR32));
2034 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE) - cArgs;
2035 int i = cArgs;
2036 while (i-- > 0)
2037 *pFrame++ = va_arg(args, RTGCUINTPTR32);
2038
2039 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2040 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2041 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnCallTrampolineRC);
2042
2043 /*
2044 * We hide log flushes (outer) and hypervisor interrupts (inner).
2045 */
2046 for (;;)
2047 {
2048 int rc;
2049 do
2050 {
2051#ifdef NO_SUPCALLR0VMM
2052 rc = VERR_GENERAL_FAILURE;
2053#else
2054 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2055 if (RT_LIKELY(rc == VINF_SUCCESS))
2056 rc = pVM->vmm.s.iLastGZRc;
2057#endif
2058 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2059
2060 /*
2061 * Flush the logs.
2062 */
2063#ifdef LOG_ENABLED
2064 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2065 if ( pLogger
2066 && pLogger->offScratch > 0)
2067 RTLogFlushRC(NULL, pLogger);
2068#endif
2069#ifdef VBOX_WITH_RC_RELEASE_LOGGING
2070 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2071 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2072 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2073#endif
2074 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2075 VMMR3FatalDump(pVM, rc);
2076 if (rc != VINF_VMM_CALL_HOST)
2077 {
2078 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2079 return rc;
2080 }
2081 rc = vmmR3ServiceCallHostRequest(pVM);
2082 if (VBOX_FAILURE(rc))
2083 return rc;
2084 }
2085}
2086
2087
2088/**
2089 * Resumes executing hypervisor code when interrupted by a queue flush or a
2090 * debug event.
2091 *
2092 * @returns VBox status code.
2093 * @param pVM VM handle.
2094 */
2095VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2096{
2097 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2098
2099 /*
2100 * We hide log flushes (outer) and hypervisor interrupts (inner).
2101 */
2102 for (;;)
2103 {
2104 int rc;
2105 do
2106 {
2107#ifdef NO_SUPCALLR0VMM
2108 rc = VERR_GENERAL_FAILURE;
2109#else
2110 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2111 if (RT_LIKELY(rc == VINF_SUCCESS))
2112 rc = pVM->vmm.s.iLastGZRc;
2113#endif
2114 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2115
2116 /*
2117 * Flush the loggers,
2118 */
2119#ifdef LOG_ENABLED
2120 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2121 if ( pLogger
2122 && pLogger->offScratch > 0)
2123 RTLogFlushRC(NULL, pLogger);
2124#endif
2125#ifdef VBOX_WITH_RC_RELEASE_LOGGING
2126 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2127 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2128 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2129#endif
2130 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2131 VMMR3FatalDump(pVM, rc);
2132 if (rc != VINF_VMM_CALL_HOST)
2133 {
2134 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2135 return rc;
2136 }
2137 rc = vmmR3ServiceCallHostRequest(pVM);
2138 if (VBOX_FAILURE(rc))
2139 return rc;
2140 }
2141}
2142
2143
2144/**
2145 * Service a call to the ring-3 host code.
2146 *
2147 * @returns VBox status code.
2148 * @param pVM VM handle.
2149 * @remark Careful with critsects.
2150 */
2151static int vmmR3ServiceCallHostRequest(PVM pVM)
2152{
2153 switch (pVM->vmm.s.enmCallHostOperation)
2154 {
2155 /*
2156 * Acquire the PDM lock.
2157 */
2158 case VMMCALLHOST_PDM_LOCK:
2159 {
2160 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2161 break;
2162 }
2163
2164 /*
2165 * Flush a PDM queue.
2166 */
2167 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2168 {
2169 PDMR3QueueFlushWorker(pVM, NULL);
2170 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2171 break;
2172 }
2173
2174 /*
2175 * Grow the PGM pool.
2176 */
2177 case VMMCALLHOST_PGM_POOL_GROW:
2178 {
2179 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2180 break;
2181 }
2182
2183 /*
2184 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2185 */
2186 case VMMCALLHOST_PGM_MAP_CHUNK:
2187 {
2188 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2189 break;
2190 }
2191
2192 /*
2193 * Allocates more handy pages.
2194 */
2195 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2196 {
2197 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2198 break;
2199 }
2200#ifndef VBOX_WITH_NEW_PHYS_CODE
2201
2202 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2203 {
2204 const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2205 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2206 break;
2207 }
2208#endif
2209
2210 /*
2211 * Acquire the PGM lock.
2212 */
2213 case VMMCALLHOST_PGM_LOCK:
2214 {
2215 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2216 break;
2217 }
2218
2219 /*
2220 * Flush REM handler notifications.
2221 */
2222 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2223 {
2224 REMR3ReplayHandlerNotifications(pVM);
2225 break;
2226 }
2227
2228 /*
2229 * This is a noop. We just take this route to avoid unnecessary
2230 * tests in the loops.
2231 */
2232 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2233 break;
2234
2235 /*
2236 * Set the VM error message.
2237 */
2238 case VMMCALLHOST_VM_SET_ERROR:
2239 VMR3SetErrorWorker(pVM);
2240 break;
2241
2242 /*
2243 * Set the VM runtime error message.
2244 */
2245 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2246 VMR3SetRuntimeErrorWorker(pVM);
2247 break;
2248
2249 /*
2250 * Signal a ring 0 hypervisor assertion.
2251 * Cancel the longjmp operation that's in progress.
2252 */
2253 case VMMCALLHOST_VM_R0_ASSERTION:
2254 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2255 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2256#ifdef RT_ARCH_X86
2257 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2258#else
2259 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2260#endif
2261 LogRel((pVM->vmm.s.szRing0AssertMsg1));
2262 LogRel((pVM->vmm.s.szRing0AssertMsg2));
2263 return VERR_VMM_RING0_ASSERTION;
2264
2265 default:
2266 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2267 return VERR_INTERNAL_ERROR;
2268 }
2269
2270 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2271 return VINF_SUCCESS;
2272}
2273
2274
2275/**
2276 * Displays the Force action Flags.
2277 *
2278 * @param pVM The VM handle.
2279 * @param pHlp The output helpers.
2280 * @param pszArgs The additional arguments (ignored).
2281 */
2282static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2283{
2284 const uint32_t fForcedActions = pVM->fForcedActions;
2285
2286 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2287
2288 /* show the flag mnemonics */
2289 int c = 0;
2290 uint32_t f = fForcedActions;
2291#define PRINT_FLAG(flag) do { \
2292 if (f & (flag)) \
2293 { \
2294 static const char *s_psz = #flag; \
2295 if (!(c % 6)) \
2296 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2297 else \
2298 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2299 c++; \
2300 f &= ~(flag); \
2301 } \
2302 } while (0)
2303 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2304 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2305 PRINT_FLAG(VM_FF_TIMER);
2306 PRINT_FLAG(VM_FF_PDM_QUEUES);
2307 PRINT_FLAG(VM_FF_PDM_DMA);
2308 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2309 PRINT_FLAG(VM_FF_DBGF);
2310 PRINT_FLAG(VM_FF_REQUEST);
2311 PRINT_FLAG(VM_FF_TERMINATE);
2312 PRINT_FLAG(VM_FF_RESET);
2313 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2314 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2315 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2316 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2317 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2318 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2319 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2320 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2321 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2322 PRINT_FLAG(VM_FF_TO_R3);
2323 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2324 if (f)
2325 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2326 else
2327 pHlp->pfnPrintf(pHlp, "\n");
2328#undef PRINT_FLAG
2329
2330 /* the groups */
2331 c = 0;
2332#define PRINT_GROUP(grp) do { \
2333 if (fForcedActions & (grp)) \
2334 { \
2335 static const char *s_psz = #grp; \
2336 if (!(c % 5)) \
2337 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2338 else \
2339 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2340 c++; \
2341 } \
2342 } while (0)
2343 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2344 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2345 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2346 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2347 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2348 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2349 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2350 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2351 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2352 if (c)
2353 pHlp->pfnPrintf(pHlp, "\n");
2354#undef PRINT_GROUP
2355}
2356
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use