VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 35263

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1/* $Id: HWACCMInternal.h 34184 2010-11-18 21:19:11Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HWACCMInternal_h
19#define ___HWACCMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/em.h>
24#include <VBox/stam.h>
25#include <VBox/dis.h>
26#include <VBox/hwaccm.h>
27#include <VBox/hwacc_vmx.h>
28#include <VBox/pgm.h>
29#include <VBox/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34
35#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
36/* Enable 64 bits guest support. */
37# define VBOX_ENABLE_64_BITS_GUESTS
38#endif
39
40#define VMX_USE_CACHED_VMCS_ACCESSES
41#define HWACCM_VMX_EMULATE_REALMODE
42#define HWACCM_VTX_WITH_EPT
43#define HWACCM_VTX_WITH_VPID
44
45
46#if 0
47/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
48 * for some strange reason the CPU doesn't save the MSRs during the VM-exit.
49 * Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
50 *
51 * Note: change the assembly files when enabling this! (remove the manual auto load/save)
52 */
53#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
54#endif
55
56RT_C_DECLS_BEGIN
57
58
59/** @defgroup grp_hwaccm_int Internal
60 * @ingroup grp_hwaccm
61 * @internal
62 * @{
63 */
64
65
66/** Maximum number of exit reason statistics counters. */
67#define MAX_EXITREASON_STAT 0x100
68#define MASK_EXITREASON_STAT 0xff
69#define MASK_INJECT_IRQ_STAT 0xff
70
71/** @name Changed flags
72 * These flags are used to keep track of which important registers that
73 * have been changed since last they were reset.
74 * @{
75 */
76#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
77#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
78#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
79#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
80#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
81#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
82#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
83#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
84#define HWACCM_CHANGED_GUEST_MSR RT_BIT(8)
85#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
86#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
87#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
88
89#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
90 | HWACCM_CHANGED_GUEST_CR0 \
91 | HWACCM_CHANGED_GUEST_CR3 \
92 | HWACCM_CHANGED_GUEST_CR4 \
93 | HWACCM_CHANGED_GUEST_GDTR \
94 | HWACCM_CHANGED_GUEST_IDTR \
95 | HWACCM_CHANGED_GUEST_LDTR \
96 | HWACCM_CHANGED_GUEST_TR \
97 | HWACCM_CHANGED_GUEST_MSR \
98 | HWACCM_CHANGED_GUEST_FPU \
99 | HWACCM_CHANGED_GUEST_DEBUG \
100 | HWACCM_CHANGED_HOST_CONTEXT)
101
102#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
103 | HWACCM_CHANGED_GUEST_CR0 \
104 | HWACCM_CHANGED_GUEST_CR3 \
105 | HWACCM_CHANGED_GUEST_CR4 \
106 | HWACCM_CHANGED_GUEST_GDTR \
107 | HWACCM_CHANGED_GUEST_IDTR \
108 | HWACCM_CHANGED_GUEST_LDTR \
109 | HWACCM_CHANGED_GUEST_TR \
110 | HWACCM_CHANGED_GUEST_MSR \
111 | HWACCM_CHANGED_GUEST_DEBUG \
112 | HWACCM_CHANGED_GUEST_FPU)
113
114/** @} */
115
116/** @name Intercepted traps
117 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
118 * Currently #NM and #PF only
119 */
120#ifdef VBOX_STRICT
121#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
122#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
123#else
124#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
125#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
126#endif
127/* All exceptions have to be intercept in emulated real-mode (minus NM & PF as they are always intercepted. */
128#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NMI) | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_DF) | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF) | RT_BIT(X86_XCPT_AC) | RT_BIT(X86_XCPT_MC) | RT_BIT(X86_XCPT_XF)
129/** @} */
130
131
132/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
133#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
134
135/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
136#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
137/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
138#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
139/** Total guest mapped memory needed. */
140#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
141
142/* Enable for TPR guest patching. */
143#define VBOX_HWACCM_WITH_GUEST_PATCHING
144
145/** HWACCM SSM version
146 */
147#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
148#define HWACCM_SSM_VERSION 5
149#define HWACCM_SSM_VERSION_NO_PATCHING 4
150#else
151#define HWACCM_SSM_VERSION 4
152#define HWACCM_SSM_VERSION_NO_PATCHING 4
153#endif
154#define HWACCM_SSM_VERSION_2_0_X 3
155
156/* Per-cpu information. (host) */
157typedef struct
158{
159 RTCPUID idCpu;
160
161 RTR0MEMOBJ pMemObj;
162 /* Current ASID (AMD-V)/VPID (Intel) */
163 uint32_t uCurrentASID;
164 /* TLB flush count */
165 uint32_t cTLBFlushes;
166
167 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
168 bool fFlushTLB;
169
170 /** Configured for VT-x or AMD-V. */
171 bool fConfigured;
172
173 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
174 bool fIgnoreAMDVInUseError;
175
176 /** In use by our code. (for power suspend) */
177 volatile bool fInUse;
178} HWACCM_CPUINFO;
179typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181typedef enum
182{
183 HWACCMPENDINGIO_INVALID = 0,
184 HWACCMPENDINGIO_PORT_READ,
185 HWACCMPENDINGIO_PORT_WRITE,
186 HWACCMPENDINGIO_STRING_READ,
187 HWACCMPENDINGIO_STRING_WRITE,
188 /** The usual 32-bit paranoia. */
189 HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190} HWACCMPENDINGIO;
191
192
193typedef enum
194{
195 HWACCMTPRINSTR_INVALID,
196 HWACCMTPRINSTR_READ,
197 HWACCMTPRINSTR_READ_SHR4,
198 HWACCMTPRINSTR_WRITE_REG,
199 HWACCMTPRINSTR_WRITE_IMM,
200 HWACCMTPRINSTR_JUMP_REPLACEMENT,
201 /** The usual 32-bit paranoia. */
202 HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203} HWACCMTPRINSTR;
204
205typedef struct
206{
207 /** The key is the address of patched instruction. (32 bits GC ptr) */
208 AVLOU32NODECORE Core;
209 /** Original opcode. */
210 uint8_t aOpcode[16];
211 /** Instruction size. */
212 uint32_t cbOp;
213 /** Replacement opcode. */
214 uint8_t aNewOpcode[16];
215 /** Replacement instruction size. */
216 uint32_t cbNewOp;
217 /** Instruction type. */
218 HWACCMTPRINSTR enmType;
219 /** Source operand. */
220 uint32_t uSrcOperand;
221 /** Destination operand. */
222 uint32_t uDstOperand;
223 /** Number of times the instruction caused a fault. */
224 uint32_t cFaults;
225 /** Patch address of the jump replacement. */
226 RTGCPTR32 pJumpTarget;
227} HWACCMTPRPATCH;
228/** Pointer to HWACCMTPRPATCH. */
229typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231/**
232 * Switcher function, HC to RC.
233 *
234 * @param pVM The VM handle.
235 * @param uOffsetVMCPU VMCPU offset from pVM
236 * @returns Return code indicating the action to take.
237 */
238typedef DECLCALLBACK (int) FNHWACCMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
239/** Pointer to switcher function. */
240typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
241
242/**
243 * HWACCM VM Instance data.
244 * Changes to this must checked against the padding of the cfgm union in VM!
245 */
246typedef struct HWACCM
247{
248 /** Set when we've initialized VMX or SVM. */
249 bool fInitialized;
250
251 /** Set when hardware acceleration is allowed. */
252 bool fAllowed;
253
254 /** Set if nested paging is enabled. */
255 bool fNestedPaging;
256
257 /** Set if nested paging is allowed. */
258 bool fAllowNestedPaging;
259
260 /** Set if large pages are enabled (requires nested paging). */
261 bool fLargePages;
262
263 /** Set if we can support 64-bit guests or not. */
264 bool fAllow64BitGuests;
265
266 /** Set if an IO-APIC is configured for this VM. */
267 bool fHasIoApic;
268
269 /** Set when TPR patching is allowed. */
270 bool fTRPPatchingAllowed;
271
272 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
273 bool fGlobalInit;
274
275 /** Set when TPR patching is active. */
276 bool fTPRPatchingActive;
277 bool u8Alignment[6];
278
279 /** And mask for copying register contents. */
280 uint64_t u64RegisterMask;
281
282 /** Maximum ASID allowed. */
283 RTUINT uMaxASID;
284
285 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
286 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
287 uint32_t cMaxResumeLoops;
288
289 /** Guest allocated memory for patching purposes. */
290 RTGCPTR pGuestPatchMem;
291 /** Current free pointer inside the patch block. */
292 RTGCPTR pFreeGuestPatchMem;
293 /** Size of the guest patch memory block. */
294 uint32_t cbGuestPatchMem;
295 uint32_t uPadding1;
296
297#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
298 /** 32 to 64 bits switcher entrypoint. */
299 R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
300
301 /* AMD-V 64 bits vmrun handler */
302 RTRCPTR pfnSVMGCVMRun64;
303
304 /* VT-x 64 bits vmlaunch handler */
305 RTRCPTR pfnVMXGCStartVM64;
306
307 /* RC handler to setup the 64 bits FPU state. */
308 RTRCPTR pfnSaveGuestFPU64;
309
310 /* RC handler to setup the 64 bits debug state. */
311 RTRCPTR pfnSaveGuestDebug64;
312
313 /* Test handler */
314 RTRCPTR pfnTest64;
315
316 RTRCPTR uAlignment[2];
317/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
318 uint32_t u32Alignment[1]; */
319#endif
320
321 struct
322 {
323 /** Set by the ring-0 side of HWACCM to indicate VMX is supported by the
324 * CPU. */
325 bool fSupported;
326
327 /** Set when we've enabled VMX. */
328 bool fEnabled;
329
330 /** Set if VPID is supported. */
331 bool fVPID;
332
333 /** Set if VT-x VPID is allowed. */
334 bool fAllowVPID;
335
336 /** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
337 bool fUnrestrictedGuest;
338
339 /** Whether we're using the preemption timer or not. */
340 bool fUsePreemptTimer;
341 /** The shift mask employed by the VMX-Preemption timer. */
342 uint8_t cPreemptTimerShift;
343
344 bool uAlignment[1];
345
346 /** Virtual address of the TSS page used for real mode emulation. */
347 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
348
349 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
350 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
351
352 /** R0 memory object for the APIC physical page (serves for filtering accesses). */
353 RTR0MEMOBJ pMemObjAPIC;
354 /** Physical address of the APIC physical page (serves for filtering accesses). */
355 RTHCPHYS pAPICPhys;
356 /** Virtual address of the APIC physical page (serves for filtering accesses). */
357 R0PTRTYPE(uint8_t *) pAPIC;
358
359 /** R0 memory object for the MSR entry load page (guest MSRs). */
360 RTR0MEMOBJ pMemObjMSREntryLoad;
361 /** Physical address of the MSR entry load page (guest MSRs). */
362 RTHCPHYS pMSREntryLoadPhys;
363 /** Virtual address of the MSR entry load page (guest MSRs). */
364 R0PTRTYPE(uint8_t *) pMSREntryLoad;
365
366#ifdef VBOX_WITH_CRASHDUMP_MAGIC
367 RTR0MEMOBJ pMemObjScratch;
368 RTHCPHYS pScratchPhys;
369 R0PTRTYPE(uint8_t *) pScratch;
370#endif
371 /** R0 memory object for the MSR exit store page (guest MSRs). */
372 RTR0MEMOBJ pMemObjMSRExitStore;
373 /** Physical address of the MSR exit store page (guest MSRs). */
374 RTHCPHYS pMSRExitStorePhys;
375 /** Virtual address of the MSR exit store page (guest MSRs). */
376 R0PTRTYPE(uint8_t *) pMSRExitStore;
377
378 /** R0 memory object for the MSR exit load page (host MSRs). */
379 RTR0MEMOBJ pMemObjMSRExitLoad;
380 /** Physical address of the MSR exit load page (host MSRs). */
381 RTHCPHYS pMSRExitLoadPhys;
382 /** Virtual address of the MSR exit load page (host MSRs). */
383 R0PTRTYPE(uint8_t *) pMSRExitLoad;
384
385 /** Ring 0 handlers for VT-x. */
386 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
387
388#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
389 uint32_t u32Alignment;
390#endif
391 /** Host CR4 value (set by ring-0 VMX init) */
392 uint64_t hostCR4;
393
394 /** Host EFER value (set by ring-0 VMX init) */
395 uint64_t hostEFER;
396
397 /** VMX MSR values */
398 struct
399 {
400 uint64_t feature_ctrl;
401 uint64_t vmx_basic_info;
402 VMX_CAPABILITY vmx_pin_ctls;
403 VMX_CAPABILITY vmx_proc_ctls;
404 VMX_CAPABILITY vmx_proc_ctls2;
405 VMX_CAPABILITY vmx_exit;
406 VMX_CAPABILITY vmx_entry;
407 uint64_t vmx_misc;
408 uint64_t vmx_cr0_fixed0;
409 uint64_t vmx_cr0_fixed1;
410 uint64_t vmx_cr4_fixed0;
411 uint64_t vmx_cr4_fixed1;
412 uint64_t vmx_vmcs_enum;
413 uint64_t vmx_eptcaps;
414 } msr;
415
416 /** Flush types for invept & invvpid; they depend on capabilities. */
417 VMX_FLUSH enmFlushPage;
418 VMX_FLUSH enmFlushContext;
419 } vmx;
420
421 struct
422 {
423 /** Set by the ring-0 side of HWACCM to indicate SVM is supported by the
424 * CPU. */
425 bool fSupported;
426 /** Set when we've enabled SVM. */
427 bool fEnabled;
428 /** Set if erratum 170 affects the AMD cpu. */
429 bool fAlwaysFlushTLB;
430 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
431 bool fIgnoreInUseError;
432
433 /** R0 memory object for the IO bitmap (12kb). */
434 RTR0MEMOBJ pMemObjIOBitmap;
435 /** Physical address of the IO bitmap (12kb). */
436 RTHCPHYS pIOBitmapPhys;
437 /** Virtual address of the IO bitmap. */
438 R0PTRTYPE(void *) pIOBitmap;
439
440 /* HWCR msr (for diagnostics) */
441 uint64_t msrHWCR;
442
443 /** SVM revision. */
444 uint32_t u32Rev;
445
446 /** SVM feature bits from cpuid 0x8000000a */
447 uint32_t u32Features;
448 } svm;
449
450 /**
451 * AVL tree with all patches (active or disabled) sorted by guest instruction address
452 */
453 AVLOU32TREE PatchTree;
454 uint32_t cPatches;
455 HWACCMTPRPATCH aPatches[64];
456
457 struct
458 {
459 uint32_t u32AMDFeatureECX;
460 uint32_t u32AMDFeatureEDX;
461 } cpuid;
462
463 /** Saved error from detection */
464 int32_t lLastError;
465
466 /** HWACCMR0Init was run */
467 bool fHWACCMR0Init;
468 bool u8Alignment1[7];
469
470 STAMCOUNTER StatTPRPatchSuccess;
471 STAMCOUNTER StatTPRPatchFailure;
472 STAMCOUNTER StatTPRReplaceSuccess;
473 STAMCOUNTER StatTPRReplaceFailure;
474} HWACCM;
475/** Pointer to HWACCM VM instance data. */
476typedef HWACCM *PHWACCM;
477
478/* Maximum number of cached entries. */
479#define VMCSCACHE_MAX_ENTRY 128
480
481/* Structure for storing read and write VMCS actions. */
482typedef struct VMCSCACHE
483{
484#ifdef VBOX_WITH_CRASHDUMP_MAGIC
485 /* Magic marker for searching in crash dumps. */
486 uint8_t aMagic[16];
487 uint64_t uMagic;
488 uint64_t u64TimeEntry;
489 uint64_t u64TimeSwitch;
490 uint64_t cResume;
491 uint64_t interPD;
492 uint64_t pSwitcher;
493 uint32_t uPos;
494 uint32_t idCpu;
495#endif
496 /* CR2 is saved here for EPT syncing. */
497 uint64_t cr2;
498 struct
499 {
500 uint32_t cValidEntries;
501 uint32_t uAlignment;
502 uint32_t aField[VMCSCACHE_MAX_ENTRY];
503 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
504 } Write;
505 struct
506 {
507 uint32_t cValidEntries;
508 uint32_t uAlignment;
509 uint32_t aField[VMCSCACHE_MAX_ENTRY];
510 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
511 } Read;
512#ifdef DEBUG
513 struct
514 {
515 RTHCPHYS pPageCpuPhys;
516 RTHCPHYS pVMCSPhys;
517 RTGCPTR pCache;
518 RTGCPTR pCtx;
519 } TestIn;
520 struct
521 {
522 RTHCPHYS pVMCSPhys;
523 RTGCPTR pCache;
524 RTGCPTR pCtx;
525 uint64_t eflags;
526 uint64_t cr8;
527 } TestOut;
528 struct
529 {
530 uint64_t param1;
531 uint64_t param2;
532 uint64_t param3;
533 uint64_t param4;
534 } ScratchPad;
535#endif
536} VMCSCACHE;
537/** Pointer to VMCSCACHE. */
538typedef VMCSCACHE *PVMCSCACHE;
539
540/** VMX StartVM function. */
541typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
542/** Pointer to a VMX StartVM function. */
543typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
544
545/** SVM VMRun function. */
546typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
547/** Pointer to a SVM VMRun function. */
548typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
549
550/**
551 * HWACCM VMCPU Instance data.
552 */
553typedef struct HWACCMCPU
554{
555 /** Old style FPU reporting trap mask override performed (optimization) */
556 bool fFPUOldStyleOverride;
557
558 /** Set if we don't have to flush the TLB on VM entry. */
559 bool fResumeVM;
560
561 /** Set if we need to flush the TLB during the world switch. */
562 bool fForceTLBFlush;
563
564 /** Set when we're using VT-x or AMD-V at that moment. */
565 bool fActive;
566
567 /** Set when the TLB has been checked until we return from the world switch. */
568 volatile uint8_t fCheckedTLBFlush;
569 uint8_t bAlignment[3];
570
571 /** HWACCM_CHANGED_* flags. */
572 RTUINT fContextUseFlags;
573
574 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
575 RTCPUID idLastCpu;
576
577 /** TLB flush count */
578 RTUINT cTLBFlushes;
579
580 /** Current ASID in use by the VM */
581 RTUINT uCurrentASID;
582
583 /** World switch exit counter. */
584 volatile uint32_t cWorldSwitchExit;
585 uint32_t u32Alignment;
586
587 struct
588 {
589 /** Physical address of the VM control structure (VMCS). */
590 RTHCPHYS pVMCSPhys;
591 /** R0 memory object for the VM control structure (VMCS). */
592 RTR0MEMOBJ pMemObjVMCS;
593 /** Virtual address of the VM control structure (VMCS). */
594 R0PTRTYPE(void *) pVMCS;
595
596 /** Ring 0 handlers for VT-x. */
597 PFNHWACCMVMXSTARTVM pfnStartVM;
598
599#if HC_ARCH_BITS == 32
600 uint32_t u32Alignment;
601#endif
602
603 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
604 uint64_t proc_ctls;
605
606 /** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
607 uint64_t proc_ctls2;
608
609 /** Physical address of the virtual APIC page for TPR caching. */
610 RTHCPHYS pVAPICPhys;
611 /** R0 memory object for the virtual APIC page for TPR caching. */
612 RTR0MEMOBJ pMemObjVAPIC;
613 /** Virtual address of the virtual APIC page for TPR caching. */
614 R0PTRTYPE(uint8_t *) pVAPIC;
615
616 /** Current CR0 mask. */
617 uint64_t cr0_mask;
618 /** Current CR4 mask. */
619 uint64_t cr4_mask;
620
621 /** Current EPTP. */
622 RTHCPHYS GCPhysEPTP;
623
624 /** Physical address of the MSR bitmap (1 page). */
625 RTHCPHYS pMSRBitmapPhys;
626 /** R0 memory object for the MSR bitmap (1 page). */
627 RTR0MEMOBJ pMemObjMSRBitmap;
628 /** Virtual address of the MSR bitmap (1 page). */
629 R0PTRTYPE(uint8_t *) pMSRBitmap;
630
631#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
632 /** Physical address of the guest MSR load area (1 page). */
633 RTHCPHYS pGuestMSRPhys;
634 /** R0 memory object for the guest MSR load area (1 page). */
635 RTR0MEMOBJ pMemObjGuestMSR;
636 /** Virtual address of the guest MSR load area (1 page). */
637 R0PTRTYPE(uint8_t *) pGuestMSR;
638
639 /** Physical address of the MSR load area (1 page). */
640 RTHCPHYS pHostMSRPhys;
641 /** R0 memory object for the MSR load area (1 page). */
642 RTR0MEMOBJ pMemObjHostMSR;
643 /** Virtual address of the MSR load area (1 page). */
644 R0PTRTYPE(uint8_t *) pHostMSR;
645#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
646
647 /* Number of automatically loaded/restored MSRs. */
648 uint32_t cCachedMSRs;
649 uint32_t uAlignement;
650
651 /* Last use TSC offset value. (cached) */
652 uint64_t u64TSCOffset;
653
654 /** VMCS cache. */
655 VMCSCACHE VMCSCache;
656
657 /** Real-mode emulation state. */
658 struct
659 {
660 X86EFLAGS eflags;
661 uint32_t fValid;
662 } RealMode;
663
664 struct
665 {
666 uint64_t u64VMCSPhys;
667 uint32_t ulVMCSRevision;
668 uint32_t ulInstrError;
669 uint32_t ulExitReason;
670 RTCPUID idEnteredCpu;
671 RTCPUID idCurrentCpu;
672 uint32_t padding;
673 } lasterror;
674
675 /** The last seen guest paging mode (by VT-x). */
676 PGMMODE enmLastSeenGuestMode;
677 /** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
678 PGMMODE enmCurrGuestMode;
679 /** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
680 PGMMODE enmPrevGuestMode;
681 } vmx;
682
683 struct
684 {
685 /** R0 memory object for the host VM control block (VMCB). */
686 RTR0MEMOBJ pMemObjVMCBHost;
687 /** Physical address of the host VM control block (VMCB). */
688 RTHCPHYS pVMCBHostPhys;
689 /** Virtual address of the host VM control block (VMCB). */
690 R0PTRTYPE(void *) pVMCBHost;
691
692 /** R0 memory object for the VM control block (VMCB). */
693 RTR0MEMOBJ pMemObjVMCB;
694 /** Physical address of the VM control block (VMCB). */
695 RTHCPHYS pVMCBPhys;
696 /** Virtual address of the VM control block (VMCB). */
697 R0PTRTYPE(void *) pVMCB;
698
699 /** Ring 0 handlers for VT-x. */
700 PFNHWACCMSVMVMRUN pfnVMRun;
701
702 /** R0 memory object for the MSR bitmap (8kb). */
703 RTR0MEMOBJ pMemObjMSRBitmap;
704 /** Physical address of the MSR bitmap (8kb). */
705 RTHCPHYS pMSRBitmapPhys;
706 /** Virtual address of the MSR bitmap. */
707 R0PTRTYPE(void *) pMSRBitmap;
708 } svm;
709
710 /** Event injection state. */
711 struct
712 {
713 uint32_t fPending;
714 uint32_t errCode;
715 uint64_t intInfo;
716 } Event;
717
718 /** IO Block emulation state. */
719 struct
720 {
721 bool fEnabled;
722 uint8_t u8Align[7];
723
724 /** RIP at the start of the io code we wish to emulate in the recompiler. */
725 RTGCPTR GCPtrFunctionEip;
726
727 uint64_t cr0;
728 } EmulateIoBlock;
729
730 struct
731 {
732 /* Pending IO operation type. */
733 HWACCMPENDINGIO enmType;
734 uint32_t uPadding;
735 RTGCPTR GCPtrRip;
736 RTGCPTR GCPtrRipNext;
737 union
738 {
739 struct
740 {
741 unsigned uPort;
742 unsigned uAndVal;
743 unsigned cbSize;
744 } Port;
745 uint64_t aRaw[2];
746 } s;
747 } PendingIO;
748
749 /** Currently shadow paging mode. */
750 PGMMODE enmShadowMode;
751
752 /** The CPU ID of the CPU currently owning the VMCS. Set in
753 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
754 RTCPUID idEnteredCpu;
755
756 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
757 struct
758 {
759 RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
760 unsigned cPages;
761 } TlbShootdown;
762
763 /** For saving stack space, the disassembler state is allocated here instead of
764 * on the stack.
765 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
766 union
767 {
768 /** The disassembler scratch space. */
769 DISCPUSTATE DisState;
770 /** Padding. */
771 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
772 };
773
774 RTUINT padding2[1];
775
776 STAMPROFILEADV StatEntry;
777 STAMPROFILEADV StatExit1;
778 STAMPROFILEADV StatExit2;
779#if 1 /* temporary for tracking down darwin issues. */
780 STAMPROFILEADV StatExit2Sub1;
781 STAMPROFILEADV StatExit2Sub2;
782 STAMPROFILEADV StatExit2Sub3;
783#endif
784 STAMPROFILEADV StatInGC;
785
786#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
787 STAMPROFILEADV StatWorldSwitch3264;
788#endif
789 STAMPROFILEADV StatPoke;
790 STAMPROFILEADV StatSpinPoke;
791 STAMPROFILEADV StatSpinPokeFailed;
792
793 STAMCOUNTER StatIntInject;
794
795 STAMCOUNTER StatExitShadowNM;
796 STAMCOUNTER StatExitGuestNM;
797 STAMCOUNTER StatExitShadowPF;
798 STAMCOUNTER StatExitGuestPF;
799 STAMCOUNTER StatExitGuestUD;
800 STAMCOUNTER StatExitGuestSS;
801 STAMCOUNTER StatExitGuestNP;
802 STAMCOUNTER StatExitGuestGP;
803 STAMCOUNTER StatExitGuestDE;
804 STAMCOUNTER StatExitGuestDB;
805 STAMCOUNTER StatExitGuestMF;
806 STAMCOUNTER StatExitInvpg;
807 STAMCOUNTER StatExitInvd;
808 STAMCOUNTER StatExitCpuid;
809 STAMCOUNTER StatExitRdtsc;
810 STAMCOUNTER StatExitRdpmc;
811 STAMCOUNTER StatExitCli;
812 STAMCOUNTER StatExitSti;
813 STAMCOUNTER StatExitPushf;
814 STAMCOUNTER StatExitPopf;
815 STAMCOUNTER StatExitIret;
816 STAMCOUNTER StatExitInt;
817 STAMCOUNTER StatExitCRxWrite[16];
818 STAMCOUNTER StatExitCRxRead[16];
819 STAMCOUNTER StatExitDRxWrite;
820 STAMCOUNTER StatExitDRxRead;
821 STAMCOUNTER StatExitRdmsr;
822 STAMCOUNTER StatExitWrmsr;
823 STAMCOUNTER StatExitCLTS;
824 STAMCOUNTER StatExitHlt;
825 STAMCOUNTER StatExitMwait;
826 STAMCOUNTER StatExitMonitor;
827 STAMCOUNTER StatExitLMSW;
828 STAMCOUNTER StatExitIOWrite;
829 STAMCOUNTER StatExitIORead;
830 STAMCOUNTER StatExitIOStringWrite;
831 STAMCOUNTER StatExitIOStringRead;
832 STAMCOUNTER StatExitIrqWindow;
833 STAMCOUNTER StatExitMaxResume;
834 STAMCOUNTER StatExitPreemptPending;
835 STAMCOUNTER StatIntReinject;
836 STAMCOUNTER StatPendingHostIrq;
837
838 STAMCOUNTER StatFlushPage;
839 STAMCOUNTER StatFlushPageManual;
840 STAMCOUNTER StatFlushPhysPageManual;
841 STAMCOUNTER StatFlushTLB;
842 STAMCOUNTER StatFlushTLBManual;
843 STAMCOUNTER StatFlushPageInvlpg;
844 STAMCOUNTER StatFlushTLBWorldSwitch;
845 STAMCOUNTER StatNoFlushTLBWorldSwitch;
846 STAMCOUNTER StatFlushTLBCRxChange;
847 STAMCOUNTER StatFlushASID;
848 STAMCOUNTER StatFlushTLBInvlpga;
849 STAMCOUNTER StatTlbShootdown;
850 STAMCOUNTER StatTlbShootdownFlush;
851
852 STAMCOUNTER StatSwitchGuestIrq;
853 STAMCOUNTER StatSwitchToR3;
854
855 STAMCOUNTER StatTSCOffset;
856 STAMCOUNTER StatTSCIntercept;
857 STAMCOUNTER StatTSCInterceptOverFlow;
858
859 STAMCOUNTER StatExitReasonNPF;
860 STAMCOUNTER StatDRxArmed;
861 STAMCOUNTER StatDRxContextSwitch;
862 STAMCOUNTER StatDRxIOCheck;
863
864 STAMCOUNTER StatLoadMinimal;
865 STAMCOUNTER StatLoadFull;
866
867#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
868 STAMCOUNTER StatFpu64SwitchBack;
869 STAMCOUNTER StatDebug64SwitchBack;
870#endif
871
872#ifdef VBOX_WITH_STATISTICS
873 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
874 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
875 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
876 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
877#endif
878} HWACCMCPU;
879/** Pointer to HWACCM VM instance data. */
880typedef HWACCMCPU *PHWACCMCPU;
881
882
883#ifdef IN_RING0
884
885VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
886VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
887
888
889#ifdef VBOX_STRICT
890VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
891VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
892#else
893# define HWACCMDumpRegs(a, b ,c) do { } while (0)
894# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
895#endif
896
897/* Dummy callback handlers. */
898VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
899VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
900VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
901VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
902VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
903VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
904VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
905VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
906VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
907VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
908
909# ifdef VBOX_WITH_KERNEL_USING_XMM
910DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
911DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
912# endif
913
914# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
915/**
916 * Gets 64-bit GDTR and IDTR on darwin.
917 * @param pGdtr Where to store the 64-bit GDTR.
918 * @param pIdtr Where to store the 64-bit IDTR.
919 */
920DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
921
922/**
923 * Gets 64-bit CR3 on darwin.
924 * @returns CR3
925 */
926DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
927# endif
928
929#endif /* IN_RING0 */
930
931/** @} */
932
933RT_C_DECLS_END
934
935#endif
936
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