ConsoleImplConfigArmV8.cpp@ 103085

Last change on this file since 103085 was 103085, checked in by vboxsync, 10 months ago
Main,FE/VBoxManage,FE/VirtualBox,ValidationKit: Allow setting the primary VM execution engine to make it easier to force particular engine for testing, bugref:10583
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1	/* $Id: ConsoleImplConfigArmV8.cpp 103085 2024-01-26 16:17:43Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4	*/
5
6	/*
7	* Copyright (C) 2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33	#include "LoggingNew.h"
34
35	#include "ConsoleImpl.h"
36	#include "ResourceStoreImpl.h"
37	#include "Global.h"
38	#include "VMMDev.h"
39
40	// generated header
41	#include "SchemaDefs.h"
42
43	#include "AutoCaller.h"
44
45	#include <iprt/buildconfig.h>
46	#include <iprt/ctype.h>
47	#include <iprt/dir.h>
48	#include <iprt/fdt.h>
49	#include <iprt/file.h>
50	#include <iprt/param.h>
51	#include <iprt/path.h>
52	#include <iprt/string.h>
53	#include <iprt/system.h>
54	#if 0 /* enable to play with lots of memory. */
55	# include <iprt/env.h>
56	#endif
57	#include <iprt/stream.h>
58
59	#include <iprt/formats/arm-psci.h>
60
61	#include <VBox/vmm/vmmr3vtable.h>
62	#include <VBox/vmm/vmapi.h>
63	#include <VBox/err.h>
64	#include <VBox/param.h>
65	#include <VBox/version.h>
66	#include <VBox/platforms/vbox-armv8.h>
67
68	#include "BusAssignmentManager.h"
69	#include "ResourceAssignmentManager.h"
70	#ifdef VBOX_WITH_EXTPACK
71	# include "ExtPackManagerImpl.h"
72	#endif
73
74
75	/*********************************************************************************************************************************
76	* Internal Functions *
77	*********************************************************************************************************************************/
78
79	/* Darwin compile kludge */
80	#undef PVM
81
82	#ifdef VBOX_WITH_VIRT_ARMV8
83	/**
84	* Worker for configConstructor.
85	*
86	* @return VBox status code.
87	* @param pUVM The user mode VM handle.
88	* @param pVM The cross context VM handle.
89	* @param pVMM The VMM vtable.
90	* @param pAlock The automatic lock instance. This is for when we have
91	* to leave it in order to avoid deadlocks (ext packs and
92	* more).
93	*/
94	int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
95	{
96	RT_NOREF(pVM /* when everything is disabled */);
97	ComPtr<IMachine> pMachine = i_machine();
98
99	HRESULT hrc;
100	Utf8Str strTmp;
101	Bstr bstr;
102
103	RTFDT hFdt = NIL_RTFDT;
104	int vrc = RTFdtCreateEmpty(&hFdt);
105	AssertRCReturn(vrc, vrc);
106
107	#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
108	#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
109
110	/** @todo Find a way to figure it out before CPUM is set up, can't use CPUMGetGuestAddrWidths() and on macOS we need
111	* access to Hypervisor.framework to query the ID registers (Linux can in theory parse /proc/cpuinfo, no idea for Windows). */
112	RTGCPHYS GCPhysTopOfAddrSpace = RT_BIT_64(36);
113
114	/*
115	* Get necessary objects and frequently used parameters.
116	*/
117	ComPtr<IVirtualBox> virtualBox;
118	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
119
120	ComPtr<IHost> host;
121	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
122
123	PlatformArchitecture_T platformArchHost;
124	hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
125
126	ComPtr<ISystemProperties> systemProperties;
127	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
128
129	ComPtr<IFirmwareSettings> firmwareSettings;
130	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
131
132	ComPtr<INvramStore> nvramStore;
133	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
134
135	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
136	RTUUID HardwareUuid;
137	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
138	AssertRCReturn(vrc, vrc);
139
140	ULONG cRamMBs;
141	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
142	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
143
144	ComPtr<IPlatform> platform;
145	hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
146
147	/* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
148	#if 1 /* For now we only support running ARM VMs on ARM hosts. */
149	PlatformArchitecture_T platformArchMachine;
150	hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
151	if (platformArchMachine != platformArchHost)
152	return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
153	N_("VM platform architecture (%s) not supported on this host (%s)."),
154	Global::stringifyPlatformArchitecture(platformArchMachine),
155	Global::stringifyPlatformArchitecture(platformArchHost));
156	#endif
157
158	ComPtr<IPlatformProperties> pPlatformProperties;
159	hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
160
161	ChipsetType_T chipsetType;
162	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
163
164	ULONG cCpus = 1;
165	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
166	Assert(cCpus);
167
168	ULONG ulCpuExecutionCap = 100;
169	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
170
171	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
172	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
173
174	if ( enmExecEngine != VMExecutionEngine_Default
175	&& enmExecEngine != VMExecutionEngine_NativeApi)
176	{
177	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
178	N_("The ARM backend doesn't support any other execution engine than 'default' or 'native-api' right now."));
179	}
180
181	LogRel(("Guest architecture: ARM\n"));
182
183	Bstr osTypeId;
184	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
185	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
186
187	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
188	ResourceAssignmentManager *pResMgr = ResourceAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None,
189	GCPhysTopOfAddrSpace - sizeof(VBOXPLATFORMARMV8),
190	_1G, /GCPhysRam/
191	128 * _1M, /GCPhysMmio32Start/
192	_1G - 128 * _1M, /cbMmio32/
193	32 /cInterrupts/);
194
195	/*
196	* Get root node first.
197	* This is the only node in the tree.
198	*/
199	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
200	Assert(pRoot);
201
202	RTGCPHYS GCPhysRam = NIL_RTGCPHYS;
203
204	// catching throws from InsertConfigString and friends.
205	try
206	{
207
208	/*
209	* Set the root (and VMM) level values.
210	*/
211	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
212	InsertConfigString(pRoot, "Name", bstr);
213	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
214	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
215	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
216	InsertConfigInteger(pRoot, "TimerMillies", 10);
217
218	/*
219	* NEM
220	*/
221	PCFGMNODE pNEM;
222	InsertConfigNode(pRoot, "NEM", &pNEM);
223
224	uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
225	Assert(idPHandleIntCtrl != UINT32_MAX);
226	uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
227	Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
228	uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
229	Assert(idPHandleAbpPClk != UINT32_MAX);
230	uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
231	Assert(idPHandleGpio != UINT32_MAX);
232
233	uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
234	for (uint32_t i = 0; i < cCpus; i++)
235	{
236	aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
237	Assert(aidPHandleCpus[i] != UINT32_MAX);
238	}
239
240	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
241	vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
242	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
243	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
244	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
245
246	/* Configure the Power State Coordination Interface. */
247	vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
248	vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
249	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
250	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
251	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
252	vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
253	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
254	"arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
255	vrc = RTFdtNodeFinalize(hFdt); VRC();
256
257	/* Configure the timer and clock. */
258	InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
259	vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
260	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
261	0x01, 0x0d, 0x104,
262	0x01, 0x0e, 0x104,
263	0x01, 0x0b, 0x104,
264	0x01, 0x0a, 0x104); VRC();
265	vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
266	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
267	vrc = RTFdtNodeFinalize(hFdt);
268
269	vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
270	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
271	vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
272	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24 * 1000 * 1000); VRC();
273	vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
274	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
275	vrc = RTFdtNodeFinalize(hFdt);
276
277	/*
278	* MM values.
279	*/
280	PCFGMNODE pMM;
281	InsertConfigNode(pRoot, "MM", &pMM);
282
283	/*
284	* Memory setup.
285	*/
286	PCFGMNODE pMem = NULL;
287	InsertConfigNode(pMM, "MemRegions", &pMem);
288
289	hrc = pResMgr->assignRamRegion("Conventional", cbRam, &GCPhysRam); H();
290
291	PCFGMNODE pMemRegion = NULL;
292	InsertConfigNode(pMem, "Conventional", &pMemRegion);
293	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRam);
294	InsertConfigInteger(pMemRegion, "Size", cbRam);
295
296	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRam); VRC();
297	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRam, cbRam); VRC();
298	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
299	vrc = RTFdtNodeFinalize(hFdt); VRC();
300
301	/* Configure the CPUs in the system, only one socket and cluster at the moment. */
302	vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
303	vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
304	vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
305
306	vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
307	vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
308
309	for (uint32_t i = 0; i < cCpus; i++)
310	{
311	vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
312	vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
313	vrc = RTFdtNodeFinalize(hFdt); VRC();
314	}
315
316	vrc = RTFdtNodeFinalize(hFdt); VRC();
317	vrc = RTFdtNodeFinalize(hFdt); VRC();
318
319	for (uint32_t i = 0; i < cCpus; i++)
320	{
321	vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
322	vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
323	vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
324	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
325	vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
326	if (cCpus > 1)
327	{
328	vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
329	}
330	vrc = RTFdtNodeFinalize(hFdt); VRC();
331	}
332
333	vrc = RTFdtNodeFinalize(hFdt); VRC();
334
335
336	/*
337	* PDM config.
338	* Load drivers in VBoxC.[so\|dll]
339	*/
340	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
341
342
343	/*
344	* VGA.
345	*/
346	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
347	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
348	GraphicsControllerType_T enmGraphicsController;
349	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
350
351	/*
352	* Devices
353	*/
354	PCFGMNODE pDevices = NULL; /* /Devices */
355	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
356	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
357	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
358	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
359
360	InsertConfigNode(pRoot, "Devices", &pDevices);
361
362	InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
363
364	InsertConfigNode(pDevices, "platform", &pDev);
365	InsertConfigNode(pDev, "0", &pInst);
366	InsertConfigNode(pInst, "Config", &pCfg);
367	InsertConfigNode(pInst, "LUN#0", &pLunL0);
368	InsertConfigString(pLunL0, "Driver", "ResourceStore");
369
370	/* Add the resources. */
371	PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
372	PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
373	InsertConfigString(pCfg, "ResourceNamespace", "resources");
374	InsertConfigNode(pCfg, "Resources", &pResources);
375	InsertConfigNode(pResources, "EfiRom", &pRes);
376	InsertConfigInteger(pRes, "RegisterAsRom", 1);
377	InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
378
379	/** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
380	/*
381	* Firmware.
382	*/
383	FirmwareType_T eFwType = FirmwareType_EFI64;
384	#ifdef VBOX_WITH_EFI_IN_DD2
385	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
386	: eFwType == FirmwareType_EFI32 ? "VBoxEFIAArch32.fd"
387	: "VBoxEFIAArch64.fd";
388	const char *pszKey = "ResourceId";
389	#else
390	Utf8Str efiRomFile;
391	vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
392	AssertRCReturn(vrc, vrc);
393	const char *pszEfiRomFile = efiRomFile.c_str();
394	const char *pszKey = "Filename";
395	#endif
396	InsertConfigString(pRes, pszKey, pszEfiRomFile);
397
398	InsertConfigNode(pResources, "ArmV8Desc", &pRes);
399	InsertConfigInteger(pRes, "RegisterAsRom", 1);
400	InsertConfigInteger(pRes, "GCPhysLoadAddress", UINT64_MAX); /* End of physical address space. */
401	InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
402
403	/*
404	* Configure the interrupt controller.
405	*/
406	RTGCPHYS GCPhysIntcDist;
407	RTGCPHYS GCPhysIntcReDist;
408	RTGCPHYS cbMmioIntcDist;
409	RTGCPHYS cbMmioIntcReDist;
410
411	/* Each vCPU needs on re-distributor, this would allow for up to 256 vCPUs in the future. */
412	hrc = pResMgr->assignMmioRegion("gic", 256 * _64K, &GCPhysIntcReDist, &cbMmioIntcReDist); H();
413	hrc = pResMgr->assignMmioRegion("gic", _64K, &GCPhysIntcDist, &cbMmioIntcDist); H();
414
415	InsertConfigNode(pDevices, "gic", &pDev);
416	InsertConfigNode(pDev, "0", &pInst);
417	InsertConfigInteger(pInst, "Trusted", 1);
418	InsertConfigNode(pInst, "Config", &pCfg);
419	InsertConfigInteger(pCfg, "DistributorMmioBase", GCPhysIntcDist);
420	InsertConfigInteger(pCfg, "RedistributorMmioBase", GCPhysIntcReDist);
421
422	vrc = RTFdtNodeAddF(hFdt, "intc@%RGp", GCPhysIntcDist); VRC();
423	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
424	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
425	GCPhysIntcDist, cbMmioIntcDist, /* Distributor */
426	GCPhysIntcReDist, cbMmioIntcReDist); /* Re-Distributor */ VRC();
427	vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
428	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
429	vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
430	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
431	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
432	vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
433	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
434
435	#if 0
436	vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
437	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
438	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
439	vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
440	vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
441	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
442	vrc = RTFdtNodeFinalize(hFdt); VRC();
443	#endif
444
445	vrc = RTFdtNodeFinalize(hFdt); VRC();
446
447	RTGCPHYS GCPhysMmioStart;
448	RTGCPHYS cbMmio;
449	if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
450	{
451	hrc = pResMgr->assignMmioRegion("qemu-fw-cfg", _4K, &GCPhysMmioStart, &cbMmio); H();
452
453	InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
454	InsertConfigNode(pDev, "0", &pInst);
455	InsertConfigNode(pInst, "Config", &pCfg);
456	InsertConfigInteger(pCfg, "MmioSize", cbMmio);
457	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
458	InsertConfigInteger(pCfg, "DmaEnabled", 1);
459	InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
460	InsertConfigNode(pInst, "LUN#0", &pLunL0);
461	InsertConfigString(pLunL0, "Driver", "MainDisplay");
462
463	vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RGp", GCPhysMmioStart); VRC();
464	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
465	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
466	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
467	vrc = RTFdtNodeFinalize(hFdt); VRC();
468	}
469
470	InsertConfigNode(pDevices, "flash-cfi", &pDev);
471	InsertConfigNode(pDev, "0", &pInst);
472	InsertConfigNode(pInst, "Config", &pCfg);
473	InsertConfigInteger(pCfg, "BaseAddress", 64 * _1M);
474	InsertConfigInteger(pCfg, "Size", 768 * _1K);
475	InsertConfigString(pCfg, "FlashFile", "nvram");
476	/* Attach the NVRAM storage driver. */
477	InsertConfigNode(pInst, "LUN#0", &pLunL0);
478	InsertConfigString(pLunL0, "Driver", "NvramStore");
479
480	vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
481	vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
482	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
483	0, 0x04000000, /* First region (EFI). */
484	0x04000000, 0x04000000); /* Second region (NVRAM). */ VRC();
485	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
486	vrc = RTFdtNodeFinalize(hFdt); VRC();
487
488	InsertConfigNode(pDevices, "arm-pl011", &pDev);
489	for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
490	{
491	ComPtr<ISerialPort> serialPort;
492	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
493	BOOL fEnabledSerPort = FALSE;
494	if (serialPort)
495	{
496	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
497	}
498	if (!fEnabledSerPort)
499	{
500	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
501	continue;
502	}
503
504	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
505	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
506	InsertConfigNode(pInst, "Config", &pCfg);
507
508	uint32_t iIrq = 0;
509	hrc = pResMgr->assignSingleInterrupt("arm-pl011", &iIrq); H();
510	hrc = pResMgr->assignMmioRegion("arm-pl011", _4K, &GCPhysMmioStart, &cbMmio); H();
511
512	InsertConfigInteger(pCfg, "Irq", iIrq);
513	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
514
515	vrc = RTFdtNodeAddF(hFdt, "pl011@%RGp", GCPhysMmioStart); VRC();
516	vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
517	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
518	idPHandleAbpPClk, idPHandleAbpPClk); VRC();
519	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
520	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
521	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
522	"arm,pl011", "arm,primecell"); VRC();
523	vrc = RTFdtNodeFinalize(hFdt); VRC();
524
525	BOOL fServer;
526	hrc = serialPort->COMGETTER(Server)(&fServer); H();
527	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
528
529	PortMode_T eHostMode;
530	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
531
532	m_aeSerialPortMode[ulInstance] = eHostMode;
533	if (eHostMode != PortMode_Disconnected)
534	{
535	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
536	if (RT_FAILURE(vrc))
537	return vrc;
538	}
539	}
540
541	BOOL fRTCUseUTC;
542	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
543
544	uint32_t iIrq = 0;
545	hrc = pResMgr->assignSingleInterrupt("arm-pl031-rtc", &iIrq); H();
546	hrc = pResMgr->assignMmioRegion("arm-pl031-rtc", _4K, &GCPhysMmioStart, &cbMmio); H();
547	InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
548	InsertConfigNode(pDev, "0", &pInst);
549	InsertConfigNode(pInst, "Config", &pCfg);
550	InsertConfigInteger(pCfg, "Irq", iIrq);
551	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
552	InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
553
554	vrc = RTFdtNodeAddF(hFdt, "pl032@%RGp", GCPhysMmioStart); VRC();
555	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
556	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
557	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
558	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
559	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
560	"arm,pl031", "arm,primecell"); VRC();
561	vrc = RTFdtNodeFinalize(hFdt); VRC();
562
563	/* Configure gpio keys. */
564	hrc = pResMgr->assignSingleInterrupt("arm-pl061-gpio", &iIrq); H();
565	hrc = pResMgr->assignMmioRegion("arm-pl061-gpio", _4K, &GCPhysMmioStart, &cbMmio); H();
566	InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
567	InsertConfigNode(pDev, "0", &pInst);
568	InsertConfigNode(pInst, "Config", &pCfg);
569	InsertConfigInteger(pCfg, "Irq", iIrq);
570	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
571	vrc = RTFdtNodeAddF(hFdt, "pl061@%RGp", GCPhysMmioStart); VRC();
572	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
573	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
574	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
575	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
576	vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
577	vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
578	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
579	"arm,pl061", "arm,primecell"); VRC();
580	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
581	vrc = RTFdtNodeFinalize(hFdt); VRC();
582
583	InsertConfigNode(pInst, "LUN#0", &pLunL0);
584	InsertConfigString(pLunL0, "Driver", "GpioButton");
585	InsertConfigNode(pLunL0, "Config", &pCfg);
586	InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
587	InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
588
589	vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
590	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
591
592	vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
593	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
594	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
595	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
596	vrc = RTFdtNodeFinalize(hFdt); VRC();
597
598	vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
599	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
600	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
601	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
602	vrc = RTFdtNodeFinalize(hFdt);
603
604	vrc = RTFdtNodeFinalize(hFdt); VRC();
605
606	hrc = pResMgr->assignInterrupts("pci-generic-ecam", 4 /cInterrupts/, &iIrq); H();
607	uint32_t aPinIrqs[] = { iIrq, iIrq + 1, iIrq + 2, iIrq + 3 };
608	RTGCPHYS GCPhysPciMmioEcam, GCPhysPciMmio, GCPhysPciMmio32;
609	RTGCPHYS cbPciMmioEcam, cbPciMmio, cbPciMmio32;
610	hrc = pResMgr->assignMmioRegionAligned("pci-pio", _64K, _64K, &GCPhysMmioStart, &cbMmio); H();
611	hrc = pResMgr->assignMmioRegion( "pci-ecam", 16 * _1M, &GCPhysPciMmioEcam, &cbPciMmioEcam); H();
612	hrc = pResMgr->assignMmioRegion( "pci-mmio", _2G, &GCPhysPciMmio, &cbPciMmio); H();
613	hrc = pResMgr->assignMmio32Region( "pci-mmio32", (1024 - 128) * _1M, &GCPhysPciMmio32, &cbPciMmio32); H();
614
615	InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
616	InsertConfigNode(pDev, "0", &pInst);
617	InsertConfigNode(pInst, "Config", &pCfg);
618	InsertConfigInteger(pCfg, "MmioEcamBase", GCPhysPciMmioEcam);
619	InsertConfigInteger(pCfg, "MmioEcamLength", cbPciMmioEcam);
620	InsertConfigInteger(pCfg, "MmioPioBase", GCPhysMmioStart);
621	InsertConfigInteger(pCfg, "MmioPioSize", cbMmio);
622	InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
623	InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
624	InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
625	InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
626	vrc = RTFdtNodeAddF(hFdt, "pcie@%RGp", GCPhysPciMmio); VRC();
627	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
628
629	uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
630	uint32_t *pau32IrqCell = &aIrqCells[0];
631	uint32_t iIrqPinSwizzle = 0;
632
633	for (uint32_t i = 0; i < 32; i++)
634	{
635	for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
636	{
637	pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
638	pau32IrqCell[1] = 0;
639	pau32IrqCell[2] = 0;
640	pau32IrqCell[3] = iIrqPin + 1;
641	pau32IrqCell[4] = idPHandleIntCtrl;
642	pau32IrqCell[5] = 0;
643	pau32IrqCell[6] = 0;
644	pau32IrqCell[7] = 0;
645	pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
646	pau32IrqCell[9] = 0x04;
647	pau32IrqCell += 10;
648	}
649
650	iIrqPinSwizzle++;
651	}
652
653	vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]);
654	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
655	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 21,
656	0x1000000, 0, 0,
657	GCPhysMmioStart >> 32, GCPhysMmioStart, cbMmio >> 32, cbMmio,
658	0x2000000, GCPhysPciMmio32 >> 32, GCPhysPciMmio32, GCPhysPciMmio32 >> 32, GCPhysPciMmio32,
659	cbPciMmio32 >> 32, cbPciMmio32,
660	0x3000000, GCPhysPciMmio >> 32, GCPhysPciMmio, GCPhysPciMmio >> 32, GCPhysPciMmio,
661	cbPciMmio >> 32, cbPciMmio); VRC();
662	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysPciMmioEcam, cbPciMmioEcam); VRC();
663	/** @todo msi-map */
664	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
665	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
666	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
667	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
668	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
669	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
670	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
671	vrc = RTFdtNodeFinalize(hFdt); VRC();
672
673	/*
674	* VMSVGA compliant graphics controller.
675	*/
676	if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
677	&& enmGraphicsController != GraphicsControllerType_Null)
678	{
679	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
680	pGraphicsAdapter, firmwareSettings,
681	true /fForceVmSvga3/, false /fExposeLegacyVga/); VRC();
682	}
683
684	/*
685	* The USB Controllers and input devices.
686	*/
687	#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
688	KeyboardHIDType_T aKbdHID;
689	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
690	#endif
691
692	PointingHIDType_T aPointingHID;
693	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
694
695	PCFGMNODE pUsbDevices = NULL;
696	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
697
698	/*
699	* Storage controllers.
700	*/
701	bool fFdcEnabled = false;
702	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
703	pDevices, pUsbDevices, NULL /pBiosCfg/, &fFdcEnabled); VRC();
704
705	/*
706	* Network adapters
707	*/
708	std::list<BootNic> llBootNics;
709	vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
710	pVMM, pUVM, pDevices, llBootNics); VRC();
711
712	/*
713	* The VMM device.
714	*/
715	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /fMmioReq/); VRC();
716
717	/*
718	* Audio configuration.
719	*/
720	bool fAudioEnabled = false;
721	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
722	false /fOsXGuest/, &fAudioEnabled); VRC();
723	}
724	catch (ConfigError &x)
725	{
726	RTFdtDestroy(hFdt);
727
728	// InsertConfig threw something:
729	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
730	return x.m_vrc;
731	}
732	catch (HRESULT hrcXcpt)
733	{
734	RTFdtDestroy(hFdt);
735	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
736	}
737
738	#ifdef VBOX_WITH_EXTPACK
739	/*
740	* Call the extension pack hooks if everything went well thus far.
741	*/
742	if (RT_SUCCESS(vrc))
743	{
744	pAlock->release();
745	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
746	pAlock->acquire();
747	}
748	#endif
749
750	#if 0
751	vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
752	vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
753	vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
754	vrc = RTFdtNodeFinalize(hFdt);
755	#endif
756
757	/* Finalize the FDT and add it to the resource store. */
758	vrc = RTFdtFinalize(hFdt);
759	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
760
761	RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
762	vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /cbEstimate/, &hVfsFileDesc);
763	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
764	RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
765	AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
766
767	/* Initialize the VBox platform descriptor. */
768	VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
769
770	vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, hVfsIosDesc, NULL /pErrInfo/);
771	if (RT_SUCCESS(vrc))
772	vrc = RTVfsFileQuerySize(hVfsFileDesc, &ArmV8Platform.cbFdt);
773	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
774
775	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(ArmV8Platform.cbFdt, _64K) - ArmV8Platform.cbFdt));
776	AssertRCReturn(vrc, vrc);
777
778	RTGCPHYS GCPhysMmioStart;
779	RTGCPHYS cbMmio;
780	hrc = pResMgr->queryMmioRegion(&GCPhysMmioStart, &cbMmio);
781	Assert(SUCCEEDED(hrc));
782
783	RTGCPHYS GCPhysMmio32Start;
784	RTGCPHYS cbMmio32;
785	hrc = pResMgr->queryMmio32Region(&GCPhysMmio32Start, &cbMmio32);
786	Assert(SUCCEEDED(hrc));
787
788	ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
789	ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
790	ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
791	ArmV8Platform.fFlags = 0;
792	ArmV8Platform.u64PhysAddrRamBase = GCPhysRam;
793	ArmV8Platform.cbRamBase = cbRam;
794	ArmV8Platform.u64OffBackFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
795	ArmV8Platform.cbFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
796	ArmV8Platform.u64OffBackAcpiXsdp = 0;
797	ArmV8Platform.cbAcpiXsdp = 0;
798	ArmV8Platform.u64OffBackUefiRom = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform);
799	ArmV8Platform.cbUefiRom = _64M; /** @todo Fixed reservation but the ROM region is usually much smaller. */
800	ArmV8Platform.u64OffBackMmio = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform) - GCPhysMmioStart;
801	ArmV8Platform.cbMmio = cbMmio;
802	ArmV8Platform.u64OffBackMmio32 = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform) - GCPhysMmio32Start;
803	ArmV8Platform.cbMmio32 = cbMmio32;
804
805	/* Add the VBox platform descriptor to the resource store. */
806	vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /fBlocking/, NULL /pcbWritten/);
807	RTVfsIoStrmRelease(hVfsIosDesc);
808	vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
809	RTVfsFileRelease(hVfsFileDesc);
810	AssertRCReturn(vrc, vrc);
811
812	/* Dump the DTB for debugging purposes if requested. */
813	Bstr DtbDumpVal;
814	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
815	DtbDumpVal.asOutParam());
816	if ( hrc == S_OK
817	&& DtbDumpVal.isNotEmpty())
818	{
819	vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, Utf8Str(DtbDumpVal).c_str(), NULL /pErrInfo/);
820	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
821	}
822
823	delete pResMgr; /* Delete the address/interrupt assignment manager. */
824
825	/*
826	* Apply the CFGM overlay.
827	*/
828	if (RT_SUCCESS(vrc))
829	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
830
831	/*
832	* Dump all extradata API settings tweaks, both global and per VM.
833	*/
834	if (RT_SUCCESS(vrc))
835	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
836
837	#undef H
838
839	pAlock->release(); /* Avoid triggering the lock order inversion check. */
840
841	/*
842	* Register VM state change handler.
843	*/
844	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
845	AssertRC(vrc2);
846	if (RT_SUCCESS(vrc))
847	vrc = vrc2;
848
849	/*
850	* Register VM runtime error handler.
851	*/
852	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
853	AssertRC(vrc2);
854	if (RT_SUCCESS(vrc))
855	vrc = vrc2;
856
857	pAlock->acquire();
858
859	LogFlowFunc(("vrc = %Rrc\n", vrc));
860	LogFlowFuncLeave();
861
862	return vrc;
863	}
864	#endif /* !VBOX_WITH_VIRT_ARMV8 */
865

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 103085

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