[54224] | 1 | /* $Id: SUPLibAll.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VirtualBox Support Library - All Contexts Code.
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| 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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[54224] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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[54224] | 11 | *
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[96407] | 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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[54224] | 25 | * The contents of this file may alternatively be used under the terms
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| 26 | * of the Common Development and Distribution License Version 1.0
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[96407] | 27 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | * in the VirtualBox distribution, in which case the provisions of the
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[54224] | 29 | * CDDL are applicable instead of those of the GPL.
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| 30 | *
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| 31 | * You may elect to license modified versions of this file under the
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| 32 | * terms and conditions of either the GPL or the CDDL or both.
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[96407] | 33 | *
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| 34 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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[54224] | 35 | */
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| 36 |
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[57358] | 37 |
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| 38 | /*********************************************************************************************************************************
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| 39 | * Header Files *
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| 40 | *********************************************************************************************************************************/
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[54224] | 41 | #include <VBox/sup.h>
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[54257] | 42 | #ifdef IN_RC
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| 43 | # include <VBox/vmm/vm.h>
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| 44 | # include <VBox/vmm/vmm.h>
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| 45 | #endif
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[54224] | 46 | #ifdef IN_RING0
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| 47 | # include <iprt/mp.h>
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| 48 | #endif
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| 49 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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| 50 | # include <iprt/asm-amd64-x86.h>
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| 51 | #endif
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[76389] | 52 | #include <iprt/errcore.h>
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[87700] | 53 | #if defined(IN_RING0) && defined(RT_OS_LINUX)
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| 54 | # include "SUPDrvInternal.h"
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| 55 | #endif
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[54224] | 56 |
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| 57 |
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[87700] | 58 |
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[54224] | 59 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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| 60 | /**
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| 61 | * The slow case for SUPReadTsc where we need to apply deltas.
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| 62 | *
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| 63 | * Must only be called when deltas are applicable, so please do not call it
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| 64 | * directly.
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| 65 | *
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| 66 | * @returns TSC with delta applied.
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[54308] | 67 | * @param pGip Pointer to the GIP.
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[54224] | 68 | *
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| 69 | * @remarks May be called with interrupts disabled in ring-0! This is why the
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| 70 | * ring-0 code doesn't attempt to figure the delta.
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| 71 | *
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| 72 | * @internal
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| 73 | */
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[54335] | 74 | SUPDECL(uint64_t) SUPReadTscWithDelta(PSUPGLOBALINFOPAGE pGip)
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[54224] | 75 | {
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[54257] | 76 | uint64_t uTsc;
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| 77 | uint16_t iGipCpu;
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| 78 | AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
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| 79 | AssertCompile(RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx) >= RTCPUSET_MAX_CPUS);
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[54308] | 80 | Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO);
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[54224] | 81 |
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| 82 | /*
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[54257] | 83 | * Read the TSC and get the corresponding aCPUs index.
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[54224] | 84 | */
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[54308] | 85 | #ifdef IN_RING3
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[54257] | 86 | if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
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[54224] | 87 | {
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[54257] | 88 | /* RDTSCP gives us all we need, no loops/cli. */
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| 89 | uint32_t iCpuSet;
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| 90 | uTsc = ASMReadTscWithAux(&iCpuSet);
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| 91 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 92 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 93 | }
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| 94 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
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| 95 | {
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| 96 | /* Storing the IDTR is normally very quick, but we need to loop. */
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| 97 | uint32_t cTries = 0;
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| 98 | for (;;)
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[54224] | 99 | {
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[54257] | 100 | uint16_t cbLim = ASMGetIdtrLimit();
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| 101 | uTsc = ASMReadTSC();
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| 102 | if (RT_LIKELY(ASMGetIdtrLimit() == cbLim))
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| 103 | {
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| 104 | uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
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| 105 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 106 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 107 | break;
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| 108 | }
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| 109 | if (cTries >= 16)
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| 110 | {
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| 111 | iGipCpu = UINT16_MAX;
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| 112 | break;
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| 113 | }
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| 114 | cTries++;
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| 115 | }
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| 116 | }
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[81071] | 117 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
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| 118 | {
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| 119 | /* Get APIC ID / 0x1b via the slow CPUID instruction, requires looping. */
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| 120 | uint32_t cTries = 0;
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| 121 | for (;;)
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| 122 | {
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| 123 | uint32_t idApic = ASMGetApicIdExt0B();
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| 124 | uTsc = ASMReadTSC();
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| 125 | if (RT_LIKELY(ASMGetApicIdExt0B() == idApic))
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| 126 | {
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| 127 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 128 | break;
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| 129 | }
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| 130 | if (cTries >= 16)
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| 131 | {
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| 132 | iGipCpu = UINT16_MAX;
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| 133 | break;
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| 134 | }
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| 135 | cTries++;
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| 136 | }
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| 137 | }
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| 138 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
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| 139 | {
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| 140 | /* Get APIC ID / 0x8000001e via the slow CPUID instruction, requires looping. */
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| 141 | uint32_t cTries = 0;
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| 142 | for (;;)
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| 143 | {
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| 144 | uint32_t idApic = ASMGetApicIdExt8000001E();
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| 145 | uTsc = ASMReadTSC();
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| 146 | if (RT_LIKELY(ASMGetApicIdExt8000001E() == idApic))
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| 147 | {
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| 148 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 149 | break;
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| 150 | }
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| 151 | if (cTries >= 16)
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| 152 | {
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| 153 | iGipCpu = UINT16_MAX;
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| 154 | break;
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| 155 | }
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| 156 | cTries++;
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| 157 | }
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| 158 | }
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[54257] | 159 | else
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| 160 | {
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[54308] | 161 | /* Get APIC ID via the slow CPUID instruction, requires looping. */
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[54257] | 162 | uint32_t cTries = 0;
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| 163 | for (;;)
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| 164 | {
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| 165 | uint8_t idApic = ASMGetApicId();
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| 166 | uTsc = ASMReadTSC();
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| 167 | if (RT_LIKELY(ASMGetApicId() == idApic))
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| 168 | {
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| 169 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 170 | break;
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| 171 | }
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| 172 | if (cTries >= 16)
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| 173 | {
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| 174 | iGipCpu = UINT16_MAX;
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| 175 | break;
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| 176 | }
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| 177 | cTries++;
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| 178 | }
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[54308] | 179 | }
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| 180 | #elif defined(IN_RING0)
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| 181 | /* Ring-0: Use use RTMpCpuId(), no loops. */
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| 182 | RTCCUINTREG uFlags = ASMIntDisableFlags();
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| 183 | int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
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| 184 | if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 185 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 186 | else
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| 187 | iGipCpu = UINT16_MAX;
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| 188 | uTsc = ASMReadTSC();
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| 189 | ASMSetFlags(uFlags);
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[54224] | 190 |
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[54257] | 191 | # elif defined(IN_RC)
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[54308] | 192 | /* Raw-mode context: We can get the host CPU set index via VMCPU, no loops. */
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| 193 | RTCCUINTREG uFlags = ASMIntDisableFlags(); /* Are already disable, but play safe. */
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| 194 | uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
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| 195 | if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 196 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 197 | else
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| 198 | iGipCpu = UINT16_MAX;
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| 199 | uTsc = ASMReadTSC();
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| 200 | ASMSetFlags(uFlags);
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| 201 | #else
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| 202 | # error "IN_RING3, IN_RC or IN_RING0 must be defined!"
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| 203 | #endif
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[54257] | 204 |
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[54224] | 205 | /*
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[54257] | 206 | * If the delta is valid, apply it.
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[54224] | 207 | */
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[54257] | 208 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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| 209 | {
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| 210 | int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
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| 211 | if (RT_LIKELY(iTscDelta != INT64_MAX))
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[55246] | 212 | return uTsc - iTscDelta;
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[54224] | 213 |
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[54257] | 214 | # ifdef IN_RING3
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| 215 | /*
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| 216 | * The delta needs calculating, call supdrv to get the TSC.
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| 217 | */
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| 218 | int rc = SUPR3ReadTsc(&uTsc, NULL);
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| 219 | if (RT_SUCCESS(rc))
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| 220 | return uTsc;
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| 221 | AssertMsgFailed(("SUPR3ReadTsc -> %Rrc\n", rc));
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| 222 | uTsc = ASMReadTSC();
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| 223 | # endif /* IN_RING3 */
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| 224 | }
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| 225 |
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[54224] | 226 | /*
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[54257] | 227 | * This shouldn't happen, especially not in ring-3 and raw-mode context.
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| 228 | * But if it does, return something that's half useful.
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[54224] | 229 | */
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[54257] | 230 | AssertMsgFailed(("iGipCpu=%d (%#x) cCpus=%d fGetGipCpu=%#x\n", iGipCpu, iGipCpu, pGip->cCpus, pGip->fGetGipCpu));
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[54224] | 231 | return uTsc;
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| 232 | }
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[87702] | 233 | # ifdef SUPR0_EXPORT_SYMBOL
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[87700] | 234 | SUPR0_EXPORT_SYMBOL(SUPReadTscWithDelta);
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| 235 | # endif
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[87235] | 236 | #endif /* RT_ARCH_AMD64 || RT_ARCH_X86 */
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[54224] | 237 |
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[54308] | 238 |
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| 239 | /**
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| 240 | * Internal worker for getting the GIP CPU array index for the calling CPU.
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| 241 | *
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| 242 | * @returns Index into SUPGLOBALINFOPAGE::aCPUs or UINT16_MAX.
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| 243 | * @param pGip The GIP.
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| 244 | */
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| 245 | DECLINLINE(uint16_t) supGetGipCpuIndex(PSUPGLOBALINFOPAGE pGip)
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| 246 | {
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| 247 | uint16_t iGipCpu;
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| 248 | #ifdef IN_RING3
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[87235] | 249 | # if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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[54308] | 250 | if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
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| 251 | {
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| 252 | /* Storing the IDTR is normally very fast. */
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| 253 | uint16_t cbLim = ASMGetIdtrLimit();
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| 254 | uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
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| 255 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 256 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 257 | }
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| 258 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
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| 259 | {
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| 260 | /* RDTSCP gives us what need need and more. */
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| 261 | uint32_t iCpuSet;
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| 262 | ASMReadTscWithAux(&iCpuSet);
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| 263 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 264 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 265 | }
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[81071] | 266 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
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| 267 | {
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| 268 | /* Get APIC ID via the slow CPUID/0000000B instruction. */
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| 269 | uint32_t idApic = ASMGetApicIdExt0B();
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| 270 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 271 | }
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| 272 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
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| 273 | {
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| 274 | /* Get APIC ID via the slow CPUID/8000001E instruction. */
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| 275 | uint32_t idApic = ASMGetApicIdExt8000001E();
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| 276 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 277 | }
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[54308] | 278 | else
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| 279 | {
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| 280 | /* Get APIC ID via the slow CPUID instruction. */
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| 281 | uint8_t idApic = ASMGetApicId();
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| 282 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 283 | }
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[87235] | 284 |
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| 285 | # else
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| 286 | int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
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| 287 | if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 288 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 289 | else
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| 290 | iGipCpu = UINT16_MAX;
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| 291 | # endif
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| 292 |
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[54308] | 293 | #elif defined(IN_RING0)
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| 294 | /* Ring-0: Use use RTMpCpuId() (disables cli to avoid host OS assertions about unsafe CPU number usage). */
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| 295 | RTCCUINTREG uFlags = ASMIntDisableFlags();
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| 296 | int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
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| 297 | if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 298 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 299 | else
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| 300 | iGipCpu = UINT16_MAX;
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| 301 | ASMSetFlags(uFlags);
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| 302 |
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| 303 | # elif defined(IN_RC)
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| 304 | /* Raw-mode context: We can get the host CPU set index via VMCPU. */
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| 305 | uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
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| 306 | if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 307 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 308 | else
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| 309 | iGipCpu = UINT16_MAX;
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[87235] | 310 |
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[54308] | 311 | #else
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| 312 | # error "IN_RING3, IN_RC or IN_RING0 must be defined!"
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| 313 | #endif
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| 314 | return iGipCpu;
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| 315 | }
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| 316 |
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| 317 |
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| 318 | /**
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| 319 | * Slow path in SUPGetTscDelta, don't call directly.
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| 320 | *
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| 321 | * @returns See SUPGetTscDelta.
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| 322 | * @param pGip The GIP.
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| 323 | * @internal
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| 324 | */
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[85213] | 325 | SUPDECL(int64_t) SUPGetTscDeltaSlow(PSUPGLOBALINFOPAGE pGip)
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[54308] | 326 | {
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| 327 | uint16_t iGipCpu = supGetGipCpuIndex(pGip);
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| 328 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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| 329 | {
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| 330 | int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
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| 331 | if (iTscDelta != INT64_MAX)
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| 332 | return iTscDelta;
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| 333 | }
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| 334 | AssertFailed();
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| 335 | return 0;
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| 336 | }
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| 337 |
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| 338 |
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| 339 | /**
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[92613] | 340 | * SLow path in SUPGetGipCpuPtr, don't call directly.
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| 341 | *
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| 342 | * @returns Pointer to the CPU entry for the caller, NULL on failure.
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| 343 | * @param pGip The GIP.
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| 344 | */
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| 345 | SUPDECL(PSUPGIPCPU) SUPGetGipCpuPtrForAsyncMode(PSUPGLOBALINFOPAGE pGip)
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| 346 | {
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| 347 | uint16_t iGipCpu = supGetGipCpuIndex(pGip);
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| 348 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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| 349 | return &pGip->aCPUs[iGipCpu];
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| 350 | AssertFailed();
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| 351 | return NULL;
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| 352 | }
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| 353 |
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| 354 |
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| 355 | /**
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[54308] | 356 | * Slow path in SUPGetCpuHzFromGip, don't call directly.
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| 357 | *
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| 358 | * @returns See SUPGetCpuHzFromGip.
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| 359 | * @param pGip The GIP.
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| 360 | * @internal
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| 361 | */
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| 362 | SUPDECL(uint64_t) SUPGetCpuHzFromGipForAsyncMode(PSUPGLOBALINFOPAGE pGip)
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| 363 | {
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| 364 | uint16_t iGipCpu = supGetGipCpuIndex(pGip);
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| 365 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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| 366 | return pGip->aCPUs[iGipCpu].u64CpuHz;
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| 367 | AssertFailed();
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| 368 | return pGip->u64CpuHz;
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| 369 | }
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| 370 |
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| 371 |
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[87235] | 372 |
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[57090] | 373 | /**
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| 374 | * Worker for SUPIsTscFreqCompatible().
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| 375 | *
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| 376 | * @returns true if it's compatible, false otherwise.
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| 377 | * @param uBaseCpuHz The reference CPU frequency of the system.
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| 378 | * @param uCpuHz The CPU frequency to compare with the base.
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| 379 | * @param fRelax Whether to use a more relaxed threshold (like
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| 380 | * for when running in a virtualized environment).
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| 381 | *
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| 382 | * @remarks Don't use directly, use SUPIsTscFreqCompatible() instead. This is
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| 383 | * to be used by tstGIP-2 or the like.
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| 384 | */
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| 385 | SUPDECL(bool) SUPIsTscFreqCompatibleEx(uint64_t uBaseCpuHz, uint64_t uCpuHz, bool fRelax)
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| 386 | {
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| 387 | if (uBaseCpuHz != uCpuHz)
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| 388 | {
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| 389 | /* Arbitrary tolerance threshold, tweak later if required, perhaps
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| 390 | more tolerance on lower frequencies and less tolerance on higher. */
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[57218] | 391 | uint16_t uFact = !fRelax ? 666 /* 0.15% */ : 125 /* 0.8% */;
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| 392 | uint64_t uThr = uBaseCpuHz / uFact;
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| 393 | uint64_t uLo = uBaseCpuHz - uThr;
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| 394 | uint64_t uHi = uBaseCpuHz + uThr;
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[57090] | 395 | if ( uCpuHz < uLo
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| 396 | || uCpuHz > uHi)
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| 397 | return false;
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| 398 | }
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| 399 | return true;
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| 400 | }
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| 401 |
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| 402 |
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| 403 | /**
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| 404 | * Checks if the provided TSC frequency is close enough to the computed TSC
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| 405 | * frequency of the host.
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| 406 | *
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| 407 | * @returns true if it's compatible, false otherwise.
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| 408 | * @param uCpuHz The TSC frequency to check.
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| 409 | * @param puGipCpuHz Where to store the GIP TSC frequency used
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| 410 | * during the compatibility test - optional.
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| 411 | * @param fRelax Whether to use a more relaxed threshold (like
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| 412 | * for when running in a virtualized environment).
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| 413 | */
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| 414 | SUPDECL(bool) SUPIsTscFreqCompatible(uint64_t uCpuHz, uint64_t *puGipCpuHz, bool fRelax)
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| 415 | {
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| 416 | PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
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[57097] | 417 | bool fCompat = false;
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| 418 | uint64_t uGipCpuHz = 0;
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[57090] | 419 | if ( pGip
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| 420 | && pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
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| 421 | {
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[57097] | 422 | uGipCpuHz = pGip->u64CpuHz;
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| 423 | fCompat = SUPIsTscFreqCompatibleEx(uGipCpuHz, uCpuHz, fRelax);
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[57090] | 424 | }
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[57097] | 425 | if (puGipCpuHz)
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| 426 | *puGipCpuHz = uGipCpuHz;
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| 427 | return fCompat;
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[57090] | 428 | }
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| 429 |
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