VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 21205

Last change on this file since 21205 was 20374, checked in by vboxsync, 15 years ago

*: s/RT_\(BEGIN|END\)_DECLS/RT_C_DECLS_\1/g
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1/* $Id: DevPit-i8254.cpp 20374 2009-06-08 00:43:21Z vboxsync $ */
2/** @file
3 * DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 * --------------------------------------------------------------------
21 *
22 * This code is based on:
23 *
24 * QEMU 8253/8254 interval timer emulation
25 *
26 * Copyright (c) 2003-2004 Fabrice Bellard
27 *
28 * Permission is hereby granted, free of charge, to any person obtaining a copy
29 * of this software and associated documentation files (the "Software"), to deal
30 * in the Software without restriction, including without limitation the rights
31 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32 * copies of the Software, and to permit persons to whom the Software is
33 * furnished to do so, subject to the following conditions:
34 *
35 * The above copyright notice and this permission notice shall be included in
36 * all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44 * THE SOFTWARE.
45 */
46
47/*******************************************************************************
48* Header Files *
49*******************************************************************************/
50#define LOG_GROUP LOG_GROUP_DEV_PIT
51#include <VBox/pdmdev.h>
52#include <VBox/log.h>
53#include <VBox/stam.h>
54#include <iprt/assert.h>
55#include <iprt/asm.h>
56
57#include "../Builtins.h"
58
59
60/*******************************************************************************
61* Defined Constants And Macros *
62*******************************************************************************/
63/** The PIT frequency. */
64#define PIT_FREQ 1193182
65
66#define RW_STATE_LSB 1
67#define RW_STATE_MSB 2
68#define RW_STATE_WORD0 3
69#define RW_STATE_WORD1 4
70
71/** The version of the saved state. */
72#define PIT_SAVED_STATE_VERSION 2
73
74/** @def FAKE_REFRESH_CLOCK
75 * Define this to flip the 15usec refresh bit on every read.
76 * If not defined, it will be flipped correctly. */
77/* #define FAKE_REFRESH_CLOCK */
78#ifdef DOXYGEN_RUNNING
79# define FAKE_REFRESH_CLOCK
80#endif
81
82
83/*******************************************************************************
84* Structures and Typedefs *
85*******************************************************************************/
86typedef struct PITChannelState
87{
88 /** Pointer to the instance data - R3 Ptr. */
89 R3PTRTYPE(struct PITState *) pPitR3;
90 /** The timer - R3 Ptr. */
91 PTMTIMERR3 pTimerR3;
92 /** Pointer to the instance data - R0 Ptr. */
93 R0PTRTYPE(struct PITState *) pPitR0;
94 /** The timer - R0 Ptr. */
95 PTMTIMERR0 pTimerR0;
96 /** Pointer to the instance data - RC Ptr. */
97 RCPTRTYPE(struct PITState *) pPitRC;
98 /** The timer - RC Ptr. */
99 PTMTIMERRC pTimerRC;
100 /** The virtual time stamp at the last reload. (only used in mode 2 for now) */
101 uint64_t u64ReloadTS;
102 /** The actual time of the next tick.
103 * As apposed to the next_transition_time which contains the correct time of the next tick. */
104 uint64_t u64NextTS;
105
106 /** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
107 uint64_t count_load_time;
108 /* irq handling */
109 int64_t next_transition_time;
110 int32_t irq;
111 /** Number of release log entries. Used to prevent floading. */
112 uint32_t cRelLogEntries;
113
114 uint32_t count; /* can be 65536 */
115 uint16_t latched_count;
116 uint8_t count_latched;
117 uint8_t status_latched;
118
119 uint8_t status;
120 uint8_t read_state;
121 uint8_t write_state;
122 uint8_t write_latch;
123
124 uint8_t rw_mode;
125 uint8_t mode;
126 uint8_t bcd; /* not supported */
127 uint8_t gate; /* timer start */
128
129} PITChannelState;
130
131typedef struct PITState
132{
133 PITChannelState channels[3];
134 /** Speaker data. */
135 int32_t speaker_data_on;
136#ifdef FAKE_REFRESH_CLOCK
137 /** Speaker dummy. */
138 int32_t dummy_refresh_clock;
139#else
140 uint32_t Alignment1;
141#endif
142 /** Pointer to the device instance. */
143 PPDMDEVINSR3 pDevIns;
144#if HC_ARCH_BITS == 32
145 uint32_t Alignment0;
146#endif
147 /** Number of IRQs that's been raised. */
148 STAMCOUNTER StatPITIrq;
149 /** Profiling the timer callback handler. */
150 STAMPROFILEADV StatPITHandler;
151} PITState;
152
153
154#ifndef VBOX_DEVICE_STRUCT_TESTCASE
155/*******************************************************************************
156* Internal Functions *
157*******************************************************************************/
158RT_C_DECLS_BEGIN
159PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
160PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
161PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
162#ifdef IN_RING3
163PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
164static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
165#endif
166RT_C_DECLS_END
167
168
169
170
171static int pit_get_count(PITChannelState *s)
172{
173 uint64_t d;
174 int counter;
175 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
176
177 if (s->mode == 2)
178 {
179 if (s->u64NextTS == UINT64_MAX)
180 {
181 d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
182 return s->count - (d % s->count); /** @todo check this value. */
183 }
184 uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
185 if (!Interval)
186 return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
187 d = TMTimerGet(pTimer);
188 d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
189 if (d >= s->count)
190 return 1;
191 return s->count - d;
192 }
193 d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
194 switch(s->mode) {
195 case 0:
196 case 1:
197 case 4:
198 case 5:
199 counter = (s->count - d) & 0xffff;
200 break;
201 case 3:
202 /* XXX: may be incorrect for odd counts */
203 counter = s->count - ((2 * d) % s->count);
204 break;
205 default:
206 counter = s->count - (d % s->count);
207 break;
208 }
209 /** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
210 return counter;
211}
212
213/* get pit output bit */
214static int pit_get_out1(PITChannelState *s, int64_t current_time)
215{
216 uint64_t d;
217 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
218 int out;
219
220 d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
221 switch(s->mode) {
222 default:
223 case 0:
224 out = (d >= s->count);
225 break;
226 case 1:
227 out = (d < s->count);
228 break;
229 case 2:
230 Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
231 if ((d % s->count) == 0 && d != 0)
232 out = 1;
233 else
234 out = 0;
235 break;
236 case 3:
237 out = (d % s->count) < ((s->count + 1) >> 1);
238 break;
239 case 4:
240 case 5:
241 out = (d == s->count);
242 break;
243 }
244 return out;
245}
246
247
248static int pit_get_out(PITState *pit, int channel, int64_t current_time)
249{
250 PITChannelState *s = &pit->channels[channel];
251 return pit_get_out1(s, current_time);
252}
253
254
255static int pit_get_gate(PITState *pit, int channel)
256{
257 PITChannelState *s = &pit->channels[channel];
258 return s->gate;
259}
260
261
262/* if already latched, do not latch again */
263static void pit_latch_count(PITChannelState *s)
264{
265 if (!s->count_latched) {
266 s->latched_count = pit_get_count(s);
267 s->count_latched = s->rw_mode;
268 LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
269 s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
270 }
271}
272
273#ifdef IN_RING3
274
275/* val must be 0 or 1 */
276static void pit_set_gate(PITState *pit, int channel, int val)
277{
278 PITChannelState *s = &pit->channels[channel];
279 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
280 Assert((val & 1) == val);
281
282 switch(s->mode) {
283 default:
284 case 0:
285 case 4:
286 /* XXX: just disable/enable counting */
287 break;
288 case 1:
289 case 5:
290 if (s->gate < val) {
291 /* restart counting on rising edge */
292 Log(("pit_set_gate: restarting mode %d\n", s->mode));
293 s->count_load_time = TMTimerGet(pTimer);
294 pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
295 }
296 break;
297 case 2:
298 case 3:
299 if (s->gate < val) {
300 /* restart counting on rising edge */
301 Log(("pit_set_gate: restarting mode %d\n", s->mode));
302 s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
303 pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
304 }
305 /* XXX: disable/enable counting */
306 break;
307 }
308 s->gate = val;
309}
310
311DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
312{
313 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
314 if (val == 0)
315 val = 0x10000;
316 s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
317 s->count = val;
318 pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
319
320 /* log the new rate (ch 0 only). */
321 if ( s->pTimerR3 /* ch 0 */
322 && s->cRelLogEntries++ < 32)
323 LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
324 s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
325 else
326 Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
327 s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
328}
329
330/* return -1 if no transition will occur. */
331static int64_t pit_get_next_transition_time(PITChannelState *s,
332 uint64_t current_time)
333{
334 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
335 uint64_t d, next_time, base;
336 uint32_t period2;
337
338 d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
339 switch(s->mode) {
340 default:
341 case 0:
342 case 1:
343 if (d < s->count)
344 next_time = s->count;
345 else
346 return -1;
347 break;
348 /*
349 * Mode 2: The period is count + 1 PIT ticks.
350 * When the counter reaches 1 we sent the output low (for channel 0 that
351 * means raise an irq). On the next tick, where we should be decrementing
352 * from 1 to 0, the count is loaded and the output goes high (channel 0
353 * means clearing the irq).
354 *
355 * In VBox we simplify the tick cycle between 1 and 0 and immediately clears
356 * the irq. We also don't set it until we reach 0, which is a tick late - will
357 * try fix that later some day.
358 */
359 case 2:
360 base = (d / s->count) * s->count;
361#ifndef VBOX /* see above */
362 if ((d - base) == 0 && d != 0)
363 next_time = base + s->count;
364 else
365#endif
366 next_time = base + s->count + 1;
367 break;
368 case 3:
369 base = (d / s->count) * s->count;
370 period2 = ((s->count + 1) >> 1);
371 if ((d - base) < period2)
372 next_time = base + period2;
373 else
374 next_time = base + s->count;
375 break;
376 case 4:
377 case 5:
378 if (d < s->count)
379 next_time = s->count;
380 else if (d == s->count)
381 next_time = s->count + 1;
382 else
383 return -1;
384 break;
385 }
386 /* convert to timer units */
387 LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
388 ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
389 next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
390 /* fix potential rounding problems */
391 /* XXX: better solution: use a clock at PIT_FREQ Hz */
392 if (next_time <= current_time)
393 next_time = current_time + 1;
394 return next_time;
395}
396
397static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
398{
399 int64_t expire_time;
400 int irq_level;
401 PPDMDEVINS pDevIns;
402 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
403
404 if (!s->CTX_SUFF(pTimer))
405 return;
406 expire_time = pit_get_next_transition_time(s, current_time);
407 irq_level = pit_get_out1(s, current_time);
408
409 /* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
410 pDevIns = s->CTX_SUFF(pPit)->pDevIns;
411 PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
412 if (irq_level)
413 PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
414 if (irq_level)
415 {
416 s->u64ReloadTS = now;
417 STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
418 }
419
420 if (expire_time != -1)
421 {
422 Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
423 s->u64NextTS = expire_time;
424 TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
425 }
426 else
427 {
428 LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
429 TMTimerStop(s->CTX_SUFF(pTimer));
430 s->u64NextTS = UINT64_MAX;
431 }
432 s->next_transition_time = expire_time;
433}
434
435#endif /* IN_RING3 */
436
437
438/**
439 * Port I/O Handler for IN operations.
440 *
441 * @returns VBox status code.
442 *
443 * @param pDevIns The device instance.
444 * @param pvUser User argument - ignored.
445 * @param Port Port number used for the IN operation.
446 * @param pu32 Where to store the result.
447 * @param cb Number of bytes read.
448 */
449PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
450{
451 Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
452 NOREF(pvUser);
453 Port &= 3;
454 if (cb != 1 || Port == 3)
455 {
456 Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
457 return VERR_IOM_IOPORT_UNUSED;
458 }
459
460 PITState *pit = PDMINS_2_DATA(pDevIns, PITState *);
461 int ret;
462 PITChannelState *s = &pit->channels[Port];
463 if (s->status_latched)
464 {
465 s->status_latched = 0;
466 ret = s->status;
467 }
468 else if (s->count_latched)
469 {
470 switch (s->count_latched)
471 {
472 default:
473 case RW_STATE_LSB:
474 ret = s->latched_count & 0xff;
475 s->count_latched = 0;
476 break;
477 case RW_STATE_MSB:
478 ret = s->latched_count >> 8;
479 s->count_latched = 0;
480 break;
481 case RW_STATE_WORD0:
482 ret = s->latched_count & 0xff;
483 s->count_latched = RW_STATE_MSB;
484 break;
485 }
486 }
487 else
488 {
489 int count;
490 switch (s->read_state)
491 {
492 default:
493 case RW_STATE_LSB:
494 count = pit_get_count(s);
495 ret = count & 0xff;
496 break;
497 case RW_STATE_MSB:
498 count = pit_get_count(s);
499 ret = (count >> 8) & 0xff;
500 break;
501 case RW_STATE_WORD0:
502 count = pit_get_count(s);
503 ret = count & 0xff;
504 s->read_state = RW_STATE_WORD1;
505 break;
506 case RW_STATE_WORD1:
507 count = pit_get_count(s);
508 ret = (count >> 8) & 0xff;
509 s->read_state = RW_STATE_WORD0;
510 break;
511 }
512 }
513
514 *pu32 = ret;
515 Log2(("pitIOPortRead: Port=%#x cb=%x *pu32=%#04x\n", Port, cb, *pu32));
516 return VINF_SUCCESS;
517}
518
519
520/**
521 * Port I/O Handler for OUT operations.
522 *
523 * @returns VBox status code.
524 *
525 * @param pDevIns The device instance.
526 * @param pvUser User argument - ignored.
527 * @param Port Port number used for the IN operation.
528 * @param u32 The value to output.
529 * @param cb The value size in bytes.
530 */
531PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
532{
533 Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
534 NOREF(pvUser);
535 if (cb != 1)
536 return VINF_SUCCESS;
537
538 PITState *pit = PDMINS_2_DATA(pDevIns, PITState *);
539 Port &= 3;
540 if (Port == 3)
541 {
542 /*
543 * Port 43h - Mode/Command Register.
544 * 7 6 5 4 3 2 1 0
545 * * * . . . . . . Select channel: 0 0 = Channel 0
546 * 0 1 = Channel 1
547 * 1 0 = Channel 2
548 * 1 1 = Read-back command (8254 only)
549 * (Illegal on 8253)
550 * (Illegal on PS/2 {JAM})
551 * . . * * . . . . Command/Access mode: 0 0 = Latch count value command
552 * 0 1 = Access mode: lobyte only
553 * 1 0 = Access mode: hibyte only
554 * 1 1 = Access mode: lobyte/hibyte
555 * . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
556 * 0 1 0 = Mode 2, 0 1 1 = Mode 3,
557 * 1 0 0 = Mode 4, 1 0 1 = Mode 5,
558 * 1 1 0 = Mode 2, 1 1 1 = Mode 3
559 * . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
560 */
561 unsigned channel = u32 >> 6;
562 if (channel == 3)
563 {
564 /* read-back command */
565 for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
566 {
567 PITChannelState *s = &pit->channels[channel];
568 if (u32 & (2 << channel)) {
569 if (!(u32 & 0x20))
570 pit_latch_count(s);
571 if (!(u32 & 0x10) && !s->status_latched)
572 {
573 /* status latch */
574 /* XXX: add BCD and null count */
575 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
576 s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
577 | (s->rw_mode << 4)
578 | (s->mode << 1)
579 | s->bcd;
580 s->status_latched = 1;
581 }
582 }
583 }
584 }
585 else
586 {
587 PITChannelState *s = &pit->channels[channel];
588 unsigned access = (u32 >> 4) & 3;
589 if (access == 0)
590 pit_latch_count(s);
591 else
592 {
593 s->rw_mode = access;
594 s->read_state = access;
595 s->write_state = access;
596
597 s->mode = (u32 >> 1) & 7;
598 s->bcd = u32 & 1;
599 /* XXX: update irq timer ? */
600 }
601 }
602 }
603 else
604 {
605#ifndef IN_RING3
606 return VINF_IOM_HC_IOPORT_WRITE;
607#else /* IN_RING3 */
608 /*
609 * Port 40-42h - Channel Data Ports.
610 */
611 PITChannelState *s = &pit->channels[Port];
612 switch(s->write_state)
613 {
614 default:
615 case RW_STATE_LSB:
616 pit_load_count(s, u32);
617 break;
618 case RW_STATE_MSB:
619 pit_load_count(s, u32 << 8);
620 break;
621 case RW_STATE_WORD0:
622 s->write_latch = u32;
623 s->write_state = RW_STATE_WORD1;
624 break;
625 case RW_STATE_WORD1:
626 pit_load_count(s, s->write_latch | (u32 << 8));
627 s->write_state = RW_STATE_WORD0;
628 break;
629 }
630#endif /* !IN_RING3 */
631 }
632 return VINF_SUCCESS;
633}
634
635
636/**
637 * Port I/O Handler for speaker IN operations.
638 *
639 * @returns VBox status code.
640 *
641 * @param pDevIns The device instance.
642 * @param pvUser User argument - ignored.
643 * @param Port Port number used for the IN operation.
644 * @param pu32 Where to store the result.
645 * @param cb Number of bytes read.
646 */
647PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
648{
649 NOREF(pvUser);
650 if (cb == 1)
651 {
652 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
653 const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
654 Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
655
656 /* bit 6,7 Parity error stuff. */
657 /* bit 5 - mirrors timer 2 output condition. */
658 const int fOut = pit_get_out(pThis, 2, u64Now);
659 /* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
660 ASSUMES ns timer freq, see assertion above. */
661#ifndef FAKE_REFRESH_CLOCK
662 const int fRefresh = (u64Now / 15085) & 1;
663#else
664 pThis->dummy_refresh_clock ^= 1;
665 const int fRefresh = pThis->dummy_refresh_clock;
666#endif
667 /* bit 2,3 NMI / parity status stuff. */
668 /* bit 1 - speaker data status */
669 const int fSpeakerStatus = pThis->speaker_data_on;
670 /* bit 0 - timer 2 clock gate to speaker status. */
671 const int fTimer2GateStatus = pit_get_gate(pThis, 2);
672
673 *pu32 = fTimer2GateStatus
674 | (fSpeakerStatus << 1)
675 | (fRefresh << 4)
676 | (fOut << 5);
677 Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=%#x\n", Port, cb, *pu32));
678 return VINF_SUCCESS;
679 }
680 Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
681 return VERR_IOM_IOPORT_UNUSED;
682}
683
684#ifdef IN_RING3
685
686/**
687 * Port I/O Handler for speaker OUT operations.
688 *
689 * @returns VBox status code.
690 *
691 * @param pDevIns The device instance.
692 * @param pvUser User argument - ignored.
693 * @param Port Port number used for the IN operation.
694 * @param u32 The value to output.
695 * @param cb The value size in bytes.
696 */
697PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
698{
699 NOREF(pvUser);
700 if (cb == 1)
701 {
702 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
703 pThis->speaker_data_on = (u32 >> 1) & 1;
704 pit_set_gate(pThis, 2, u32 & 1);
705 }
706 Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
707 return VINF_SUCCESS;
708}
709
710
711/**
712 * Saves a state of the programmable interval timer device.
713 *
714 * @returns VBox status code.
715 * @param pDevIns The device instance.
716 * @param pSSMHandle The handle to save the state to.
717 */
718static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
719{
720 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
721 unsigned i;
722
723 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
724 {
725 PITChannelState *s = &pThis->channels[i];
726 SSMR3PutU32(pSSMHandle, s->count);
727 SSMR3PutU16(pSSMHandle, s->latched_count);
728 SSMR3PutU8(pSSMHandle, s->count_latched);
729 SSMR3PutU8(pSSMHandle, s->status_latched);
730 SSMR3PutU8(pSSMHandle, s->status);
731 SSMR3PutU8(pSSMHandle, s->read_state);
732 SSMR3PutU8(pSSMHandle, s->write_state);
733 SSMR3PutU8(pSSMHandle, s->write_latch);
734 SSMR3PutU8(pSSMHandle, s->rw_mode);
735 SSMR3PutU8(pSSMHandle, s->mode);
736 SSMR3PutU8(pSSMHandle, s->bcd);
737 SSMR3PutU8(pSSMHandle, s->gate);
738 SSMR3PutU64(pSSMHandle, s->count_load_time);
739 SSMR3PutU64(pSSMHandle, s->u64NextTS);
740 SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
741 SSMR3PutS64(pSSMHandle, s->next_transition_time);
742 if (s->CTX_SUFF(pTimer))
743 TMR3TimerSave(s->CTX_SUFF(pTimer), pSSMHandle);
744 }
745
746 SSMR3PutS32(pSSMHandle, pThis->speaker_data_on);
747#ifdef FAKE_REFRESH_CLOCK
748 return SSMR3PutS32(pSSMHandle, pThis->dummy_refresh_clock);
749#else
750 return SSMR3PutS32(pSSMHandle, 0);
751#endif
752}
753
754
755/**
756 * Loads a saved programmable interval timer device state.
757 *
758 * @returns VBox status code.
759 * @param pDevIns The device instance.
760 * @param pSSMHandle The handle to the saved state.
761 * @param u32Version The data unit version number.
762 */
763static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
764{
765 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
766 unsigned i;
767
768 if (u32Version != PIT_SAVED_STATE_VERSION)
769 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
770
771 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
772 {
773 PITChannelState *s = &pThis->channels[i];
774 SSMR3GetU32(pSSMHandle, &s->count);
775 SSMR3GetU16(pSSMHandle, &s->latched_count);
776 SSMR3GetU8(pSSMHandle, &s->count_latched);
777 SSMR3GetU8(pSSMHandle, &s->status_latched);
778 SSMR3GetU8(pSSMHandle, &s->status);
779 SSMR3GetU8(pSSMHandle, &s->read_state);
780 SSMR3GetU8(pSSMHandle, &s->write_state);
781 SSMR3GetU8(pSSMHandle, &s->write_latch);
782 SSMR3GetU8(pSSMHandle, &s->rw_mode);
783 SSMR3GetU8(pSSMHandle, &s->mode);
784 SSMR3GetU8(pSSMHandle, &s->bcd);
785 SSMR3GetU8(pSSMHandle, &s->gate);
786 SSMR3GetU64(pSSMHandle, &s->count_load_time);
787 SSMR3GetU64(pSSMHandle, &s->u64NextTS);
788 SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
789 SSMR3GetS64(pSSMHandle, &s->next_transition_time);
790 if (s->CTX_SUFF(pTimer))
791 {
792 TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSMHandle);
793 LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
794 s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
795 }
796 pThis->channels[0].cRelLogEntries = 0;
797 }
798
799 SSMR3GetS32(pSSMHandle, &pThis->speaker_data_on);
800#ifdef FAKE_REFRESH_CLOCK
801 return SSMR3GetS32(pSSMHandle, &pThis->dummy_refresh_clock);
802#else
803 int32_t u32Dummy;
804 return SSMR3GetS32(pSSMHandle, &u32Dummy);
805#endif
806}
807
808
809/**
810 * Device timer callback function.
811 *
812 * @param pDevIns Device instance of the device which registered the timer.
813 * @param pTimer The timer handle.
814 * @param pvUser Pointer to the PIT channel state.
815 */
816static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
817{
818 PITChannelState *s = (PITChannelState *)pvUser;
819 STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
820 Log(("pitTimer\n"));
821 pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
822 STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
823}
824
825
826/**
827 * Relocation notification.
828 *
829 * @returns VBox status.
830 * @param pDevIns The device instance data.
831 * @param offDelta The delta relative to the old address.
832 */
833static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
834{
835 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
836 unsigned i;
837 LogFlow(("pitRelocate: \n"));
838
839 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
840 {
841 PITChannelState *pCh = &pThis->channels[i];
842 if (pCh->pTimerR3)
843 pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
844 pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
845 }
846}
847
848/** @todo remove this! */
849static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
850
851/**
852 * Reset notification.
853 *
854 * @returns VBox status.
855 * @param pDevIns The device instance data.
856 */
857static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
858{
859 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
860 unsigned i;
861 LogFlow(("pitReset: \n"));
862
863 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
864 {
865 PITChannelState *s = &pThis->channels[i];
866
867#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
868 s->latched_count = 0;
869 s->count_latched = 0;
870 s->status_latched = 0;
871 s->status = 0;
872 s->read_state = 0;
873 s->write_state = 0;
874 s->write_latch = 0;
875 s->rw_mode = 0;
876 s->bcd = 0;
877#endif
878 s->u64NextTS = UINT64_MAX;
879 s->cRelLogEntries = 0;
880 s->mode = 3;
881 s->gate = (i != 2);
882 pit_load_count(s, 0);
883 }
884}
885
886
887/**
888 * Info handler, device version.
889 *
890 * @param pDevIns Device instance which registered the info.
891 * @param pHlp Callback functions for doing output.
892 * @param pszArgs Argument string. Optional and specific to the handler.
893 */
894static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
895{
896 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
897 unsigned i;
898 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
899 {
900 const PITChannelState *pCh = &pThis->channels[i];
901
902 pHlp->pfnPrintf(pHlp,
903 "PIT (i8254) channel %d status: irq=%#x\n"
904 " count=%08x" " latched_count=%04x count_latched=%02x\n"
905 " status=%02x status_latched=%02x read_state=%02x\n"
906 " write_state=%02x write_latch=%02x rw_mode=%02x\n"
907 " mode=%02x bcd=%02x gate=%02x\n"
908 " count_load_time=%016RX64 next_transition_time=%016RX64\n"
909 " u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
910 ,
911 i, pCh->irq,
912 pCh->count, pCh->latched_count, pCh->count_latched,
913 pCh->status, pCh->status_latched, pCh->read_state,
914 pCh->write_state, pCh->write_latch, pCh->rw_mode,
915 pCh->mode, pCh->bcd, pCh->gate,
916 pCh->count_load_time, pCh->next_transition_time,
917 pCh->u64ReloadTS, pCh->u64NextTS);
918 }
919#ifdef FAKE_REFRESH_CLOCK
920 pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
921 pThis->speaker_data_on, pThis->dummy_refresh_clock);
922#else
923 pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
924#endif
925}
926
927
928/**
929 * Construct a device instance for a VM.
930 *
931 * @returns VBox status.
932 * @param pDevIns The device instance data.
933 * If the registration structure is needed, pDevIns->pDevReg points to it.
934 * @param iInstance Instance number. Use this to figure out which registers and such to use.
935 * The device number is also found in pDevIns->iInstance, but since it's
936 * likely to be freqently used PDM passes it as parameter.
937 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
938 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
939 * iInstance it's expected to be used a bit in this function.
940 */
941static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
942{
943 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
944 int rc;
945 uint8_t u8Irq;
946 uint16_t u16Base;
947 bool fSpeaker;
948 bool fGCEnabled;
949 bool fR0Enabled;
950 unsigned i;
951 Assert(iInstance == 0);
952
953 /*
954 * Validate configuration.
955 */
956 if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0" "Base\0" "Speaker\0" "GCEnabled\0" "R0Enabled\0"))
957 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
958
959 /*
960 * Init the data.
961 */
962 rc = CFGMR3QueryU8Def(pCfgHandle, "Irq", &u8Irq, 0);
963 if (RT_FAILURE(rc))
964 return PDMDEV_SET_ERROR(pDevIns, rc,
965 N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
966
967 rc = CFGMR3QueryU16Def(pCfgHandle, "Base", &u16Base, 0x40);
968 if (RT_FAILURE(rc))
969 return PDMDEV_SET_ERROR(pDevIns, rc,
970 N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
971
972 rc = CFGMR3QueryBoolDef(pCfgHandle, "SpeakerEnabled", &fSpeaker, true);
973 if (RT_FAILURE(rc))
974 return PDMDEV_SET_ERROR(pDevIns, rc,
975 N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
976
977 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
978 if (RT_FAILURE(rc))
979 return PDMDEV_SET_ERROR(pDevIns, rc,
980 N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
981
982 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
983 if (RT_FAILURE(rc))
984 return PDMDEV_SET_ERROR(pDevIns, rc,
985 N_("Configuration error: failed to read R0Enabled as boolean"));
986
987 pThis->pDevIns = pDevIns;
988 pThis->channels[0].irq = u8Irq;
989 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
990 {
991 pThis->channels[i].pPitR3 = pThis;
992 pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
993 pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
994 }
995
996 /*
997 * Create timer, register I/O Ports and save state.
998 */
999 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1000 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1001 &pThis->channels[0].pTimerR3);
1002 if (RT_FAILURE(rc))
1003 return rc;
1004 pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1005 pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1006
1007 rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1008 if (RT_FAILURE(rc))
1009 return rc;
1010 if (fGCEnabled)
1011 {
1012 rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1013 if (RT_FAILURE(rc))
1014 return rc;
1015 }
1016 if (fR0Enabled)
1017 {
1018 rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1019 if (RT_FAILURE(rc))
1020 return rc;
1021 }
1022
1023 if (fSpeaker)
1024 {
1025 rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1026 if (RT_FAILURE(rc))
1027 return rc;
1028 if (fGCEnabled)
1029 {
1030 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1031 if (RT_FAILURE(rc))
1032 return rc;
1033 }
1034 }
1035
1036 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pThis),
1037 NULL, pitSaveExec, NULL,
1038 NULL, pitLoadExec, NULL);
1039 if (RT_FAILURE(rc))
1040 return rc;
1041
1042 /*
1043 * Initialize the device state.
1044 */
1045 pitReset(pDevIns);
1046
1047 /*
1048 * Register statistics and debug info.
1049 */
1050 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1051 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1052
1053 PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1054
1055 return VINF_SUCCESS;
1056}
1057
1058
1059/**
1060 * The device registration structure.
1061 */
1062const PDMDEVREG g_DeviceI8254 =
1063{
1064 /* u32Version */
1065 PDM_DEVREG_VERSION,
1066 /* szDeviceName */
1067 "i8254",
1068 /* szRCMod */
1069 "VBoxDDGC.gc",
1070 /* szR0Mod */
1071 "VBoxDDR0.r0",
1072 /* pszDescription */
1073 "Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1074 /* fFlags */
1075 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1076 /* fClass */
1077 PDM_DEVREG_CLASS_PIT,
1078 /* cMaxInstances */
1079 1,
1080 /* cbInstance */
1081 sizeof(PITState),
1082 /* pfnConstruct */
1083 pitConstruct,
1084 /* pfnDestruct */
1085 NULL,
1086 /* pfnRelocate */
1087 pitRelocate,
1088 /* pfnIOCtl */
1089 NULL,
1090 /* pfnPowerOn */
1091 NULL,
1092 /* pfnReset */
1093 pitReset,
1094 /* pfnSuspend */
1095 NULL,
1096 /* pfnResume */
1097 NULL,
1098 /* pfnAttach */
1099 NULL,
1100 /* pfnDetach */
1101 NULL,
1102 /* pfnQueryInterface. */
1103 NULL,
1104 /* pfnInitComplete */
1105 NULL,
1106 /* pfnPowerOff */
1107 NULL,
1108 /* pfnSoftReset */
1109 NULL,
1110 /* u32VersionEnd */
1111 PDM_DEVREG_VERSION
1112};
1113
1114#endif /* IN_RING3 */
1115#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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