VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 21205

Last change on this file since 21205 was 20572, checked in by vboxsync, 15 years ago

DrvVUSBRootHub.cpp,DevPCI,DevAPIC: Don't register stats under /PDM/.
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1/* $Id: DevPIC.cpp 20572 2009-06-14 21:29:23Z vboxsync $ */
2/** @file
3 * DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_PIC
26#include <VBox/pdmdev.h>
27#include <VBox/log.h>
28#include <iprt/assert.h>
29#include <iprt/string.h>
30
31#include "../Builtins.h"
32
33
34/*******************************************************************************
35* Defined Constants And Macros *
36*******************************************************************************/
37/** @def PIC_LOCK
38 * Acquires the PDM lock. This is a NOP if locking is disabled. */
39/** @def PIC_UNLOCK
40 * Releases the PDM lock. This is a NOP if locking is disabled. */
41#define PIC_LOCK(pThis, rc) \
42 do { \
43 int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
44 if (rc2 != VINF_SUCCESS) \
45 return rc2; \
46 } while (0)
47#define PIC_UNLOCK(pThis) \
48 (pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
49
50
51#ifndef VBOX_DEVICE_STRUCT_TESTCASE
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55RT_C_DECLS_BEGIN
56
57PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
58PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
59PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
60PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
61PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
62PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
63
64RT_C_DECLS_END
65#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
66
67
68/*
69 * QEMU 8259 interrupt controller emulation
70 *
71 * Copyright (c) 2003-2004 Fabrice Bellard
72 *
73 * Permission is hereby granted, free of charge, to any person obtaining a copy
74 * of this software and associated documentation files (the "Software"), to deal
75 * in the Software without restriction, including without limitation the rights
76 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
77 * copies of the Software, and to permit persons to whom the Software is
78 * furnished to do so, subject to the following conditions:
79 *
80 * The above copyright notice and this permission notice shall be included in
81 * all copies or substantial portions of the Software.
82 *
83 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
84 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
85 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
86 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
87 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
88 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
89 * THE SOFTWARE.
90 */
91
92/* debug PIC */
93#define DEBUG_PIC
94
95/*#define DEBUG_IRQ_COUNT*/
96
97typedef struct PicState {
98 uint8_t last_irr; /* edge detection */
99 uint8_t irr; /* interrupt request register */
100 uint8_t imr; /* interrupt mask register */
101 uint8_t isr; /* interrupt service register */
102 uint8_t priority_add; /* highest irq priority */
103 uint8_t irq_base;
104 uint8_t read_reg_select;
105 uint8_t poll;
106 uint8_t special_mask;
107 uint8_t init_state;
108 uint8_t auto_eoi;
109 uint8_t rotate_on_auto_eoi;
110 uint8_t special_fully_nested_mode;
111 uint8_t init4; /* true if 4 byte init */
112 uint8_t elcr; /* PIIX edge/trigger selection*/
113 uint8_t elcr_mask;
114 /** Pointer to the device instance, R3 Ptr. */
115 PPDMDEVINSR3 pDevInsR3;
116 /** Pointer to the device instance, R0 Ptr. */
117 PPDMDEVINSR0 pDevInsR0;
118 /** Pointer to the device instance, RC Ptr. */
119 PPDMDEVINSRC pDevInsRC;
120 RTRCPTR Alignment0; /**< Structure size alignment. */
121} PicState;
122
123/**
124 * A PIC device instance data.
125 */
126typedef struct DEVPIC
127{
128 /** The two interrupt controllers. */
129 PicState aPics[2];
130 /** Pointer to the device instance - R3 Ptr. */
131 PPDMDEVINSR3 pDevInsR3;
132 /** Pointer to the PIC R3 helpers. */
133 PCPDMPICHLPR3 pPicHlpR3;
134 /** Pointer to the device instance - R0 Ptr. */
135 PPDMDEVINSR0 pDevInsR0;
136 /** Pointer to the PIC R0 helpers. */
137 PCPDMPICHLPR0 pPicHlpR0;
138 /** Pointer to the device instance - RC Ptr. */
139 PPDMDEVINSRC pDevInsRC;
140 /** Pointer to the PIC RC helpers. */
141 PCPDMPICHLPRC pPicHlpRC;
142#ifdef VBOX_WITH_STATISTICS
143 STAMCOUNTER StatSetIrqGC;
144 STAMCOUNTER StatSetIrqHC;
145 STAMCOUNTER StatClearedActiveIRQ2;
146 STAMCOUNTER StatClearedActiveMasterIRQ;
147 STAMCOUNTER StatClearedActiveSlaveIRQ;
148#endif
149} DEVPIC, *PDEVPIC;
150
151
152#ifndef VBOX_DEVICE_STRUCT_TESTCASE
153#ifdef LOG_ENABLED
154static inline void DumpPICState(PicState *s, const char *szFn)
155{
156 PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
157
158 Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
159 szFn, (&pThis->aPics[0] == s) ? 0 : 1,
160 s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
161}
162#else
163# define DumpPICState(pThis, szFn) do { } while (0)
164#endif
165
166/* set irq level. If an edge is detected, then the IRR is set to 1 */
167static inline void pic_set_irq1(PicState *s, int irq, int level)
168{
169 int mask;
170 Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
171 mask = 1 << irq;
172 if (s->elcr & mask) {
173 /* level triggered */
174 if (level) {
175 Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr | mask));
176 s->irr |= mask;
177 s->last_irr |= mask;
178 } else {
179 Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
180 s->irr &= ~mask;
181 s->last_irr &= ~mask;
182 }
183 } else {
184 /* edge triggered */
185 if (level) {
186 if ((s->last_irr & mask) == 0)
187 {
188 Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr | mask, s->last_irr));
189 s->irr |= mask;
190 }
191 s->last_irr |= mask;
192 } else {
193 s->last_irr &= ~mask;
194 }
195 }
196 DumpPICState(s, "pic_set_irq1");
197}
198
199/* return the highest priority found in mask (highest = smallest
200 number). Return 8 if no irq */
201static inline int get_priority(PicState *s, int mask)
202{
203 int priority;
204 if (mask == 0)
205 return 8;
206 priority = 0;
207 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
208 priority++;
209 return priority;
210}
211
212/* return the pic wanted interrupt. return -1 if none */
213static int pic_get_irq(PicState *s)
214{
215 PicState *pics = &(PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC))->aPics[0];
216 int mask, cur_priority, priority;
217 Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
218 DumpPICState(s, "pic_get_irq");
219
220 mask = s->irr & ~s->imr;
221 priority = get_priority(s, mask);
222 Log(("pic_get_irq: priority=%x\n", priority));
223 if (priority == 8)
224 return -1;
225 /* compute current priority. If special fully nested mode on the
226 master, the IRQ coming from the slave is not taken into account
227 for the priority computation. */
228 mask = s->isr;
229 if (s->special_fully_nested_mode && s == &pics[0])
230 mask &= ~(1 << 2);
231 cur_priority = get_priority(s, mask);
232 Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
233 if (priority < cur_priority) {
234 /* higher priority found: an irq should be generated */
235 return (priority + s->priority_add) & 7;
236 } else {
237 return -1;
238 }
239}
240
241/* raise irq to CPU if necessary. must be called every time the active
242 irq may change */
243static int pic_update_irq(PDEVPIC pThis)
244{
245 PicState *pics = &pThis->aPics[0];
246 int irq2, irq;
247
248 /* first look at slave pic */
249 irq2 = pic_get_irq(&pics[1]);
250 Log(("pic_update_irq irq2=%d\n", irq2));
251 if (irq2 >= 0) {
252 /* if irq request by slave pic, signal master PIC */
253 pic_set_irq1(&pics[0], 2, 1);
254 pic_set_irq1(&pics[0], 2, 0);
255 }
256 /* look at requested irq */
257 irq = pic_get_irq(&pics[0]);
258 if (irq >= 0)
259 {
260 /* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
261 * spurious slave interrupts in picGetInterrupt.
262 */
263 if (irq != 2 || irq2 != -1)
264 {
265#if defined(DEBUG_PIC)
266 int i;
267 for(i = 0; i < 2; i++) {
268 Log(("pic%d: imr=%x irr=%x padd=%d\n",
269 i, pics[i].imr, pics[i].irr,
270 pics[i].priority_add));
271 }
272 Log(("pic: cpu_interrupt\n"));
273#endif
274 pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
275 }
276 else
277 {
278 STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
279 Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
280 /* Clear it here, so lower priority interrupts can still be dispatched. */
281
282 /* if this was the only pending irq, then we must clear the interrupt ff flag */
283 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
284
285 /** @note Is this correct? */
286 pics[0].irr &= ~(1 << 2);
287
288 /* Call ourselves again just in case other interrupts are pending */
289 return pic_update_irq(pThis);
290 }
291 }
292 else
293 {
294 Log(("pic_update_irq: no interrupt is pending!!\n"));
295
296 /* we must clear the interrupt ff flag */
297 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
298 }
299 return VINF_SUCCESS;
300}
301
302/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
303static void pic_update_imr(PDEVPIC pThis, PicState *s, uint8_t val)
304{
305 int irq, intno;
306 PicState *pActivePIC;
307
308 /* Query the current pending irq, if any. */
309 pActivePIC = &pThis->aPics[0];
310 intno = irq = pic_get_irq(pActivePIC);
311 if (irq == 2)
312 {
313 pActivePIC = &pThis->aPics[1];
314 irq = pic_get_irq(pActivePIC);
315 intno = irq + 8;
316 }
317
318 /* Update IMR */
319 s->imr = val;
320
321 /* If an interrupt is pending and now masked, then clear the FF flag. */
322 if ( irq >= 0
323 && ((1 << irq) & ~pActivePIC->imr) == 0)
324 {
325 Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
326 pThis->aPics[0].elcr, pThis->aPics[0].last_irr, pThis->aPics[0].irr, pThis->aPics[0].imr, pThis->aPics[0].isr, pThis->aPics[0].irq_base));
327 Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
328 pThis->aPics[1].elcr, pThis->aPics[1].last_irr, pThis->aPics[1].irr, pThis->aPics[1].imr, pThis->aPics[1].isr, pThis->aPics[1].irq_base));
329
330 /* Clear pending IRQ 2 on master controller in case of slave interrupt. */
331 /** @todo Is this correct? */
332 if (intno > 7)
333 {
334 pThis->aPics[0].irr &= ~(1 << 2);
335 STAM_COUNTER_INC(&pThis->StatClearedActiveSlaveIRQ);
336 }
337 else
338 STAM_COUNTER_INC(&pThis->StatClearedActiveMasterIRQ);
339
340 Log(("pic_update_imr: clear pending interrupt %d\n", intno));
341 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
342 }
343}
344
345
346/**
347 * Set the an IRQ.
348 *
349 * @param pDevIns Device instance of the PICs.
350 * @param iIrq IRQ number to set.
351 * @param iLevel IRQ level.
352 */
353PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
354{
355 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
356 Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
357 Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
358 Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
359 AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
360
361 Log(("picSetIrq %d %d\n", iIrq, iLevel));
362 DumpPICState(&pThis->aPics[0], "picSetIrq");
363 DumpPICState(&pThis->aPics[1], "picSetIrq");
364 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
365 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
366 pic_update_irq(pThis);
367 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
368 {
369 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0);
370 pic_update_irq(pThis);
371 }
372}
373
374
375/* acknowledge interrupt 'irq' */
376static inline void pic_intack(PicState *s, int irq)
377{
378 if (s->auto_eoi) {
379 if (s->rotate_on_auto_eoi)
380 s->priority_add = (irq + 1) & 7;
381 } else {
382 s->isr |= (1 << irq);
383 }
384 /* We don't clear a level sensitive interrupt here */
385 if (!(s->elcr & (1 << irq)))
386 {
387 Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
388 s->irr &= ~(1 << irq);
389 }
390}
391
392
393/**
394 * Get a pending interrupt.
395 *
396 * @returns Pending interrupt number.
397 * @param pDevIns Device instance of the PICs.
398 */
399PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
400{
401 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
402 int irq;
403 int irq2;
404 int intno;
405
406 /* read the irq from the PIC */
407 DumpPICState(&pThis->aPics[0], "picGetInterrupt");
408 DumpPICState(&pThis->aPics[1], "picGetInterrupt");
409
410 irq = pic_get_irq(&pThis->aPics[0]);
411 if (irq >= 0)
412 {
413 pic_intack(&pThis->aPics[0], irq);
414 if (irq == 2)
415 {
416 irq2 = pic_get_irq(&pThis->aPics[1]);
417 if (irq2 >= 0) {
418 pic_intack(&pThis->aPics[1], irq2);
419 }
420 else
421 {
422 /* spurious IRQ on slave controller (impossible) */
423 AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
424 irq2 = 7;
425 }
426 intno = pThis->aPics[1].irq_base + irq2;
427 Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pThis->aPics[1].irq_base, irq2));
428 irq = irq2 + 8;
429 }
430 else {
431 intno = pThis->aPics[0].irq_base + irq;
432 Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pThis->aPics[0].irq_base, irq));
433 }
434 }
435 else
436 {
437 /* spurious IRQ on host controller (impossible) */
438 AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
439 irq = 7;
440 intno = pThis->aPics[0].irq_base + irq;
441 }
442 pic_update_irq(pThis);
443
444 Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
445
446 return intno;
447}
448
449static void pic_reset(PicState *s)
450{
451 PPDMDEVINSR3 pDevInsR3 = s->pDevInsR3;
452 PPDMDEVINSR0 pDevInsR0 = s->pDevInsR0;
453 PPDMDEVINSRC pDevInsRC = s->pDevInsRC;
454 int elcr_mask = s->elcr_mask;
455 int elcr = s->elcr;
456
457 memset(s, 0, sizeof(PicState));
458
459 s->elcr = elcr;
460 s->elcr_mask = elcr_mask;
461 s->pDevInsRC = pDevInsRC;
462 s->pDevInsR0 = pDevInsR0;
463 s->pDevInsR3 = pDevInsR3;
464}
465
466
467static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
468{
469 PicState *s = (PicState*)opaque;
470 PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
471 int rc = VINF_SUCCESS;
472 int priority, cmd, irq;
473
474 Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
475 addr &= 1;
476 if (addr == 0) {
477 if (val & 0x10) {
478 /* init */
479 pic_reset(s);
480 /* deassert a pending interrupt */
481 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
482
483 s->init_state = 1;
484 s->init4 = val & 1;
485 if (val & 0x02)
486 AssertReleaseMsgFailed(("single mode not supported"));
487 if (val & 0x08)
488 AssertReleaseMsgFailed(("level sensitive irq not supported"));
489 } else if (val & 0x08) {
490 if (val & 0x04)
491 s->poll = 1;
492 if (val & 0x02)
493 s->read_reg_select = val & 1;
494 if (val & 0x40)
495 s->special_mask = (val >> 5) & 1;
496 } else {
497 cmd = val >> 5;
498 switch(cmd) {
499 case 0:
500 case 4:
501 s->rotate_on_auto_eoi = cmd >> 2;
502 break;
503 case 1: /* end of interrupt */
504 case 5:
505 {
506 priority = get_priority(s, s->isr);
507 if (priority != 8) {
508 irq = (priority + s->priority_add) & 7;
509 Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
510 s->isr &= ~(1 << irq);
511 if (cmd == 5)
512 s->priority_add = (irq + 1) & 7;
513 rc = pic_update_irq(pThis);
514 Assert(rc == VINF_SUCCESS);
515 DumpPICState(s, "eoi");
516 }
517 break;
518 }
519 case 3:
520 {
521 irq = val & 7;
522 Log(("pic_write: EOI2 for irq %d\n", irq));
523 s->isr &= ~(1 << irq);
524 rc = pic_update_irq(pThis);
525 Assert(rc == VINF_SUCCESS);
526 DumpPICState(s, "eoi2");
527 break;
528 }
529 case 6:
530 {
531 s->priority_add = (val + 1) & 7;
532 Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, s->priority_add));
533 rc = pic_update_irq(pThis);
534 Assert(rc == VINF_SUCCESS);
535 break;
536 }
537 case 7:
538 {
539 irq = val & 7;
540 Log(("pic_write: EOI3 for irq %d\n", irq));
541 s->isr &= ~(1 << irq);
542 s->priority_add = (irq + 1) & 7;
543 rc = pic_update_irq(pThis);
544 Assert(rc == VINF_SUCCESS);
545 DumpPICState(s, "eoi3");
546 break;
547 }
548 default:
549 /* no operation */
550 break;
551 }
552 }
553 } else {
554 switch(s->init_state) {
555 case 0:
556 {
557 /* normal mode */
558 pic_update_imr(pThis, s, val);
559
560 rc = pic_update_irq(pThis);
561 Assert(rc == VINF_SUCCESS);
562 break;
563 }
564 case 1:
565 s->irq_base = val & 0xf8;
566 s->init_state = 2;
567 Log(("pic_write: set irq base to %x\n", s->irq_base));
568 break;
569 case 2:
570 if (s->init4) {
571 s->init_state = 3;
572 } else {
573 s->init_state = 0;
574 }
575 break;
576 case 3:
577 s->special_fully_nested_mode = (val >> 4) & 1;
578 s->auto_eoi = (val >> 1) & 1;
579 s->init_state = 0;
580 Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
581 break;
582 }
583 }
584 return rc;
585}
586
587
588static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
589{
590 PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
591 PicState *pics = &pThis->aPics[0];
592 int ret;
593
594 ret = pic_get_irq(s);
595 if (ret >= 0) {
596 if (addr1 >> 7) {
597 Log2(("pic_poll_read: clear slave irq (isr)\n"));
598 pics[0].isr &= ~(1 << 2);
599 pics[0].irr &= ~(1 << 2);
600 }
601 Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
602 s->irr &= ~(1 << ret);
603 s->isr &= ~(1 << ret);
604 if (addr1 >> 7 || ret != 2)
605 pic_update_irq(pThis);
606 } else {
607 ret = 0x07;
608 pic_update_irq(pThis);
609 }
610
611 return ret;
612}
613
614
615static uint32_t pic_ioport_read(void *opaque, uint32_t addr1, int *pRC)
616{
617 PicState *s = (PicState*)opaque;
618 unsigned int addr;
619 int ret;
620
621 *pRC = VINF_SUCCESS;
622
623 addr = addr1;
624 addr &= 1;
625 if (s->poll) {
626 ret = pic_poll_read(s, addr1);
627 s->poll = 0;
628 } else {
629 if (addr == 0) {
630 if (s->read_reg_select)
631 ret = s->isr;
632 else
633 ret = s->irr;
634 } else {
635 ret = s->imr;
636 }
637 }
638 Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
639 return ret;
640}
641
642
643
644/* -=-=-=-=-=- wrappers / stuff -=-=-=-=-=- */
645
646/**
647 * Port I/O Handler for IN operations.
648 *
649 * @returns VBox status code.
650 *
651 * @param pDevIns The device instance.
652 * @param pvUser User argument - pointer to the PIC in question.
653 * @param uPort Port number used for the IN operation.
654 * @param pu32 Where to store the result.
655 * @param cb Number of bytes read.
656 */
657PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
658{
659 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
660 uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
661
662 Assert(iPic == 0 || iPic == 1);
663 if (cb == 1)
664 {
665 int rc;
666 PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_READ);
667 *pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
668 PIC_UNLOCK(pThis);
669 return rc;
670 }
671 return VERR_IOM_IOPORT_UNUSED;
672}
673
674/**
675 * Port I/O Handler for OUT operations.
676 *
677 * @returns VBox status code.
678 *
679 * @param pDevIns The device instance.
680 * @param pvUser User argument - pointer to the PIC in question.
681 * @param uPort Port number used for the IN operation.
682 * @param u32 The value to output.
683 * @param cb The value size in bytes.
684 */
685PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
686{
687 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
688 uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
689
690 Assert(iPic == 0 || iPic == 1);
691
692 if (cb == 1)
693 {
694 int rc;
695 PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_WRITE);
696 rc = pic_ioport_write(&pThis->aPics[iPic], Port, u32);
697 PIC_UNLOCK(pThis);
698 return rc;
699 }
700 return VINF_SUCCESS;
701}
702
703
704/**
705 * Port I/O Handler for IN operations.
706 *
707 * @returns VBox status code.
708 *
709 * @param pDevIns The device instance.
710 * @param pvUser User argument - pointer to the PIC in question.
711 * @param uPort Port number used for the IN operation.
712 * @param pu32 Where to store the result.
713 * @param cb Number of bytes read.
714 */
715PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
716{
717 if (cb == 1)
718 {
719 PicState *s = (PicState*)pvUser;
720 PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
721 *pu32 = s->elcr;
722 PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
723 return VINF_SUCCESS;
724 }
725 return VERR_IOM_IOPORT_UNUSED;
726}
727
728/**
729 * Port I/O Handler for OUT operations.
730 *
731 * @returns VBox status code.
732 *
733 * @param pDevIns The device instance.
734 * @param pvUser User argument - pointer to the PIC in question.
735 * @param uPort Port number used for the IN operation.
736 * @param u32 The value to output.
737 * @param cb The value size in bytes.
738 */
739PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
740{
741 if (cb == 1)
742 {
743 PicState *s = (PicState*)pvUser;
744 PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
745 s->elcr = u32 & s->elcr_mask;
746 PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
747 }
748 return VINF_SUCCESS;
749}
750
751
752#ifdef IN_RING3
753
754#ifdef DEBUG
755/**
756 * PIC status info callback.
757 *
758 * @param pDevIns The device instance.
759 * @param pHlp The output helpers.
760 * @param pszArgs The arguments.
761 */
762static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
763{
764 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
765
766 /*
767 * Show info.
768 */
769 for (int i=0;i<2;i++)
770 {
771 pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
772 pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pThis->aPics[i].last_irr);
773 pHlp->pfnPrintf(pHlp, " irr = %02x\n", pThis->aPics[i].irr);
774 pHlp->pfnPrintf(pHlp, " imr = %02x\n", pThis->aPics[i].imr);
775 pHlp->pfnPrintf(pHlp, " isr = %02x\n", pThis->aPics[i].isr);
776 pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pThis->aPics[i].priority_add);
777 pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pThis->aPics[i].irq_base);
778 pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pThis->aPics[i].read_reg_select);
779 pHlp->pfnPrintf(pHlp, " poll = %02x\n", pThis->aPics[i].poll);
780 pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pThis->aPics[i].special_mask);
781 pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pThis->aPics[i].init_state);
782 pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pThis->aPics[i].auto_eoi);
783 pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pThis->aPics[i].rotate_on_auto_eoi);
784 pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pThis->aPics[i].special_fully_nested_mode);
785 pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pThis->aPics[i].init4);
786 pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pThis->aPics[i].elcr);
787 pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pThis->aPics[i].elcr_mask);
788 }
789}
790#endif /* DEBUG */
791
792/**
793 * Saves a state of the programmable interrupt controller device.
794 *
795 * @returns VBox status code.
796 * @param pDevIns The device instance.
797 * @param pSSMHandle The handle to save the state to.
798 */
799static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
800{
801 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
802 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
803 {
804 SSMR3PutU8(pSSMHandle, pThis->aPics[i].last_irr);
805 SSMR3PutU8(pSSMHandle, pThis->aPics[i].irr);
806 SSMR3PutU8(pSSMHandle, pThis->aPics[i].imr);
807 SSMR3PutU8(pSSMHandle, pThis->aPics[i].isr);
808 SSMR3PutU8(pSSMHandle, pThis->aPics[i].priority_add);
809 SSMR3PutU8(pSSMHandle, pThis->aPics[i].irq_base);
810 SSMR3PutU8(pSSMHandle, pThis->aPics[i].read_reg_select);
811 SSMR3PutU8(pSSMHandle, pThis->aPics[i].poll);
812 SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_mask);
813 SSMR3PutU8(pSSMHandle, pThis->aPics[i].init_state);
814 SSMR3PutU8(pSSMHandle, pThis->aPics[i].auto_eoi);
815 SSMR3PutU8(pSSMHandle, pThis->aPics[i].rotate_on_auto_eoi);
816 SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_fully_nested_mode);
817 SSMR3PutU8(pSSMHandle, pThis->aPics[i].init4);
818 SSMR3PutU8(pSSMHandle, pThis->aPics[i].elcr);
819 }
820 return VINF_SUCCESS;
821}
822
823
824/**
825 * Loads a saved programmable interrupt controller device state.
826 *
827 * @returns VBox status code.
828 * @param pDevIns The device instance.
829 * @param pSSMHandle The handle to the saved state.
830 * @param u32Version The data unit version number.
831 */
832static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
833{
834 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
835
836 if (u32Version != 1)
837 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
838
839 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
840 {
841 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].last_irr);
842 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irr);
843 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].imr);
844 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].isr);
845 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].priority_add);
846 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irq_base);
847 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].read_reg_select);
848 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].poll);
849 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_mask);
850 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init_state);
851 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].auto_eoi);
852 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].rotate_on_auto_eoi);
853 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_fully_nested_mode);
854 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init4);
855 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].elcr);
856 }
857 return VINF_SUCCESS;
858}
859
860
861/* -=-=-=-=-=- real code -=-=-=-=-=- */
862
863/**
864 * Reset notification.
865 *
866 * @returns VBox status.
867 * @param pDevIns The device instance data.
868 */
869static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
870{
871 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
872 unsigned i;
873 LogFlow(("picReset:\n"));
874 pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
875
876 for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
877 pic_reset(&pThis->aPics[i]);
878
879 PIC_UNLOCK(pThis);
880}
881
882
883/**
884 * @copydoc FNPDMDEVRELOCATE
885 */
886static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
887{
888 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
889 unsigned i;
890
891 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
892 pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
893 for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
894 pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
895}
896
897
898/**
899 * @copydoc FNPDMDEVCONSTRUCT
900 */
901static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
902{
903 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
904 PDMPICREG PicReg;
905 int rc;
906 bool fGCEnabled;
907 bool fR0Enabled;
908 Assert(iInstance == 0);
909
910 /*
911 * Validate and read configuration.
912 */
913 if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
914 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
915
916 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
917 if (RT_FAILURE(rc))
918 return PDMDEV_SET_ERROR(pDevIns, rc,
919 N_("Configuration error: failed to read GCEnabled as boolean"));
920
921 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
922 if (RT_FAILURE(rc))
923 return PDMDEV_SET_ERROR(pDevIns, rc,
924 N_("Configuration error: failed to read R0Enabled as boolean"));
925
926 Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
927
928 /*
929 * Init the data.
930 */
931 Assert(RT_ELEMENTS(pThis->aPics) == 2);
932 pThis->pDevInsR3 = pDevIns;
933 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
934 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
935 pThis->aPics[0].elcr_mask = 0xf8;
936 pThis->aPics[1].elcr_mask = 0xde;
937 pThis->aPics[0].pDevInsR3 = pDevIns;
938 pThis->aPics[1].pDevInsR3 = pDevIns;
939 pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
940 pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
941 pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
942 pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
943
944 /*
945 * Register us as the PIC with PDM.
946 */
947 PicReg.u32Version = PDM_PICREG_VERSION;
948 PicReg.pfnSetIrqR3 = picSetIrq;
949 PicReg.pfnGetInterruptR3 = picGetInterrupt;
950
951 if (fGCEnabled)
952 {
953 PicReg.pszSetIrqRC = "picSetIrq";
954 PicReg.pszGetInterruptRC = "picGetInterrupt";
955 }
956 else
957 {
958 PicReg.pszSetIrqRC = NULL;
959 PicReg.pszGetInterruptRC = NULL;
960 }
961
962 if (fR0Enabled)
963 {
964 PicReg.pszSetIrqR0 = "picSetIrq";
965 PicReg.pszGetInterruptR0 = "picGetInterrupt";
966 }
967 else
968 {
969 PicReg.pszSetIrqR0 = NULL;
970 PicReg.pszGetInterruptR0 = NULL;
971 }
972
973 Assert(pDevIns->pDevHlpR3->pfnPICRegister);
974 rc = pDevIns->pDevHlpR3->pfnPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
975 AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Rrc\n", rc), rc);
976 if (fGCEnabled)
977 pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
978 if (fR0Enabled)
979 pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
980
981
982 /*
983 * Register I/O ports and save state.
984 */
985 rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
986 if (RT_FAILURE(rc))
987 return rc;
988 rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
989 if (RT_FAILURE(rc))
990 return rc;
991 if (fGCEnabled)
992 {
993 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
994 if (RT_FAILURE(rc))
995 return rc;
996 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
997 if (RT_FAILURE(rc))
998 return rc;
999 }
1000 if (fR0Enabled)
1001 {
1002 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1003 if (RT_FAILURE(rc))
1004 return rc;
1005 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1006 if (RT_FAILURE(rc))
1007 return rc;
1008 }
1009
1010 rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
1011 picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1012 if (RT_FAILURE(rc))
1013 return rc;
1014 rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
1015 picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1016 if (RT_FAILURE(rc))
1017 return rc;
1018 if (fGCEnabled)
1019 {
1020 RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
1021 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
1022 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1023 if (RT_FAILURE(rc))
1024 return rc;
1025 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
1026 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1027 if (RT_FAILURE(rc))
1028 return rc;
1029 }
1030 if (fR0Enabled)
1031 {
1032 RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1033 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1034 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1035 if (RT_FAILURE(rc))
1036 return rc;
1037 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1038 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1039 if (RT_FAILURE(rc))
1040 return rc;
1041 }
1042
1043 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */, sizeof(*pThis),
1044 NULL, picSaveExec, NULL,
1045 NULL, picLoadExec, NULL);
1046 if (RT_FAILURE(rc))
1047 return rc;
1048
1049
1050#ifdef DEBUG
1051 /*
1052 * Register the info item.
1053 */
1054 PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1055#endif
1056
1057 /*
1058 * Initialize the device state.
1059 */
1060 picReset(pDevIns);
1061
1062#ifdef VBOX_WITH_STATISTICS
1063 /*
1064 * Statistics.
1065 */
1066 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1067 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1068
1069 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1070 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1071 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1072#endif
1073
1074 return VINF_SUCCESS;
1075}
1076
1077
1078/**
1079 * The device registration structure.
1080 */
1081const PDMDEVREG g_DeviceI8259 =
1082{
1083 /* u32Version */
1084 PDM_DEVREG_VERSION,
1085 /* szDeviceName */
1086 "i8259",
1087 /* szRCMod */
1088 "VBoxDDGC.gc",
1089 /* szR0Mod */
1090 "VBoxDDR0.r0",
1091 /* pszDescription */
1092 "Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1093 /* fFlags */
1094 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1095 /* fClass */
1096 PDM_DEVREG_CLASS_PIC,
1097 /* cMaxInstances */
1098 1,
1099 /* cbInstance */
1100 sizeof(DEVPIC),
1101 /* pfnConstruct */
1102 picConstruct,
1103 /* pfnDestruct */
1104 NULL,
1105 /* pfnRelocate */
1106 picRelocate,
1107 /* pfnIOCtl */
1108 NULL,
1109 /* pfnPowerOn */
1110 NULL,
1111 /* pfnReset */
1112 picReset,
1113 /* pfnSuspend */
1114 NULL,
1115 /* pfnResume */
1116 NULL,
1117 /* pfnAttach */
1118 NULL,
1119 /* pfnDetach */
1120 NULL,
1121 /* pfnQueryInterface. */
1122 NULL,
1123 /* pfnInitComplete */
1124 NULL,
1125 /* pfnPowerOff */
1126 NULL,
1127 /* pfnSoftReset */
1128 NULL,
1129 /* u32VersionEnd */
1130 PDM_DEVREG_VERSION
1131};
1132
1133#endif /* IN_RING3 */
1134#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1135
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