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pcibios.inc@ 93115

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1	; $Id: pcibios.inc 93115 2022-01-01 11:31:46Z vboxsync $
2	;; @file
3	; ???
4	;
5
6	;
7	; Copyright (C) 2006-2022 Oracle Corporation
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	; --------------------------------------------------------------------
17	;
18	; This code is based on:
19	;
20	; ROM BIOS for use with Bochs/Plex86/QEMU emulation environment
21	;
22	; Copyright (C) 2002 MandrakeSoft S.A.
23	;
24	; MandrakeSoft S.A.
25	; 43, rue d'Aboukir
26	; 75002 Paris - France
27	; http://www.linux-mandrake.com/
28	; http://www.mandrakesoft.com/
29	;
30	; This library is free software; you can redistribute it and/or
31	; modify it under the terms of the GNU Lesser General Public
32	; License as published by the Free Software Foundation; either
33	; version 2 of the License, or (at your option) any later version.
34	;
35	; This library is distributed in the hope that it will be useful,
36	; but WITHOUT ANY WARRANTY; without even the implied warranty of
37	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
38	; Lesser General Public License for more details.
39	;
40	; You should have received a copy of the GNU Lesser General Public
41	; License along with this library; if not, write to the Free Software
42	; Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
43	;
44
45	; Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
46	; other than GPL or LGPL is available it will apply instead, Oracle elects to use only
47	; the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
48	; a choice of LGPL license versions is made available with the language indicating
49	; that LGPLv2 or any later version may be used, or where a choice of which version
50	; of the LGPL is applied is otherwise unspecified.
51
52
53	include pcicfg.inc
54
55	if BX_PCIBIOS
56
57	ifdef DEBUG
58
59	; Publics for easier debugging and disassembly
60
61	public pcibios_init_iomem_bases
62	public pci_init_io_loop1
63	public pci_init_io_loop2
64	public init_io_base
65	public next_pci_base
66	public enable_iomem_space
67	public next_pci_dev
68	public pcibios_init_set_elcr
69	public is_master_pic
70	public pcibios_init_irqs
71	public pci_init_irq_loop1
72	public pci_init_irq_loop2
73	public pci_test_int_pin
74	public pirq_found
75	public next_pci_func
76	public next_pir_entry
77	public pci_init_end
78
79	endif
80
81	.386
82
83	if not BX_ROMBIOS32
84	pci_irq_list:
85	db 11, 10, 9, 11
86
87	pcibios_init_sel_reg:
88	push eax
89	mov eax, 800000h
90	mov ax, bx
91	shl eax, 8
92	and dl, 0FCh
93	or al, dl
94	mov dx, PCI_CFG1
95	out dx, eax
96	pop eax
97	ret
98
99	pcibios_init_iomem_bases:
100	push bp
101	mov bp, sp
102	ifdef VBOX
103	mov eax,19200509
104	mov dx,410h
105	out dx, eax
106	else
107	; This incomplete PCI resource setup code is less functional than the PCI
108	; resource assignment created by the fake PCI BIOS and is therefore disabled.
109	; Blindly enabling everything on the root bus (including bus mastering!) can
110	; only be called buggy. It causes the trouble with AMD PCNet which it then
111	; tries to work around, but that still contains a race.
112	mov eax, 0E0000000h ; base for memory init
113	push eax
114	mov ax, 0D000h ; base for i/o init
115	push ax
116	mov ax, 010h ; start at base address #0
117	push ax
118	mov bx, 8
119	pci_init_io_loop1:
120	mov dl, 0
121	call pcibios_init_sel_reg
122	mov dx, PCI_CFG2
123	in ax, dx
124	cmp ax, 0FFFFh
125	jz next_pci_dev
126
127	ifndef VBOX ; This currently breaks restoring a previously saved state.
128	mov dl, 4 ; disable i/o and memory space access
129	call pcibios_init_sel_reg
130	mov dx, PCI_CFG2
131	in al, dx
132	and al, 0FCh
133	out dx, al
134	pci_init_io_loop2:
135	mov dl, [bp-8]
136	call pcibios_init_sel_reg
137	mov dx, PCI_CFG2
138	in eax, dx
139	test al, 1
140	jnz init_io_base
141
142	mov ecx, eax
143	mov eax, 0FFFFFFFFh
144	out dx, eax
145	in eax, dx
146	cmp eax, ecx
147	je next_pci_base
148	xor eax, 0FFFFFFFFh
149	mov ecx, eax
150	mov eax, [bp-4]
151	out dx, eax
152	add eax, ecx ; calculate next free mem base
153	add eax, 01000000h
154	and eax, 0FF000000h
155	mov [bp-4], eax
156	jmp next_pci_base
157
158	init_io_base:
159	mov cx, ax
160	mov ax, 0FFFFh
161	out dx, eax
162	in eax, dx
163	cmp ax, cx
164	je next_pci_base
165
166	xor ax, 0FFFEh
167	mov cx, ax
168	mov ax, [bp-6]
169	out dx, eax
170	add ax, cx ; calculate next free i/o base
171	add ax, 00100h
172	and ax, 0FF00h
173	mov [bp-6], ax
174	next_pci_base:
175	mov al, [bp-8]
176	add al, 4
177	cmp al, 28h
178	je enable_iomem_space
179
180	mov byte ptr[bp-8], al
181	jmp pci_init_io_loop2
182	endif ; !VBOX
183
184	enable_iomem_space:
185	mov dl, 4 ;; enable i/o and memory space access if available
186	call pcibios_init_sel_reg
187	mov dx, PCI_CFG2
188	in al, dx
189	or al, 7
190	out dx, al
191	ifdef VBOX
192	mov dl, 0 ; check if PCI device is AMD PCNet
193	call pcibios_init_sel_reg
194	mov dx, PCI_CFG2
195	in eax, dx
196	cmp eax, 020001022h
197	jne next_pci_dev
198
199	mov dl, 10h ; get I/O address
200	call pcibios_init_sel_reg
201	mov dx, PCI_CFG2
202	in ax, dx
203	and ax, 0FFFCh
204	mov cx, ax
205	mov dx, cx
206	add dx, 14h ; reset register if PCNet is in word I/O mode
207	in ax, dx ; reset is performed by reading the reset register
208	mov dx, cx
209	add dx, 18h ; reset register if PCNet is in word I/O mode
210	in eax, dx ; reset is performed by reading the reset register
211	endif ; VBOX
212	next_pci_dev:
213	mov byte ptr[bp-8], 10h
214	inc bx
215	cmp bx, 0100h
216	jne pci_init_io_loop1
217	endif ; !VBOX
218	mov sp, bp
219	pop bp
220	ret
221
222	pcibios_init_set_elcr:
223	push ax
224	push cx
225	mov dx, 04D0h
226	test al, 8
227	jz is_master_pic
228
229	inc dx
230	and al, 7
231	is_master_pic:
232	mov cl, al
233	mov bl, 1
234	shl bl, cl
235	in al, dx
236	or al, bl
237	out dx, al
238	pop cx
239	pop ax
240	ret
241
242	pcibios_init_irqs:
243	push ds
244	push bp
245	mov ax, 0F000h
246	mov ds, ax
247	ifndef VBOX
248	; this code works OK, but it's unnecessary effort since the fake PCI BIOS
249	; already configured the IRQ lines and the ELCR correctly
250	mov dx, 04D0h ;; reset ELCR1 + ELCR2
251	mov al, 0
252	out dx, al
253	inc dx
254	out dx, al
255	mov si, pci_routing_table_structure
256	mov bh, [si+8]
257	mov bl, [si+9]
258	mov dl, 0
259	call pcibios_init_sel_reg
260	mov dx, PCI_CFG2
261	in eax, dx
262	cmp eax, [si+12] ;; check irq router
263	jne pci_init_end
264
265	mov dl, [si+34]
266	call pcibios_init_sel_reg
267	push bx ;; save irq router bus + devfunc
268	mov dx, PCI_CFG2
269	mov ax, 8080h
270	out dx, ax ;; reset PIRQ route control
271	add dx, 2
272	out dx, ax
273	mov ax, [si+6]
274	sub ax, 20h
275	shr ax, 4
276	mov cx, ax
277	add si, 20h ;; set pointer to 1st entry
278	mov bp, sp
279	mov ax, pci_irq_list
280	push ax
281	xor ax, ax
282	push ax
283	pci_init_irq_loop1:
284	mov bh, [si]
285	mov bl, [si+1]
286	pci_init_irq_loop2:
287	mov dl, 0
288	call pcibios_init_sel_reg
289	mov dx, PCI_CFG2
290	in ax, dx
291	cmp ax, 0FFFFh
292	jnz pci_test_int_pin
293
294	test bl, 7
295	jz next_pir_entry
296
297	jmp next_pci_func
298
299	pci_test_int_pin:
300	mov dl, 3Ch
301	call pcibios_init_sel_reg
302	mov dx, PCI_CFG2 + 1 ; access config space at 3Dh
303	in al, dx
304	and al, 7
305	jz next_pci_func
306
307	dec al ;; determine pirq reg
308	mov dl, 3
309	mul dl
310	add al, 2
311	xor ah, ah
312	mov bx, ax
313	mov al, [si+bx]
314	mov dl, al
315	mov bx, [bp]
316	call pcibios_init_sel_reg
317	mov dx, PCI_CFG2
318	and al, 3
319	add dl, al
320	in al, dx
321	cmp al, 80h
322	jb pirq_found
323
324	mov bx, [bp-2] ;; pci irq list pointer
325	mov al, [bx]
326	out dx, al
327	inc bx
328	mov [bp-2], bx
329	call pcibios_init_set_elcr
330	pirq_found:
331	mov bh, [si]
332	mov bl, [si+1]
333	add bl, [bp-3] ;; pci function number
334	mov dl, 3Ch
335	call pcibios_init_sel_reg
336	mov dx, PCI_CFG2
337	out dx, al
338	next_pci_func:
339	inc byte ptr[bp-3]
340	inc bl
341	test bl, 7
342	jnz pci_init_irq_loop2
343
344	next_pir_entry:
345	add si, 10h
346	mov byte ptr[bp-3], 0
347	loop pci_init_irq_loop1
348
349	mov sp, bp
350	pop bx
351	pci_init_end:
352	endif
353	pop bp
354	pop ds
355	ret
356
357	endif ; !BX_ROMBIOS32
358
359	endif ; BX_PCIBIOS
360
361	SET_DEFAULT_CPU_286
362

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