| 1 | /* $Id: pcibios.c 98103 2023-01-17 14:15:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * PCI BIOS support.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2004-2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | #include <stdint.h>
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| 29 | #include <string.h>
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| 30 | #include "biosint.h"
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| 31 | #include "inlines.h"
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| 32 |
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| 33 | #if DEBUG_PCI
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| 34 | # define BX_DEBUG_PCI(...) BX_DEBUG(__VA_ARGS__)
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| 35 | #else
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| 36 | # define BX_DEBUG_PCI(...)
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| 37 | #endif
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| 38 |
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| 39 | /* PCI function codes. */
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| 40 | enum pci_func {
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| 41 | PCI_BIOS_PRESENT = 0x01, /* PCI BIOS presence check. */
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| 42 | FIND_PCI_DEVICE = 0x02, /* Find PCI device by ID. */
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| 43 | FIND_PCI_CLASS_CODE = 0x03, /* Find PCI device by class. */
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| 44 | GEN_SPECIAL_CYCLE = 0x06, /* Generate special cycle. */
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| 45 | READ_CONFIG_BYTE = 0x08, /* Read a byte from PCI config space. */
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| 46 | READ_CONFIG_WORD = 0x09, /* Read a word from PCI config space. */
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| 47 | READ_CONFIG_DWORD = 0x0A, /* Read a dword from PCI config space. */
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| 48 | WRITE_CONFIG_BYTE = 0x0B, /* Write a byte to PCI config space. */
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| 49 | WRITE_CONFIG_WORD = 0x0C, /* Write a word to PCI config space. */
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| 50 | WRITE_CONFIG_DWORD = 0x0D, /* Write a dword to PCI config space. */
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| 51 | GET_IRQ_ROUTING = 0x0E, /* Get IRQ routing table. */
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| 52 | SET_PCI_HW_INT = 0x0F, /* Set PCI hardware interrupt. */
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| 53 | };
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| 54 |
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| 55 | enum pci_error {
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| 56 | SUCCESSFUL = 0x00, /* Success. */
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| 57 | FUNC_NOT_SUPPORTED = 0x81, /* Unsupported function. */
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| 58 | BAD_VENDOR_ID = 0x83, /* Bad vendor ID (all bits set) passed. */
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| 59 | DEVICE_NOT_FOUND = 0x86, /* No matching device found. */
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| 60 | BAD_REGISTER_NUMBER = 0x87, /* Register number out of range. */
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| 61 | SET_FAILED = 0x88, /* Failed to set PCI interrupt. */
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| 62 | BUFFER_TOO_SMALL = 0x89 /* Routing table buffer insufficient. */
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| 63 | };
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| 64 |
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| 65 | /// @todo merge with system.c
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| 66 | #define AX r.gr.u.r16.ax
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| 67 | #define BX r.gr.u.r16.bx
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| 68 | #define CX r.gr.u.r16.cx
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| 69 | #define DX r.gr.u.r16.dx
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| 70 | #define SI r.gr.u.r16.si
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| 71 | #define DI r.gr.u.r16.di
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| 72 | #define BP r.gr.u.r16.bp
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| 73 | #define SP r.gr.u.r16.sp
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| 74 | #define EAX r.gr.u.r32.eax
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| 75 | #define EBX r.gr.u.r32.ebx
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| 76 | #define ECX r.gr.u.r32.ecx
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| 77 | #define EDX r.gr.u.r32.edx
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| 78 | #define ES r.es
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| 79 |
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| 80 | /* The 16-bit PCI BIOS service must be callable from both real and protected
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| 81 | * mode. In protected mode, the caller must set the CS selector base to F0000h
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| 82 | * (but the CS selector value is not specified!). The caller does not always
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| 83 | * provide a DS which covers the BIOS segment.
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| 84 | *
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| 85 | * Unlike APM, there are no provisions for the 32-bit PCI BIOS interface
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| 86 | * calling the 16-bit implementation.
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| 87 | *
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| 88 | * The PCI Firmware Specification requires that the PCI BIOS service is called
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| 89 | * with at least 1,024 bytes of stack space available, that interrupts are not
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| 90 | * enabled during execution, and that the routines are re-entrant.
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| 91 | *
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| 92 | * Implementation notes:
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| 93 | * - The PCI BIOS interface already uses certain 32-bit registers even in
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| 94 | * 16-bit mode. To simplify matters, all 32-bit GPRs are saved/restored and
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| 95 | * may be used by helper routines (notably for 32-bit port I/O).
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| 96 | */
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| 97 |
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| 98 | #define PCI_CFG_ADDR 0xCF8
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| 99 | #define PCI_CFG_DATA 0xCFC
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| 100 |
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| 101 | #ifdef __386__
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| 102 |
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| 103 | #define PCIxx(x) pci32_##x
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| 104 |
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| 105 | /* The stack layout is different in 32-bit mode. */
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| 106 | typedef struct {
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| 107 | pushad_regs_t gr;
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| 108 | uint32_t es;
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| 109 | uint32_t flags;
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| 110 | } pci_regs_t;
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| 111 |
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| 112 | #define FLAGS r.flags
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| 113 |
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| 114 | /* In 32-bit mode, don't do any output; not technically impossible but needs
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| 115 | * a lot of extra code.
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| 116 | */
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| 117 | #undef BX_INFO
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| 118 | #define BX_INFO(...)
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| 119 | #undef BX_DEBUG_PCI
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| 120 | #define BX_DEBUG_PCI(...)
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| 121 |
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| 122 | #else
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| 123 |
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| 124 | #define PCIxx(x) pci16_##x
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| 125 |
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| 126 | typedef struct {
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| 127 | pushad_regs_t gr;
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| 128 | uint16_t ds;
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| 129 | uint16_t es;
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| 130 | iret_addr_t ra;
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| 131 | } pci_regs_t;
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| 132 |
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| 133 | #define FLAGS r.ra.flags.u.r16.flags
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| 134 |
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| 135 | #endif
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| 136 |
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| 137 | #ifdef __386__
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| 138 |
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| 139 | /* 32-bit code can just use the compiler intrinsics. */
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| 140 | extern unsigned inpd(unsigned port);
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| 141 | extern unsigned outpd(unsigned port, unsigned value);
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| 142 | #pragma intrinsic(inpd,outpd)
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| 143 |
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| 144 | #else
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| 145 |
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| 146 | /// @todo merge with AHCI code
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| 147 |
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| 148 | /* Warning: Destroys high bits of EAX. */
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| 149 | uint32_t inpd(uint16_t port);
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| 150 | #pragma aux inpd = \
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| 151 | ".386" \
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| 152 | "in eax, dx" \
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| 153 | "mov dx, ax" \
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| 154 | "shr eax, 16" \
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| 155 | "xchg ax, dx" \
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| 156 | parm [dx] value [dx ax] modify nomemory;
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| 157 |
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| 158 | /* Warning: Destroys high bits of EAX. */
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| 159 | void outpd(uint16_t port, uint32_t val);
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| 160 | #pragma aux outpd = \
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| 161 | ".386" \
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| 162 | "xchg ax, cx" \
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| 163 | "shl eax, 16" \
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| 164 | "mov ax, cx" \
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| 165 | "out dx, eax" \
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| 166 | parm [dx] [cx ax] modify nomemory;
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| 167 |
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| 168 | #endif
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| 169 |
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| 170 | /* PCI IRQ routing expansion buffer descriptor. */
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| 171 | typedef struct {
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| 172 | uint16_t buf_size;
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| 173 | uint8_t __far *buf_ptr;
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| 174 | } pci_route_buf;
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| 175 |
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| 176 | /* Defined in assembler module .*/
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| 177 | extern char pci_routing_table[];
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| 178 | extern uint16_t pci_routing_table_size;
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| 179 |
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| 180 | /* Write the CONFIG_ADDRESS register to prepare for data access. Requires
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| 181 | * the register offset to be DWORD aligned (low two bits clear). Warning:
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| 182 | * destroys high bits of EAX.
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| 183 | */
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| 184 | void pci16_w_addr(uint16_t bus_dev_fn, uint16_t ofs, uint16_t cfg_addr);
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| 185 | #pragma aux pci16_w_addr = \
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| 186 | ".386" \
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| 187 | "movzx eax, ax" \
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| 188 | "shl eax, 8" \
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| 189 | "or eax, 80000000h" \
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| 190 | "mov al, bl" \
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| 191 | "out dx, eax" \
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| 192 | parm [ax] [bx] [dx] modify exact [ax] nomemory;
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| 193 |
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| 194 |
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| 195 | /* Select a PCI configuration register given its offset and bus/dev/fn.
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| 196 | * This is largely a wrapper to avoid excessive inlining.
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| 197 | */
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| 198 | void PCIxx(select_reg)(uint16_t bus_dev_fn, uint16_t ofs)
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| 199 | {
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| 200 | pci16_w_addr(bus_dev_fn, ofs & ~3, PCI_CFG_ADDR);
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| 201 | }
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| 202 |
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| 203 | /* Selected configuration space offsets. */
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| 204 | #define PCI_VEN_ID 0x00
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| 205 | #define PCI_DEV_ID 0x02
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| 206 | #define PCI_REV_ID 0x08
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| 207 | #define PCI_CLASS_CODE 0x09
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| 208 | #define PCI_HEADER_TYPE 0x0E
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| 209 | #define PCI_BRIDGE_SUBORD 0x1A
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| 210 |
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| 211 | /* To avoid problems with 16-bit code, we reserve the last possible
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| 212 | * bus/dev/fn combination (65,535). Upon reaching this location, the
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| 213 | * probing will end.
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| 214 | */
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| 215 | #define BUSDEVFN_NOT_FOUND 0xFFFF
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| 216 |
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| 217 | /* In the search algorithm, we decrement the device index every time
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| 218 | * a matching device is found. If the requested device is indeed found,
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| 219 | * the index will have decremented down to -1/0xFFFF.
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| 220 | */
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| 221 | #define INDEX_DEV_FOUND 0xFFFF
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| 222 |
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| 223 | /* Find a specified PCI device, either by vendor+device ID or class.
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| 224 | * If index is non-zero, the n-th device will be located. When searching
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| 225 | * by class, the ignore_if flag only compares the base and sub-class code,
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| 226 | * ignoring the programming interface code.
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| 227 | *
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| 228 | * Note: This function is somewhat performance critical; since it may
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| 229 | * generate a high number of port I/O accesses, it can take a significant
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| 230 | * amount of time in cases where the caller is looking for a number of
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| 231 | * non-present devices.
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| 232 | */
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| 233 | uint16_t PCIxx(find_device)(uint32_t search_item, uint16_t index, int search_class, int ignore_if)
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| 234 | {
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| 235 | uint32_t data;
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| 236 | uint16_t bus_dev_fn;
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| 237 | uint8_t max_bus;
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| 238 | uint8_t hdr_type;
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| 239 | uint8_t subordinate;
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| 240 | int step;
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| 241 | int found;
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| 242 |
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| 243 | if (search_class) {
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| 244 | BX_DEBUG_PCI("PCI: Find class %08lX index %u\n",
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| 245 | search_item, index);
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| 246 | } else
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| 247 | BX_DEBUG_PCI("PCI: Find device %04X:%04X index %u\n",
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| 248 | (uint16_t)search_item, (uint16_t)(search_item >> 16), index);
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| 249 |
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| 250 | bus_dev_fn = 0; /* Start at the beginning. */
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| 251 | max_bus = 0; /* Initially assume primary bus only. */
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| 252 |
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| 253 | do {
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| 254 | /* For the first function of a device, read the device's header type.
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| 255 | * If the header type has all bits set, there's no device. A PCI
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| 256 | * multi-function device must implement function 0 and the header type
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| 257 | * will be something other than 0xFF. If the header type has the high
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| 258 | * bit clear, there is a device but it's not multi-function, so we can
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| 259 | * skip probing the next 7 sub-functions.
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| 260 | */
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| 261 | if ((bus_dev_fn & 7) == 0) {
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| 262 | PCIxx(select_reg)(bus_dev_fn, PCI_HEADER_TYPE);
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| 263 | hdr_type = inp(PCI_CFG_DATA + (PCI_HEADER_TYPE & 3));
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| 264 | if (hdr_type == 0xFF) {
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| 265 | bus_dev_fn += 8; /* Skip to next device. */
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| 266 | continue;
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| 267 | }
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| 268 | if (hdr_type & 0x80)
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| 269 | step = 1; /* MFD - try every sub-function. */
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| 270 | else
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| 271 | step = 8; /* No MFD, go to next device after probing. */
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| 272 | }
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| 273 |
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| 274 | /* If the header type indicates a bus, we're interested. The secondary
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| 275 | * and subordinate bus numbers will indicate which buses are present;
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| 276 | * thus we can determine the highest bus number. In the common case,
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| 277 | * there will be only the primary bus (i.e. bus 0) and we can avoid
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| 278 | * looking at the remaining 255 theoretically present buses. This check
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| 279 | * only needs to be done on the primary bus, since bridges must report
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| 280 | * all bridges potentially behind them.
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| 281 | */
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| 282 | if ((hdr_type & 7) == 1 && (bus_dev_fn >> 8) == 0) {
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| 283 | /* Read the subordinate (last) bridge number. */
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| 284 | PCIxx(select_reg)(bus_dev_fn, PCI_BRIDGE_SUBORD);
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| 285 | subordinate = inp(PCI_CFG_DATA + (PCI_BRIDGE_SUBORD & 3));
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| 286 | if (subordinate > max_bus)
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| 287 | max_bus = subordinate;
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| 288 | }
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| 289 |
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| 290 | /* Select the appropriate register. */
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| 291 | PCIxx(select_reg)(bus_dev_fn, search_class ? PCI_REV_ID : PCI_VEN_ID);
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| 292 | data = inpd(PCI_CFG_DATA);
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| 293 | found = 0;
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| 294 |
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| 295 | /* Only 3 or even just 2 bytes are compared for class searches. */
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| 296 | if (search_class)
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| 297 | if (ignore_if)
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| 298 | data >>= 16;
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| 299 | else
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| 300 | data >>= 8;
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| 301 |
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| 302 | #if 0
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| 303 | BX_DEBUG_PCI("PCI: Data is %08lX @ %02X:%%02X:%01X\n", data,
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| 304 | bus_dev_fn >> 8, bus_dev_fn >> 3 & 31, bus_dev_fn & 7);
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| 305 | #endif
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| 306 |
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| 307 | if (data == search_item)
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| 308 | found = 1;
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| 309 |
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| 310 | /* If device was found but index is non-zero, decrement index and
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| 311 | * continue looking. If requested device was found, index will be -1!
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| 312 | */
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| 313 | if (found && !index--)
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| 314 | break;
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| 315 |
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| 316 | bus_dev_fn += step;
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| 317 | } while ((bus_dev_fn >> 8) <= max_bus);
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| 318 |
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| 319 | if (index == INDEX_DEV_FOUND)
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| 320 | BX_DEBUG_PCI("PCI: Device found (%02X:%%02X:%01X)\n", bus_dev_fn >> 8,
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| 321 | bus_dev_fn >> 3 & 31, bus_dev_fn & 7);
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| 322 |
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| 323 | return index == INDEX_DEV_FOUND ? bus_dev_fn : BUSDEVFN_NOT_FOUND;
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| 324 | }
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| 325 |
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| 326 | void BIOSCALL PCIxx(function)(volatile pci_regs_t r)
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| 327 | {
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| 328 | pci_route_buf __far *route_buf;
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| 329 | uint16_t device;
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| 330 |
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| 331 | BX_DEBUG_PCI("PCI: AX=%04X BX=%04X CX=%04X DI=%04X\n", AX, BX, CX, DI);
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| 332 |
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| 333 | SET_AH(SUCCESSFUL); /* Assume success. */
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| 334 | CLEAR_CF();
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| 335 |
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| 336 | switch (GET_AL()) {
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| 337 | case PCI_BIOS_PRESENT:
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| 338 | AX = 0x0001; /* Configuration mechanism #1 supported. */
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| 339 | BX = 0x0210; /* Version 2.1. */
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| 340 | /// @todo return true max bus # in CL
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| 341 | CX = 0; /* Maximum bus number. */
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| 342 | EDX = 'P' | ('C' << 8) | ((uint32_t)'I' << 16) | ((uint32_t)' ' << 24);
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| 343 | break;
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| 344 | case FIND_PCI_DEVICE:
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| 345 | /* Vendor ID FFFFh is reserved so that non-present devices can
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| 346 | * be easily detected.
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| 347 | */
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| 348 | if (DX == 0xFFFF) {
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| 349 | SET_AH(BAD_VENDOR_ID);
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| 350 | SET_CF();
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| 351 | } else {
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| 352 | device = PCIxx(find_device)(DX | (uint32_t)CX << 16, SI, 0, 0);
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| 353 | if (device == BUSDEVFN_NOT_FOUND) {
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| 354 | SET_AH(DEVICE_NOT_FOUND);
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| 355 | SET_CF();
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| 356 | } else {
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| 357 | BX = device;
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| 358 | }
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| 359 | }
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| 360 | break;
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| 361 | case FIND_PCI_CLASS_CODE:
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| 362 | device = PCIxx(find_device)(ECX, SI, 1, 0);
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| 363 | if (device == BUSDEVFN_NOT_FOUND) {
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| 364 | SET_AH(DEVICE_NOT_FOUND);
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| 365 | SET_CF();
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| 366 | } else {
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| 367 | BX = device;
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| 368 | }
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| 369 | break;
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| 370 | case READ_CONFIG_BYTE:
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| 371 | case READ_CONFIG_WORD:
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| 372 | case READ_CONFIG_DWORD:
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| 373 | case WRITE_CONFIG_BYTE:
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| 374 | case WRITE_CONFIG_WORD:
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| 375 | case WRITE_CONFIG_DWORD:
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| 376 | if (DI >= 256) {
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| 377 | SET_AH(BAD_REGISTER_NUMBER);
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| 378 | SET_CF();
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| 379 | } else {
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| 380 | PCIxx(select_reg)(BX, DI);
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| 381 | switch (GET_AL()) {
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| 382 | case READ_CONFIG_BYTE:
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| 383 | SET_CL(inp(PCI_CFG_DATA + (DI & 3)));
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| 384 | break;
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| 385 | case READ_CONFIG_WORD:
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| 386 | CX = inpw(PCI_CFG_DATA + (DI & 2));
|
|---|
| 387 | break;
|
|---|
| 388 | case READ_CONFIG_DWORD:
|
|---|
| 389 | ECX = inpd(PCI_CFG_DATA);
|
|---|
| 390 | break;
|
|---|
| 391 | case WRITE_CONFIG_BYTE:
|
|---|
| 392 | outp(PCI_CFG_DATA + (DI & 3), GET_CL());
|
|---|
| 393 | break;
|
|---|
| 394 | case WRITE_CONFIG_WORD:
|
|---|
| 395 | outpw(PCI_CFG_DATA + (DI & 2), CX);
|
|---|
| 396 | break;
|
|---|
| 397 | case WRITE_CONFIG_DWORD:
|
|---|
| 398 | outpd(PCI_CFG_DATA, ECX);
|
|---|
| 399 | break;
|
|---|
| 400 | }
|
|---|
| 401 | }
|
|---|
| 402 | break;
|
|---|
| 403 | case GET_IRQ_ROUTING:
|
|---|
| 404 | route_buf = ES :> (void *)DI;
|
|---|
| 405 | BX_DEBUG_PCI("PCI: Route Buf %04X:%04X size %04X, need %04X (at %04X:%04X)\n",
|
|---|
| 406 | FP_SEG(route_buf->buf_ptr), FP_OFF(route_buf->buf_ptr),
|
|---|
| 407 | route_buf->buf_size, pci_routing_table_size, ES, DI);
|
|---|
| 408 | if (pci_routing_table_size > route_buf->buf_size) {
|
|---|
| 409 | SET_AH(BUFFER_TOO_SMALL);
|
|---|
| 410 | SET_CF();
|
|---|
| 411 | } else {
|
|---|
| 412 | rep_movsb(route_buf->buf_ptr, pci_routing_table, pci_routing_table_size);
|
|---|
| 413 | /* IRQs 9 and 11 are PCI only. */
|
|---|
| 414 | BX = (1 << 9) | (1 << 11);
|
|---|
| 415 | }
|
|---|
| 416 | route_buf->buf_size = pci_routing_table_size;
|
|---|
| 417 | break;
|
|---|
| 418 | default:
|
|---|
| 419 | BX_INFO("PCI: Unsupported function AX=%04X BX=%04X called\n", AX, BX);
|
|---|
| 420 | SET_AH(FUNC_NOT_SUPPORTED);
|
|---|
| 421 | SET_CF();
|
|---|
| 422 | }
|
|---|
| 423 | }
|
|---|
