VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsiCommon.cpp

Last change on this file was 98103, checked in by vboxsync, 17 months ago

Copyright year updates by scm.
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1/* $Id: MsiCommon.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * MSI support routines
4 *
5 * @todo Straighten up this file!!
6 */
7
8/*
9 * Copyright (C) 2010-2023 Oracle and/or its affiliates.
10 *
11 * This file is part of VirtualBox base platform packages, as
12 * available from https://www.virtualbox.org.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation, in version 3 of the
17 * License.
18 *
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see <https://www.gnu.org/licenses>.
26 *
27 * SPDX-License-Identifier: GPL-3.0-only
28 */
29
30#define LOG_GROUP LOG_GROUP_DEV_PCI
31#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
32#include <VBox/pci.h>
33#include <VBox/msi.h>
34#include <VBox/vmm/pdmdev.h>
35#include <VBox/log.h>
36
37#include "MsiCommon.h"
38#include "PciInline.h"
39#include "DevPciInternal.h"
40
41
42DECLINLINE(uint16_t) msiGetMessageControl(PPDMPCIDEV pDev)
43{
44 uint32_t idxMessageControl = pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL;
45#ifdef IN_RING3
46 if (pciDevIsPassthrough(pDev) && pDev->Int.s.pfnConfigRead)
47 {
48 uint32_t u32Value = 0;
49 VBOXSTRICTRC rcStrict = pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2, &u32Value);
50 AssertRCSuccess(VBOXSTRICTRC_VAL(rcStrict));
51 return (uint16_t)u32Value;
52 }
53#endif
54 return PCIDevGetWord(pDev, idxMessageControl);
55}
56
57DECLINLINE(bool) msiIs64Bit(PPDMPCIDEV pDev)
58{
59 return pciDevIsMsi64Capable(pDev);
60}
61
62/** @todo r=klaus This design assumes that the config space cache is always
63 * up to date, which is a wrong assumption for the "emulate passthrough" case
64 * where only the callbacks give the correct data. */
65DECLINLINE(uint32_t *) msiGetMaskBits(PPDMPCIDEV pDev)
66{
67 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
68 /* devices may have no masked/pending support */
69 if (iOff >= pDev->Int.s.u8MsiCapSize)
70 return NULL;
71 iOff += pDev->Int.s.u8MsiCapOffset;
72 return (uint32_t*)(pDev->abConfig + iOff);
73}
74
75/** @todo r=klaus This design assumes that the config space cache is always
76 * up to date, which is a wrong assumption for the "emulate passthrough" case
77 * where only the callbacks give the correct data. */
78DECLINLINE(uint32_t*) msiGetPendingBits(PPDMPCIDEV pDev)
79{
80 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32;
81 /* devices may have no masked/pending support */
82 if (iOff >= pDev->Int.s.u8MsiCapSize)
83 return NULL;
84 iOff += pDev->Int.s.u8MsiCapOffset;
85 return (uint32_t*)(pDev->abConfig + iOff);
86}
87
88DECLINLINE(bool) msiIsEnabled(PPDMPCIDEV pDev)
89{
90 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0;
91}
92
93DECLINLINE(uint8_t) msiGetMme(PPDMPCIDEV pDev)
94{
95 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) >> 4;
96}
97
98DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPDMPCIDEV pDev)
99{
100 if (msiIs64Bit(pDev))
101 {
102 uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
103 uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
104 return RT_MAKE_U64(lo, hi);
105 }
106 return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
107}
108
109DECLINLINE(uint32_t) msiGetMsiData(PPDMPCIDEV pDev, int32_t iVector)
110{
111 int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32;
112 uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
113
114 // vector encoding into lower bits of message data
115 uint8_t bits = msiGetMme(pDev);
116 uint16_t uMask = ((1 << bits) - 1);
117 lo &= ~uMask;
118 lo |= iVector & uMask;
119
120 return RT_MAKE_U32(lo, 0);
121}
122
123#ifdef IN_RING3
124
125DECLINLINE(bool) msiR3BitJustCleared(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
126{
127 return !!(uOldValue & uMask) && !(uNewValue & uMask);
128}
129
130DECLINLINE(bool) msiR3BitJustSet(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
131{
132 return !(uOldValue & uMask) && !!(uNewValue & uMask);
133}
134
135/**
136 * PCI config space accessors for MSI registers.
137 */
138void MsiR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev,
139 uint32_t u32Address, uint32_t val, unsigned len)
140{
141 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
142 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
143
144 Log2(("MsiR3PciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
145
146 uint32_t uAddr = u32Address;
147 bool f64Bit = msiIs64Bit(pDev);
148
149 for (uint32_t i = 0; i < len; i++)
150 {
151 uint32_t reg = i + iOff;
152 uint8_t u8Val = (uint8_t)val;
153 switch (reg)
154 {
155 case 0: /* Capability ID, ro */
156 case 1: /* Next pointer, ro */
157 break;
158 case VBOX_MSI_CAP_MESSAGE_CONTROL:
159 /* don't change read-only bits: 1-3,7 */
160 u8Val &= UINT8_C(~0x8e);
161 pDev->abConfig[uAddr] = u8Val | (pDev->abConfig[uAddr] & UINT8_C(0x8e));
162 break;
163 case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
164 /* don't change read-only bit 8, and reserved 9-15 */
165 break;
166 default:
167 if (pDev->abConfig[uAddr] != u8Val)
168 {
169 int32_t maskUpdated = -1;
170
171 /* If we're enabling masked vector, and have pending messages
172 for this vector, we have to send this message now */
173 if ( !f64Bit
174 && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
175 && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
176 )
177 {
178 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
179 }
180 if ( f64Bit
181 && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
182 && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
183 )
184 {
185 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
186 }
187
188 if (maskUpdated != -1 && msiIsEnabled(pDev))
189 {
190 uint32_t* puPending = msiGetPendingBits(pDev);
191 for (int iBitNum = 0; iBitNum < 8; iBitNum++)
192 {
193 int32_t iBit = 1 << iBitNum;
194 uint32_t uVector = maskUpdated*8 + iBitNum;
195
196 if (msiR3BitJustCleared(pDev->abConfig[uAddr], u8Val, iBit))
197 {
198 Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated));
199
200 /* To ensure that we're no longer masked */
201 pDev->abConfig[uAddr] &= ~iBit;
202 if ((*puPending & (1 << uVector)) != 0)
203 {
204 Log(("msi: notify earlier masked pending vector: %d\n", uVector));
205 MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH, 0 /*uTagSrc*/);
206 }
207 }
208 if (msiR3BitJustSet(pDev->abConfig[uAddr], u8Val, iBit))
209 {
210 Log(("msi: mask vector: %d\n", uVector));
211 }
212 }
213 }
214
215 pDev->abConfig[uAddr] = u8Val;
216 }
217 }
218 uAddr++;
219 val >>= 8;
220 }
221}
222
223/**
224 * Initializes MSI support for the given PCI device.
225 */
226int MsiR3Init(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
227{
228 if (pMsiReg->cMsiVectors == 0)
229 return VINF_SUCCESS;
230
231 /* XXX: done in pcirawAnalyzePciCaps() */
232 if (pciDevIsPassthrough(pDev))
233 return VINF_SUCCESS;
234
235 uint16_t cVectors = pMsiReg->cMsiVectors;
236 uint8_t iCapOffset = pMsiReg->iMsiCapOffset;
237 uint8_t iNextOffset = pMsiReg->iMsiNextOffset;
238 bool f64bit = pMsiReg->fMsi64bit;
239 bool fNoMasking = pMsiReg->fMsiNoMasking;
240 uint16_t iFlags = 0;
241
242 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
243
244 if (!fNoMasking)
245 {
246 int iMmc;
247
248 /* Compute multiple-message capable bitfield */
249 for (iMmc = 0; iMmc < 6; iMmc++)
250 {
251 if ((1 << iMmc) >= cVectors)
252 break;
253 }
254
255 if ((cVectors > VBOX_MSI_MAX_ENTRIES) || (1 << iMmc) < cVectors)
256 return VERR_TOO_MUCH_DATA;
257
258 /* We support per-vector masking */
259 iFlags |= VBOX_PCI_MSI_FLAGS_MASKBIT;
260 /* How many vectors we're capable of */
261 iFlags |= iMmc;
262 }
263
264 if (f64bit)
265 iFlags |= VBOX_PCI_MSI_FLAGS_64BIT;
266
267 pDev->Int.s.u8MsiCapOffset = iCapOffset;
268 pDev->Int.s.u8MsiCapSize = f64bit ? VBOX_MSI_CAP_SIZE_64 : VBOX_MSI_CAP_SIZE_32;
269
270 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSI);
271 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
272 PCIDevSetWord(pDev, iCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL, iFlags);
273
274 if (!fNoMasking)
275 {
276 *msiGetMaskBits(pDev) = 0;
277 *msiGetPendingBits(pDev) = 0;
278 }
279
280 pciDevSetMsiCapable(pDev);
281 if (f64bit)
282 pciDevSetMsi64Capable(pDev);
283
284 return VINF_SUCCESS;
285}
286
287#endif /* IN_RING3 */
288
289
290/**
291 * Checks if MSI is enabled for the given PCI device.
292 *
293 * (Must use MSINotify() for notifications when true.)
294 */
295bool MsiIsEnabled(PPDMPCIDEV pDev)
296{
297 return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev);
298}
299
300/**
301 * Device notification (aka interrupt).
302 */
303void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc)
304{
305 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that"));
306
307 uint32_t uMask;
308 uint32_t *puPending = msiGetPendingBits(pDev);
309 if (puPending)
310 {
311 uint32_t *puMask = msiGetMaskBits(pDev);
312 AssertPtr(puMask);
313 uMask = *puMask;
314 LogFlow(("MsiNotify: %d pending=%x mask=%x\n", iVector, *puPending, uMask));
315 }
316 else
317 {
318 uMask = 0;
319 LogFlow(("MsiNotify: %d\n", iVector));
320 }
321
322 /* We only trigger MSI on level up */
323 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
324 {
325 /** @todo maybe clear pending interrupts on level down? */
326#if 0
327 if (puPending)
328 {
329 *puPending &= ~(1<<iVector);
330 LogFlow(("msi: clear pending %d, now %x\n", iVector, *puPending));
331 }
332#endif
333 return;
334 }
335
336 if ((uMask & (1<<iVector)) != 0)
337 {
338 *puPending |= (1<<iVector);
339 LogFlow(("msi: %d is masked, mark pending, now %x\n", iVector, *puPending));
340 return;
341 }
342
343 MSIMSG Msi;
344 Msi.Addr.u64 = msiGetMsiAddress(pDev);
345 Msi.Data.u32 = msiGetMsiData(pDev, iVector);
346
347 if (puPending)
348 *puPending &= ~(1<<iVector);
349
350 PPDMDEVINS pDevInsBus = pPciHlp->pfnGetBusByNo(pDevIns, pDev->Int.s.idxPdmBus);
351 Assert(pDevInsBus);
352 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS);
353 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, pDev->uDevFn);
354
355 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
356 pPciHlp->pfnIoApicSendMsi(pDevIns, uBusDevFn, &Msi, uTagSrc);
357}
358
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