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root/trunk/include/VBox/hwacc_vmx.h

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1 /** @file
2  * HWACCM - VMX Structures and Definitions.
3  */
4
5 /*
6  * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7  *
8  * This file is part of VirtualBox Open Source Edition (OSE), as
9  * available from http://www.virtualbox.org. This file is free software;
10  * you can redistribute it and/or modify it under the terms of the GNU
11  * General Public License (GPL) as published by the Free Software
12  * Foundation, in version 2 as it comes in the "COPYING" file of the
13  * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14  * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15  *
16  * The contents of this file may alternatively be used under the terms
17  * of the Common Development and Distribution License Version 1.0
18  * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19  * VirtualBox OSE distribution, in which case the provisions of the
20  * CDDL are applicable instead of those of the GPL.
21  *
22  * You may elect to license modified versions of this file under the
23  * terms and conditions of either the GPL or the CDDL or both.
24  *
25  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26  * Clara, CA 95054 USA or visit http://www.sun.com if you need
27  * additional information or have any questions.
28  */
29
30 #ifndef ___VBox_vmx_h
31 #define ___VBox_vmx_h
32
33 #include <VBox/types.h>
34 #include <VBox/err.h>
35 #include <iprt/assert.h>
36 #include <iprt/asm.h>
37 #include <VBox/x86.h>
38
39 /** @defgroup grp_vmx   vmx Types and Definitions
40  * @ingroup grp_hwaccm
41  * @{
42  */
43
44 /** @name VMX EPT paging structures
45  * @{
46  */
47
48 /**
49  * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
50  */
51 #define EPT_PG_ENTRIES          X86_PG_PAE_ENTRIES
52
53 /**
54  * EPT Page Directory Pointer Entry. Bit view.
55  * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
56  *       this did cause trouble with one compiler/version).
57  */
58 #pragma pack(1)
59 typedef struct EPTPML4EBITS
60 {
61     /** Present bit. */
62     uint64_t    u1Present       : 1;
63     /** Writable bit. */
64     uint64_t    u1Write         : 1;
65     /** Executable bit. */
66     uint64_t    u1Execute       : 1;
67     /** Reserved (must be 0). */
68     uint64_t    u5Reserved      : 5;
69     /** Available for software. */
70     uint64_t    u4Available     : 4;
71     /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
72     uint64_t    u40PhysAddr     : 40;
73     /** Availabe for software. */
74     uint64_t    u12Available    : 12;
75 } EPTPML4EBITS;
76 #pragma pack()
77 AssertCompileSize(EPTPML4EBITS, 8);
78
79 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
80 #define EPT_PML4E_PG_MASK       X86_PML4E_PG_MASK_FULL
81 /** The page shift to get the PML4 index. */
82 #define EPT_PML4_SHIFT          X86_PML4_SHIFT
83 /** The PML4 index mask (apply to a shifted page address). */
84 #define EPT_PML4_MASK           X86_PML4_MASK
85
86 /**
87  * EPT PML4E.
88  */
89 #pragma pack(1)
90 typedef union EPTPML4E
91 {
92     /** Normal view. */
93     EPTPML4EBITS    n;
94     /** Unsigned integer view. */
95     X86PGPAEUINT    u;
96     /** 64 bit unsigned integer view. */
97     uint64_t        au64[1];
98     /** 32 bit unsigned integer view. */
99     uint32_t        au32[2];
100 } EPTPML4E;
101 #pragma pack()
102 /** Pointer to a PML4 table entry. */
103 typedef EPTPML4E *PEPTPML4E;
104 /** Pointer to a const PML4 table entry. */
105 typedef const EPTPML4E *PCEPTPML4E;
106 AssertCompileSize(EPTPML4E, 8);
107
108 /**
109  * EPT PML4 Table.
110  */
111 #pragma pack(1)
112 typedef struct EPTPML4
113 {
114     EPTPML4E    a[EPT_PG_ENTRIES];
115 } EPTPML4;
116 #pragma pack()
117 /** Pointer to an EPT PML4 Table. */
118 typedef EPTPML4 *PEPTPML4;
119 /** Pointer to a const EPT PML4 Table. */
120 typedef const EPTPML4 *PCEPTPML4;
121
122 /**
123  * EPT Page Directory Pointer Entry. Bit view.
124  */
125 #pragma pack(1)
126 typedef struct EPTPDPTEBITS
127 {
128     /** Present bit. */
129     uint64_t    u1Present       : 1;
130     /** Writable bit. */
131     uint64_t    u1Write         : 1;
132     /** Executable bit. */
133     uint64_t    u1Execute       : 1;
134     /** Reserved (must be 0). */
135     uint64_t    u5Reserved      : 5;
136     /** Available for software. */
137     uint64_t    u4Available     : 4;
138     /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
139     uint64_t    u40PhysAddr     : 40;
140     /** Availabe for software. */
141     uint64_t    u12Available    : 12;
142 } EPTPDPTEBITS;
143 #pragma pack()
144 AssertCompileSize(EPTPDPTEBITS, 8);
145
146 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
147 #define EPT_PDPTE_PG_MASK       X86_PDPE_PG_MASK_FULL
148 /** The page shift to get the PDPT index. */
149 #define EPT_PDPT_SHIFT          X86_PDPT_SHIFT
150 /** The PDPT index mask (apply to a shifted page address). */
151 #define EPT_PDPT_MASK           X86_PDPT_MASK_AMD64
152
153 /**
154  * EPT Page Directory Pointer.
155  */
156 #pragma pack(1)
157 typedef union EPTPDPTE
158 {
159     /** Normal view. */
160     EPTPDPTEBITS    n;
161     /** Unsigned integer view. */
162     X86PGPAEUINT    u;
163     /** 64 bit unsigned integer view. */
164     uint64_t        au64[1];
165     /** 32 bit unsigned integer view. */
166     uint32_t        au32[2];
167 } EPTPDPTE;
168 #pragma pack()
169 /** Pointer to an EPT Page Directory Pointer Entry. */
170 typedef EPTPDPTE *PEPTPDPTE;
171 /** Pointer to a const EPT Page Directory Pointer Entry. */
172 typedef const EPTPDPTE *PCEPTPDPTE;
173 AssertCompileSize(EPTPDPTE, 8);
174
175 /**
176  * EPT Page Directory Pointer Table.
177  */
178 #pragma pack(1)
179 typedef struct EPTPDPT
180 {
181     EPTPDPTE    a[EPT_PG_ENTRIES];
182 } EPTPDPT;
183 #pragma pack()
184 /** Pointer to an EPT Page Directory Pointer Table. */
185 typedef EPTPDPT *PEPTPDPT;
186 /** Pointer to a const EPT Page Directory Pointer Table. */
187 typedef const EPTPDPT *PCEPTPDPT;
188
189
190 /**
191  * EPT Page Directory Table Entry. Bit view.
192  */
193 #pragma pack(1)
194 typedef struct EPTPDEBITS
195 {
196     /** Present bit. */
197     uint64_t    u1Present       : 1;
198     /** Writable bit. */
199     uint64_t    u1Write         : 1;
200     /** Executable bit. */
201     uint64_t    u1Execute       : 1;
202     /** Reserved (must be 0). */
203     uint64_t    u4Reserved      : 4;
204     /** Big page (must be 0 here). */
205     uint64_t    u1Big           : 1;
206     /** Available for software. */
207     uint64_t    u4Available     : 4;
208     /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
209     uint64_t    u40PhysAddr     : 40;
210     /** Availabe for software. */
211     uint64_t    u12Available    : 12;
212 } EPTPDEBITS;
213 #pragma pack()
214 AssertCompileSize(EPTPDEBITS, 8);
215
216 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
217 #define EPT_PDE_PG_MASK         X86_PDE_PAE_PG_MASK_FULL
218 /** The page shift to get the PD index. */
219 #define EPT_PD_SHIFT            X86_PD_PAE_SHIFT
220 /** The PD index mask (apply to a shifted page address). */
221 #define EPT_PD_MASK             X86_PD_PAE_MASK
222
223 /**
224  * EPT 2MB Page Directory Table Entry. Bit view.
225  */
226 #pragma pack(1)
227 typedef struct EPTPDE2MBITS
228 {
229     /** Present bit. */
230     uint64_t    u1Present       : 1;
231     /** Writable bit. */
232     uint64_t    u1Write         : 1;
233     /** Executable bit. */
234     uint64_t    u1Execute       : 1;
235     /** EPT Table Memory Type. MBZ for non-leaf nodes. */
236     uint64_t    u3EMT           : 3;
237     /** Ignore PAT memory type */
238     uint64_t    u1IgnorePAT     : 1;
239     /** Big page (must be 1 here). */
240     uint64_t    u1Size          : 1;
241     /** Available for software. */
242     uint64_t    u4Available     : 4;
243     /** Reserved (must be 0). */
244     uint64_t    u9Reserved      : 9;
245     /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
246     uint64_t    u31PhysAddr     : 31;
247     /** Availabe for software. */
248     uint64_t    u12Available    : 12;
249 } EPTPDE2MBITS;
250 #pragma pack()
251 AssertCompileSize(EPTPDE2MBITS, 8);
252
253 /** Bits 21-51 - - EPT - Physical Page number of the next level. */
254 #define EPT_PDE2M_PG_MASK       ( 0x000fffffffe00000ULL )
255
256 /**
257  * EPT Page Directory Table Entry.
258  */
259 #pragma pack(1)
260 typedef union EPTPDE
261 {
262     /** Normal view. */
263     EPTPDEBITS      n;
264     /** 2MB view (big). */
265     EPTPDE2MBITS    b;
266     /** Unsigned integer view. */
267     X86PGPAEUINT    u;
268     /** 64 bit unsigned integer view. */
269     uint64_t        au64[1];
270     /** 32 bit unsigned integer view. */
271     uint32_t        au32[2];
272 } EPTPDE;
273 #pragma pack()
274 /** Pointer to an EPT Page Directory Table Entry. */
275 typedef EPTPDE *PEPTPDE;
276 /** Pointer to a const EPT Page Directory Table Entry. */
277 typedef const EPTPDE *PCEPTPDE;
278 AssertCompileSize(EPTPDE, 8);
279
280 /**
281  * EPT Page Directory Table.
282  */
283 #pragma pack(1)
284 typedef struct EPTPD
285 {
286     EPTPDE      a[EPT_PG_ENTRIES];
287 } EPTPD;
288 #pragma pack()
289 /** Pointer to an EPT Page Directory Table. */
290 typedef EPTPD *PEPTPD;
291 /** Pointer to a const EPT Page Directory Table. */
292 typedef const EPTPD *PCEPTPD;
293
294
295 /**
296  * EPT Page Table Entry. Bit view.
297  */
298 #pragma pack(1)
299 typedef struct EPTPTEBITS
300 {
301     /** Present bit. */
302     uint64_t    u1Present       : 1;
303     /** Writable bit. */
304     uint64_t    u1Write         : 1;
305     /** Executable bit. */
306     uint64_t    u1Execute       : 1;
307     /** EPT Table Memory Type. MBZ for non-leaf nodes. */
308     uint64_t    u3EMT           : 3;
309     /** Ignore PAT memory type */
310     uint64_t    u1IgnorePAT     : 1;
311     /** Available for software. */
312     uint64_t    u5Available     : 5;
313     /** Physical address of page. Restricted by maximum physical address width of the cpu. */
314     uint64_t    u40PhysAddr     : 40;
315     /** Availabe for software. */
316     uint64_t    u12Available    : 12;
317 } EPTPTEBITS;
318 #pragma pack()
319 AssertCompileSize(EPTPTEBITS, 8);
320
321 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
322 #define EPT_PTE_PG_MASK         X86_PTE_PAE_PG_MASK_FULL
323 /** The page shift to get the EPT PTE index. */
324 #define EPT_PT_SHIFT            X86_PT_PAE_SHIFT
325 /** The EPT PT index mask (apply to a shifted page address). */
326 #define EPT_PT_MASK             X86_PT_PAE_MASK
327
328 /**
329  * EPT Page Table Entry.
330  */
331 #pragma pack(1)
332 typedef union EPTPTE
333 {
334     /** Normal view. */
335     EPTPTEBITS      n;
336     /** Unsigned integer view. */
337     X86PGPAEUINT    u;
338     /** 64 bit unsigned integer view. */
339     uint64_t        au64[1];
340     /** 32 bit unsigned integer view. */
341     uint32_t        au32[2];
342 } EPTPTE;
343 #pragma pack()
344 /** Pointer to an EPT Page Directory Table Entry. */
345 typedef EPTPTE *PEPTPTE;
346 /** Pointer to a const EPT Page Directory Table Entry. */
347 typedef const EPTPTE *PCEPTPTE;
348 AssertCompileSize(EPTPTE, 8);
349
350 /**
351  * EPT Page Table.
352  */
353 #pragma pack(1)
354 typedef struct EPTPT
355 {
356     EPTPTE      a[EPT_PG_ENTRIES];
357 } EPTPT;
358 #pragma pack()
359 /** Pointer to an extended page table. */
360 typedef EPTPT *PEPTPT;
361 /** Pointer to a const extended table. */
362 typedef const EPTPT *PCEPTPT;
363
364 /**
365  * VPID and EPT flush types
366  */
367 typedef enum
368 {
369     /* Invalidate a specific page. */
370     VMX_FLUSH_PAGE                              = 0,
371     /* Invalidate one context (VPID or EPT) */
372     VMX_FLUSH_SINGLE_CONTEXT                    = 1,
373     /* Invalidate all contexts (VPIDs or EPTs) */
374     VMX_FLUSH_ALL_CONTEXTS                      = 2,
375     /* Invalidate a single VPID context retaining global mappings. */
376     VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL     = 3,
377     /** 32bit hackishness. */
378     VMX_FLUSH_32BIT_HACK                        = 0x7fffffff
379 } VMX_FLUSH;
380
381 /** @} */
382
383
384 /** @name VMX Basic Exit Reasons.
385  * @{
386  */
387 /** And-mask for setting reserved bits to zero */
388 #define VMX_EFLAGS_RESERVED_0           (~0xffc08028)
389 /** Or-mask for setting reserved bits to 1 */
390 #define VMX_EFLAGS_RESERVED_1           0x00000002
391 /** @} */
392
393 /** @name VMX Basic Exit Reasons.
394  * @{
395  */
396 /** 0 Exception or non-maskable interrupt (NMI). */
397 #define VMX_EXIT_EXCEPTION          0
398 /** 1 External interrupt. */
399 #define VMX_EXIT_EXTERNAL_IRQ       1
400 /** 2 Triple fault. */
401 #define VMX_EXIT_TRIPLE_FAULT       2
402 /** 3 INIT signal. */
403 #define VMX_EXIT_INIT_SIGNAL        3
404 /** 4 Start-up IPI (SIPI). */
405 #define VMX_EXIT_SIPI               4
406 /** 5 I/O system-management interrupt (SMI). */
407 #define VMX_EXIT_IO_SMI_IRQ         5
408 /** 6 Other SMI. */
409 #define VMX_EXIT_SMI_IRQ            6
410 /** 7 Interrupt window. */
411 #define VMX_EXIT_IRQ_WINDOW         7
412 /** 9 Task switch. */
413 #define VMX_EXIT_TASK_SWITCH        9
414 /** 10 Guest software attempted to execute CPUID. */
415 #define VMX_EXIT_CPUID              10
416 /** 12 Guest software attempted to execute HLT. */
417 #define VMX_EXIT_HLT                12
418 /** 13 Guest software attempted to execute INVD. */
419 #define VMX_EXIT_INVD               13
420 /** 14 Guest software attempted to execute INVPG. */
421 #define VMX_EXIT_INVPG              14
422 /** 15 Guest software attempted to execute RDPMC. */
423 #define VMX_EXIT_RDPMC              15
424 /** 16 Guest software attempted to execute RDTSC. */
425 #define VMX_EXIT_RDTSC              16
426 /** 17 Guest software attempted to execute RSM in SMM. */
427 #define VMX_EXIT_RSM                17
428 /** 18 Guest software executed VMCALL. */
429 #define VMX_EXIT_VMCALL             18
430 /** 19 Guest software executed VMCLEAR. */
431 #define VMX_EXIT_VMCLEAR            19
432 /** 20 Guest software executed VMLAUNCH. */
433 #define VMX_EXIT_VMLAUNCH           20
434 /** 21 Guest software executed VMPTRLD. */
435 #define VMX_EXIT_VMPTRLD            21
436 /** 22 Guest software executed VMPTRST. */
437 #define VMX_EXIT_VMPTRST            22
438 /** 23 Guest software executed VMREAD. */
439 #define VMX_EXIT_VMREAD             23
440 /** 24 Guest software executed VMRESUME. */
441 #define VMX_EXIT_VMRESUME           24
442 /** 25 Guest software executed VMWRITE. */
443 #define VMX_EXIT_VMWRITE            25
444 /** 26 Guest software executed VMXOFF. */
445 #define VMX_EXIT_VMXOFF             26
446 /** 27 Guest software executed VMXON. */
447 #define VMX_EXIT_VMXON              27
448 /** 28 Control-register accesses. */
449 #define VMX_EXIT_CRX_MOVE           28
450 /** 29 Debug-register accesses. */
451 #define VMX_EXIT_DRX_MOVE           29
452 /** 30 I/O instruction. */
453 #define VMX_EXIT_PORT_IO            30
454 /** 31 RDMSR. Guest software attempted to execute RDMSR. */
455 #define VMX_EXIT_RDMSR              31
456 /** 32 WRMSR. Guest software attempted to execute WRMSR. */
457 #define VMX_EXIT_WRMSR              32
458 /** 33 VM-entry failure due to invalid guest state. */
459 #define VMX_EXIT_ERR_INVALID_GUEST_STATE    33
460 /** 34 VM-entry failure due to MSR loading. */
461 #define VMX_EXIT_ERR_MSR_LOAD       34
462 /** 36 Guest software executed MWAIT. */
463 #define VMX_EXIT_MWAIT              36
464 /** 39 Guest software attempted to execute MONITOR. */
465 #define VMX_EXIT_MONITOR            39
466 /** 40 Guest software attempted to execute PAUSE. */
467 #define VMX_EXIT_PAUSE              40
468 /** 41 VM-entry failure due to machine-check. */
469 #define VMX_EXIT_ERR_MACHINE_CHECK  41
470 /** 43 TPR below threshold. Guest software executed MOV to CR8. */
471 #define VMX_EXIT_TPR                43
472 /** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
473 #define VMX_EXIT_APIC_ACCESS        44
474 /** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
475 #define VMX_EXIT_XDTR_ACCESS        46
476 /** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
477 #define VMX_EXIT_TR_ACCESS          47
478 /** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
479 #define VMX_EXIT_EPT_VIOLATION      48
480 /** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
481 #define VMX_EXIT_EPT_MISCONFIG      49
482 /** 50 INVEPT. Guest software attempted to execute INVEPT. */
483 #define VMX_EXIT_INVEPT             50
484 /** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
485 #define VMX_EXIT_PREEMPTION_TIMER   52
486 /** 53 INVVPID. Guest software attempted to execute INVVPID. */
487 #define VMX_EXIT_INVVPID            53
488 /** 54 WBINVD. Guest software attempted to execute WBINVD. */
489 #define VMX_EXIT_WBINVD             54
490 /** 55 XSETBV. Guest software attempted to execute XSETBV. */
491 #define VMX_EXIT_XSETBV             55
492 /** @} */
493
494
495 /** @name VM Instruction Errors
496  * @{
497  */
498 /** 1 VMCALL executed in VMX root operation. */
499 #define VMX_ERROR_VMCALL                            1
500 /** 2 VMCLEAR with invalid physical address. */
501 #define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR         2
502 /** 3 VMCLEAR with VMXON pointer. */
503 #define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR         3
504 /** 4 VMLAUNCH with non-clear VMCS. */
505 #define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS            4
506 /** 5 VMRESUME with non-launched VMCS. */
507 #define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS        5
508 /** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
509 #define VMX_ERROR_VMRESUME_CORRUPTED_VMCS           6
510 /** 7 VM entry with invalid control field(s). */
511 #define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS    7
512 /** 8 VM entry with invalid host-state field(s). */
513 #define VMX_ERROR_VMENTRY_INVALID_HOST_STATE        8
514 /** 9 VMPTRLD with invalid physical address. */
515 #define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR         9
516 /** 10 VMPTRLD with VMXON pointer. */
517 #define VMX_ERROR_VMPTRLD_VMXON_PTR                 10
518 /** 11 VMPTRLD with incorrect VMCS revision identifier. */
519 #define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION       11
520 /** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
521 #define VMX_ERROR_VMREAD_INVALID_COMPONENT          12
522 #define VMX_ERROR_VMWRITE_INVALID_COMPONENT         VMX_ERROR_VMREAD_INVALID_COMPONENT
523 /** 13 VMWRITE to read-only VMCS component. */
524 #define VMX_ERROR_VMWRITE_READONLY_COMPONENT        13
525 /** 15 VMXON executed in VMX root operation. */
526 #define VMX_ERROR_VMXON_IN_VMX_ROOT_OP              15
527 /** 16 VM entry with invalid executive-VMCS pointer. */
528 #define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR     16
529 /** 17 VM entry with non-launched executive VMCS. */
530 #define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS    17
531 /** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
532 #define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR             18
533 /** 19 VMCALL with non-clear VMCS. */
534 #define VMX_ERROR_VMCALL_NON_CLEAR_VMCS             19
535 /** 20 VMCALL with invalid VM-exit control fields. */
536 #define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS      20
537 /** 22 VMCALL with incorrect MSEG revision identifier. */
538 #define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION      22
539 /** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
540 #define VMX_ERROR_VMXOFF_DUAL_MONITOR               23
541 /** 24 VMCALL with invalid SMM-monitor features. */
542 #define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR        24
543 /** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
544 #define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL      25
545 /** 26 VM entry with events blocked by MOV SS. */
546 #define VMX_ERROR_VMENTRY_MOV_SS                    26
547
548 /** @} */
549
550
551 /** @name VMX MSRs - Basic VMX information.
552  * @{
553  */
554 /** VMCS revision identifier used by the processor. */
555 #define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a)                      (a & 0x7FFFFFFF)
556 /** Size of the VMCS. */
557 #define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a)                    ((a >> 32ULL) & 0xFFF)
558 /** Width of physical address used for the VMCS.
559  *  0 -> limited to the available amount of physical ram
560  *  1 -> within the first 4 GB
561  */
562 #define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a)              ((a >> 48ULL) & 1)
563 /** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
564 #define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a)                ((a >> 49ULL) & 1)
565 /** Memory type that must be used for the VMCS. */
566 #define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a)                ((a >> 50ULL) & 0xF)
567 /** @} */
568
569
570 /** @name VMX MSRs - Misc VMX info.
571  * @{
572  */
573 /** Activity states supported by the implementation. */
574 #define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a)                    ((a >> 6ULL) & 0x7)
575 /** Number of CR3 target values supported by the processor. (0-256) */
576 #define MSR_IA32_VMX_MISC_CR3_TARGET(a)                         ((a >> 16ULL) & 0x1FF)
577 /** Maximum nr of MSRs in the VMCS. (N+1)*512. */
578 #define MSR_IA32_VMX_MISC_MAX_MSR(a)                            ((((a >> 25ULL) & 0x7) + 1) * 512)
579 /** MSEG revision identifier used by the processor. */
580 #define MSR_IA32_VMX_MISC_MSEG_ID(a)                            (a >> 32ULL)
581 /** @} */
582
583
584 /** @name VMX MSRs - VMCS enumeration field info
585  * @{
586  */
587 /** Highest field index. */
588 #define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a)                 ((a >> 1ULL) & 0x1FF)
589
590 /** @} */
591
592
593 /** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
594  * @{
595  */
596 #define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY                     RT_BIT_64(0)
597 #define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY                     RT_BIT_64(1)
598 #define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY                    RT_BIT_64(2)
599 #define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS                    RT_BIT_64(3)
600 #define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS                    RT_BIT_64(4)
601 #define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS                    RT_BIT_64(5)
602 #define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS                    RT_BIT_64(6)
603 #define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS                    RT_BIT_64(7)
604 #define MSR_IA32_VMX_EPT_CAPS_EMT_UC                         RT_BIT_64(8)
605 #define MSR_IA32_VMX_EPT_CAPS_EMT_WC                         RT_BIT_64(9)
606 #define MSR_IA32_VMX_EPT_CAPS_EMT_WT                         RT_BIT_64(12)
607 #define MSR_IA32_VMX_EPT_CAPS_EMT_WP                         RT_BIT_64(13)
608 #define MSR_IA32_VMX_EPT_CAPS_EMT_WB                         RT_BIT_64(14)
609 #define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS                     RT_BIT_64(16)
610 #define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS                     RT_BIT_64(17)
611 #define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS                     RT_BIT_64(18)
612 #define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS                     RT_BIT_64(19)
613 #define MSR_IA32_VMX_EPT_CAPS_INVEPT                         RT_BIT_64(20)
614 #define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV              RT_BIT_64(24)
615 #define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT            RT_BIT_64(25)
616 #define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL                RT_BIT_64(26)
617 #define MSR_IA32_VMX_EPT_CAPS_INVVPID                        RT_BIT_64(32)
618 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV             RT_BIT_64(40)
619 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT           RT_BIT_64(41)
620 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL               RT_BIT_64(42)
621 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL    RT_BIT_64(43)
622
623 /** @} */
624
625 /** @name Extended Page Table Pointer (EPTP)
626  * @{
627  */
628 /** Uncachable EPT paging structure memory type. */
629 #define VMX_EPT_MEMTYPE_UC                                  0
630 /** Write-back EPT paging structure memory type. */
631 #define VMX_EPT_MEMTYPE_WB                                  6
632 /** Shift value to get the EPT page walk length (bits 5-3) */
633 #define VMX_EPT_PAGE_WALK_LENGTH_SHIFT                      3
634 /** Mask value to get the EPT page walk length (bits 5-3) */
635 #define VMX_EPT_PAGE_WALK_LENGTH_MASK                       7
636 /** Default EPT page walk length */
637 #define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT                    3
638 /** @} */
639
640
641 /** @name VMCS field encoding - 16 bits guest fields
642  * @{
643  */
644 #define VMX_VMCS_GUEST_FIELD_VPID                               0x0
645 #define VMX_VMCS_GUEST_FIELD_ES                                 0x800
646 #define VMX_VMCS_GUEST_FIELD_CS                                 0x802
647 #define VMX_VMCS_GUEST_FIELD_SS                                 0x804
648 #define VMX_VMCS_GUEST_FIELD_DS                                 0x806
649 #define VMX_VMCS_GUEST_FIELD_FS                                 0x808
650 #define VMX_VMCS_GUEST_FIELD_GS                                 0x80A
651 #define VMX_VMCS_GUEST_FIELD_LDTR                               0x80C
652 #define VMX_VMCS_GUEST_FIELD_TR                                 0x80E
653 /** @} */
654
655 /** @name VMCS field encoding - 16 bits host fields
656  * @{
657  */
658 #define VMX_VMCS_HOST_FIELD_ES                                  0xC00
659 #define VMX_VMCS_HOST_FIELD_CS                                  0xC02
660 #define VMX_VMCS_HOST_FIELD_SS                                  0xC04
661 #define VMX_VMCS_HOST_FIELD_DS                                  0xC06
662 #define VMX_VMCS_HOST_FIELD_FS                                  0xC08
663 #define VMX_VMCS_HOST_FIELD_GS                                  0xC0A
664 #define VMX_VMCS_HOST_FIELD_TR                                  0xC0C
665 /** @}          */
666
667 /** @name VMCS field encoding - 64 bits host fields
668  * @{
669  */
670 #define VMX_VMCS_HOST_FIELD_PAT_FULL                            0x2C00
671 #define VMX_VMCS_HOST_FIELD_PAT_HIGH                            0x2C01
672 #define VMX_VMCS_HOST_FIELD_EFER_FULL                           0x2C02
673 #define VMX_VMCS_HOST_FIELD_EFER_HIGH                           0x2C03
674 #define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL                     0x2C04      /**< MSR IA32_PERF_GLOBAL_CTRL */
675 #define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH                     0x2C05      /**< MSR IA32_PERF_GLOBAL_CTRL */
676 /** @}          */
677
678
679 /** @name VMCS field encoding - 64 Bits control fields
680  * @{
681  */
682 #define VMX_VMCS_CTRL_IO_BITMAP_A_FULL                          0x2000
683 #define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH                          0x2001
684 #define VMX_VMCS_CTRL_IO_BITMAP_B_FULL                          0x2002
685 #define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH                          0x2003
686
687 /* Optional */
688 #define VMX_VMCS_CTRL_MSR_BITMAP_FULL                           0x2004
689 #define VMX_VMCS_CTRL_MSR_BITMAP_HIGH                           0x2005
690
691 #define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL                     0x2006
692 #define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH                     0x2007
693 #define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL                      0x2008
694 #define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH                      0x2009
695
696 #define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL                     0x200A
697 #define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH                     0x200B
698
699 #define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL                        0x200C
700 #define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH                        0x200D
701
702 #define VMX_VMCS_CTRL_TSC_OFFSET_FULL                           0x2010
703 #define VMX_VMCS_CTRL_TSC_OFFSET_HIGH                           0x2011
704
705 /** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
706 #define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL                       0x2012
707 #define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH                       0x2013
708
709 /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
710 #define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL                      0x2014
711 #define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH                      0x2015
712
713 /** Extended page table pointer. */
714 #define VMX_VMCS_CTRL_EPTP_FULL                                 0x201a
715 #define VMX_VMCS_CTRL_EPTP_HIGH                                 0x201b
716
717 /** VM-exit phyiscal address. */
718 #define VMX_VMCS_EXIT_PHYS_ADDR_FULL                            0x2400
719 #define VMX_VMCS_EXIT_PHYS_ADDR_HIGH                            0x2401
720 /** @} */
721
722
723 /** @name VMCS field encoding - 64 Bits guest fields
724  * @{
725  */
726 #define VMX_VMCS_GUEST_LINK_PTR_FULL                            0x2800
727 #define VMX_VMCS_GUEST_LINK_PTR_HIGH                            0x2801
728 #define VMX_VMCS_GUEST_DEBUGCTL_FULL                            0x2802      /**< MSR IA32_DEBUGCTL */
729 #define VMX_VMCS_GUEST_DEBUGCTL_HIGH                            0x2803      /**< MSR IA32_DEBUGCTL */
730 #define VMX_VMCS_GUEST_PAT_FULL                                 0x2804
731 #define VMX_VMCS_GUEST_PAT_HIGH                                 0x2805
732 #define VMX_VMCS_GUEST_EFER_FULL                                0x2806
733 #define VMX_VMCS_GUEST_EFER_HIGH                                0x2807
734 #define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL                    0x2808      /**< MSR IA32_PERF_GLOBAL_CTRL */
735 #define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH                    0x2809      /**< MSR IA32_PERF_GLOBAL_CTRL */
736 #define VMX_VMCS_GUEST_PDPTR0_FULL                              0x280A
737 #define VMX_VMCS_GUEST_PDPTR0_HIGH                              0x280B
738 #define VMX_VMCS_GUEST_PDPTR1_FULL                              0x280C
739 #define VMX_VMCS_GUEST_PDPTR1_HIGH                              0x280D
740 #define VMX_VMCS_GUEST_PDPTR2_FULL                              0x280E
741 #define VMX_VMCS_GUEST_PDPTR2_HIGH                              0x280F
742 #define VMX_VMCS_GUEST_PDPTR3_FULL                              0x2810
743 #define VMX_VMCS_GUEST_PDPTR3_HIGH                              0x2811
744 /** @} */
745
746
747 /** @name VMCS field encoding - 32 Bits control fields
748  * @{
749  */
750 #define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS                         0x4000
751 #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS                        0x4002
752 #define VMX_VMCS_CTRL_EXCEPTION_BITMAP                          0x4004
753 #define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK                      0x4006
754 #define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH                     0x4008
755 #define VMX_VMCS_CTRL_CR3_TARGET_COUNT                          0x400A
756 #define VMX_VMCS_CTRL_EXIT_CONTROLS                             0x400C
757 #define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT                      0x400E
758 #define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT                       0x4010
759 #define VMX_VMCS_CTRL_ENTRY_CONTROLS                            0x4012
760 #define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT                      0x4014
761 #define VMX_VMCS_CTRL_ENTRY_IRQ_INFO                            0x4016
762 #define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE                   0x4018
763 #define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH                        0x401A
764 /** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
765 #define VMX_VMCS_CTRL_TPR_THRESHOLD                             0x401C
766 /** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
767 #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2                       0x401E
768 /** @} */
769
770
771 /** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
772  * @{
773  */
774 /** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
775 #define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT            RT_BIT(0)